JPH04337595A - Memory card - Google Patents

Abstract

PURPOSE:To develop a memory card capable of expanding a storage capacity logically unlimitedly without increasing the number of pins. CONSTITUTION:A memory card 1 is used connected to a certain information equipment. This memory card is provided with a common memory 3 capable of storing several kinds of data, an atribute memory 2 for storing the physical information of a card including the memory capacity of this common memory, an address register capable of specifying an address enabling accessing to the above-mentioned common memory 3 and a control circuit 4 capable of controlling the reading and writing of the atribute memory and the common memory. A necessary address is set on the address register by the control circuit 4 based on the memory capacity information of the common memory 3 from the atribute memory 2.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a memory card used as an external memory device for information equipment such as an electronic still camera, a personal computer, or a word processor.
The present invention relates to memory cards, and particularly to memory cards that can store still image data and large amounts of data.

0002

[Prior Art] Recently, IC memory cards have been widely used in various technical fields, such as external devices for information devices such as electronic still cameras, personal computers, and word processors. Used as a memory device. Regarding this IC memory card, for example, the ``IC Memory Card Guidelines (Standard Specifications for Personal Computers, Memory Cards/Pin Connectors)'', Version 3 (May 1989) was published by the ``Japan Electronics Industry Promotion Association''. ) has been proposed as the latest one. Conventionally, IC memory cards have either a direct bus system that allows the input/output pins of the internal IC memory chip to be used as direct interface signals, or an I/O bus system that can be easily connected to the input/output bus of a microcomputer.
However, since the former has a large number of pins and is difficult to connect to an input/output bus, the I/O bus method is often used.

This I/O bus type memory card has a built-in address register for pointing to an arbitrary address of the internal memory chip. In the I/O bus system shown in version 3 of the above-mentioned guidelines, this register has 3 bytes, and 2 bits are allocated to specify this 3-byte register. This 2
Regarding the bits, when viewed from the outside of the memory card, the 0th address (“0” “0”) is the register for the lower address, the first address (“0” “1”) is the register for the middle address, and the second address (“0”) is the register for the middle address. 1" and "0") are used to specify the upper address register. Also, the third address (“1” “1”
) is a register for memory access, and by specifying "read" or "write" to this register, you can read or write to the memory at the address specified by the address register. Can be done.

However, as mentioned above, the conventional address register is 3 bytes (1 byte = 8 bits), so the maximum address that can be expressed is "2" to the 24th power, and 1
Only addresses up to 6,777,216 can be specified. In other words, this memory card can only be loaded with a storage capacity of 16 megabytes. Note that, as described above, in order to designate the 3-byte register, it is sufficient to have two lines as address lines.

[0005]

[Problem to be Solved by the Invention] In this way, the conventional I/O bus type memory card according to the above guidelines
In the case of a hard disk, the maximum storage capacity is only 16 megabytes, so there is a drawback that when used as a medium for storing large amounts of data, such as in an electronic still camera, the capacity becomes insufficient. Therefore, in order to secure a maximum storage capacity of 16 megabytes or more, it is conceivable to add an address register within the IC memory card. For example, if the address register is 4 bytes, the maximum address that can be handled is 2 to the 32nd power = 4,294,967,296.
This means that a large amount of memory capacity can be handled. However, in this case, the number of control registers is 5, and the number of pins is 3.
This has the disadvantage that the number of pins on the C memory card increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory card that eliminates the above-mentioned drawbacks and can significantly increase storage capacity without increasing the number of pins.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a common memory capable of storing various data in a memory card used while being connected to a certain information device. an attribute memory that stores physical information of the card including the memory capacity of the common memory; and an address register that can specify an address that can access the common memory;
and a control circuit capable of controlling reading and writing of the attribute memory and the common memory, and the control circuit is capable of setting a necessary address in the address register based on information about the memory capacity of the common memory from the attribute memory. We propose a memory card featuring:

[0008]

[Operation] In the present invention, the physical information of the card including the capacity of the common memory is stored in the attribute memory in advance by changing the combination of control signals, and when accessing the common memory for reading or writing. Next, an address is set in an address register in which a common memory address can be set based on physical information from the attribute memory. Further, the address register has the same bit width as the bus depending on the memory capacity. Therefore, even if the common memory has a logically infinite memory capacity, it can be accessed from the outside.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the internal structure of the memory card of the present invention. FIG. 2 is a diagram showing the correspondence of signals to pins of the same memory card, and basically follows the above-mentioned guidelines.

The memory card 1 shown in FIG. 1 includes an attribute memory 2, a common memory 3, a control circuit 4 for controlling these, a power supply control circuit 5, and a backup battery 6. The attribute memory 2 stores, for example, the memory types (ROM,
This memory stores physical information of the card, such as RAM, EEPROM, etc.), read/write speed, and capacity of the common memory 3, and connects the control circuit 4 to control lines, address lines,
Connected by data bus line.

The common memory 3 is a memory that mainly stores data, and similarly to the above, the common memory 3 is connected to the control circuit 4 by a control line,
They are connected by address lines and data bus lines. The control circuit 4 sends a card enable CE, control signals C0 and C1, a read signal RD, a write signal WR, and a ready signal RDY/B to an external circuit (for example, a card controller).
SY, write inhibit signal WP, data address bus D
0 to D7 are connected for input/output. Also,
The control circuit 4 includes an address register that can set an address according to the capacity of the common memory 3.

Here, as shown in FIG. 2, the memory card 1 has pin numbers "1, 20" connected to GND, and pin numbers "2 to 20" connected to GND.
9”, data address bus D0 to D7, number “10”
Power supply Vcc to number “11”, program supply Vp to number “11”
p, ready signal RDY/BSY to number "12", number "
Card enable CE to "13", control signals C0, C1 to numbers "14, 15", read signal RD to number "16"
, the write signal WR is assigned to the number "17", the write inhibit signal WP is assigned to the number "18", and the battery check Vbat is assigned to the number "19". Further, in FIG. 2, control signals C0 and C1 numbered "14, 15" are control signals used in the embodiment of the present invention, and details of the control contents will be explained in the explanation of FIG. 4 below. The power supply control circuit 5 is connected to an external power supply through a power supply line Vcc and GND, and is also configured to be able to give a signal Vbat indicating the battery status to the external circuit, and further internally connects to a backup battery 6. connected, attribute memory 2,
Power is supplied to the common memory 3 and the control circuit 4.

FIG. 3 is an explanatory diagram schematically showing an embodiment of the present invention. The circuit shown in FIG. 3 is configured inside the control circuit 4, and includes a plurality of address registers 41, 42, 43, . . . corresponding to the capacity of the common memory 3. These address registers 41, 42, 43...
has a size large enough to specify the address of the capacity of the common memory 3.

FIG. 4 is an explanatory diagram shown to explain the functional assignment of control signals C0 and C1 of the present invention. Control signal C
1 is “0” and attribute memory 2 is specified, and “
Common memory 3 can be specified with “1”. Then, the control signals C0, C1, R/W are “0”
0” “R””, the address register of attribute memory 2 is read, and the control signals C0, C1, R/W are ““
0", "0", and "W"" can be written to the address register of the attribute memory 2. In addition, the control signal C0,
C1, R/W is attribute with “1” “0” “R”
Reads data from memory 2 and sends control signals C0 and C1.
, R/W writes data to the attribute memory 2 with "1", "0", and "W". Furthermore, control signals C0, C
1. If R/W is "0""1""R", read the address register of common memory 3 and send control signal C0,
If C1 and R/W are "0", "1", and "W", it can be written to the address register of the common memory 3. Control signals C0, C1, and R/W are ““1” “1” “R”
Then, data is read from the common memory 3, and if the control signals C0, C1, and R/W are "1", "1", and "W", then
Data can be written to the common memory 3.

The operation of such an embodiment will be explained. Figure 5
6 is a time chart showing the read timing of the attribute memory 2 of the memory card, and FIG. 6 is a time chart showing the write timing of the attribute memory 2 of the memory card. Also, FIG. 7 is a time chart showing the read timing of the common memory 3 of the memory card.
FIG. 8 is a time chart showing the write timing of the common memory 3 of the memory card.

{Reading operation of attribute memory 2} First, the reading operation of attribute memory 2 will be explained with reference to FIG. Card controller (
(not shown) inputs card enable CE "1" to the memory card 1 (time t0).

Next, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R/W are set to “0”.
0""WR (see also FIG. 4, the same applies hereinafter)" (times t1 to t2) and sets addresses in the address registers 41 and 42 of the attribute memory 2 (times t1 to t2).

Next, the card controller sets the control signals C0, C1, and R/W to "0", "1", and "R" ((
From time t3), the contents of the attribute memory 2 are sequentially read from the set address (from time t3). This allows the card controller to know the capacity, type, read/write speed, etc. of the attribute memory 2 and common memory 3.

{Write operation of attribute memory 2} When it is necessary to write to the attribute memory 2 based on the above information, the card controller performs a write operation on the memory card 1 as shown in FIG. -Doenable C
E "1" is input (time t10).

Next, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R/W are set to “0”.
0""W"" (see also FIG. 4, the same applies hereinafter)" (times t11 to t12), the address is set in the address registers 41, 42, 43, etc. of the attribute memory 2. (Time t11-t12).

Next, the card controller sets the control signals C0, C1, and R/W to "1", "0", and "W", and (
From time t13), writing is controlled to the attribute memory 2 sequentially from the set address. (Time point t13~). From this, attribute memory 2 has
Necessary data is written.

{Reading operation of common memory 3} Next,
The read operation of the common memory 3 will be explained with reference to FIG. The card controller (not shown) inputs card enable CE "1" to the memory card 1 (time t20).

Next, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R/W are set to “0”.
1""R" (see also FIG. 4, the same applies hereinafter)" (times t21 to t22), addresses are set in the address registers 41, 42, 43, etc. of the common memory 3 (times t21 to t22). ~t22). As a result, one of the address registers 41, 42, 43, . . . is designated.

[0024] Next, by the card controller, the
As shown in , the control signals C0, C1, and R/W are “1”.
1""R"" (from time t23), data is read from the common memory 3 according to the addresses written in the address registers 41, 42, 43, . . . (from time t23). As a result, the address registers 41, 42, 43, . . .
・Since you can set the necessary address for , the capacity can theoretically be expanded infinitely. At this time, address register 41
, 42, 43, . . . must have a sufficient number to specify the address.

{Write operation to the common memory 3 of the memory card} Next, the write operation to the common memory 3 of the memo card 1 will be explained with reference to FIG. Car
The card controller (not shown) inputs card enable CE "1" to the memory card 1 as shown in FIG.
Time t30).

Next, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R/W are set to “0”.
1""W" (see also FIG. 4, the same applies hereinafter)" (times t31 to t32), the address register 41,
Addresses are written to 42, 43, etc. (at time t
31-t32). This is because the larger the memory capacity, the more times it is necessary to write in 8-bit units.

Next, by the card controller, the image shown in FIG.
As shown in , the control signals C0, C1, and R/W are “1”.
1""W"" (from time t33), and writes data to the common memory 3 according to the addresses written in the address registers 41, 42, 43, etc. (from time 33). .

In order to set the address of the common memory 3 in this way, the capacity of the common memory 3 is known from the information from the attribute memory 2, and the address registers 41, 42, 43, . Since the address necessary for ... can be written multiple times depending on its size, common memory 3 can be accessed even if the capacity of common memory 3 is logically infinite. be able to.

The present embodiment operates as described above, and the memory capacity can be theoretically expanded to infinity without increasing the number of pins and without causing any electrical problems.

[0030]

[Effects of the Invention] As described above, according to the present invention, the combination of control signals is changed, the capacity of the common memory is stored in the attribute memory, and an address register is provided that can access the memory capacity. Therefore, there is an effect that the memory capacity can be theoretically increased to an infinite limit without increasing the number of pins of the memory card.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card of the present invention.

FIG. 2 is an explanatory diagram for explaining the correspondence of signals to pins of the memory card of the present invention.

FIG. 3 is a diagram for explaining main parts of an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a configuration example of a control signal used in an embodiment of the present invention.

FIG. 5 is a time chart diagram for explaining a write operation of an attribute memory.

FIG. 6 is a time chart diagram for explaining the read operation of the attribute memory.

FIG. 7 is a time chart diagram for explaining a write operation of the common memory.

FIG. 8 is a time chart diagram for explaining the read operation of the common memory.

[Explanation of symbols]

1 Memory card 2 Attribute memory 3 Common memory 4 Control circuit 5 Power control circuit 6 Backup battery

Claims (1)

[Claims] [Claim 1] A memory card used by being connected to a certain information device includes a common memory that can store various data, and physical information of the card including the memory capacity of this common memory. The control circuit includes an attribute memory for storing an attribute memory and an address register capable of specifying an address at which the common memory can be accessed, and is capable of controlling reading and writing of the attribute memory and the common memory. - A memory card characterized in that a necessary address can be set in an address register based on information about the memory capacity of a common memory from a host memory.