JPH04336348A - Memory card - Google Patents

Abstract

PURPOSE:To develop the memory card which can greatly be increased in storage capacity without increasing the number of pins. CONSTITUTION:The memory card is used while connected to constant information equipment. This memory card is equipped with address registers 41-47 where the address of an attribute memory stored with the physical information of the card or a common memory stored with data can be set and which correspond to memory capacity of bit width equal to the data buses of those memories and an address control register 40 which specifies the address registers 41-47, bit to bit, and specifies which of the attribute memory and common memory is accessed. The memory card is so constituted that after memory control data is written in the address control register 40, the address can be written in the address registers 41-47 specified by the address control register 40.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a memory card used as an external memory device for information equipment such as an electronic still camera, a personal computer, or a word processor.
The present invention relates to memory cards, and particularly to memory cards that can store still image data and large amounts of data.

0002

[Prior Art] Recently, IC memory cards have come into widespread use in various technical fields, such as in information devices such as electronic still cameras, personal computers, and word processors. Used as an external memory device. Regarding this IC memory card, for example, the ``IC Memory Card Guidelines (Standard Specifications for Personal Computers, Memory Cards/Pin Connectors)'', Version 3 (May 1989) was published by the ``Japan Electronics Industry Promotion Association''. ) has been proposed as the latest one. Conventionally, IC memory cards have a direct connection bus system in which the input/output pins of the internal IC memory chip can be used as direct interface signals.
An I/O bus method is adopted that can be easily connected to the input/output bus of a microcomputer, but the former has a large number of pins and is difficult to connect to the input/output bus, so
Buses are often used.

This I/O bus type memory card has a built-in address register for pointing to an arbitrary address of the internal memory chip. In the I/O bus system shown in version 3 of the above-mentioned guidelines, this register has 3 bytes, and 2 bits are allocated to specify this 3-byte register. This 2
Regarding the bits, when viewed from the outside of the memory card, the 0th address (“0” “0”) is the register for the lower address, the first address (“0” “1”) is the register for the middle address, and the second address (“0”) is the register for the middle address. 1" and "0") are used to specify the upper address register. Also, the third address (“1” “1”
) is a register for memory access, and by specifying "read" or "write" to this register, you can read or write to the memory at the address specified by the address register. Can be done.

However, as mentioned above, the conventional address register is 3 bytes (1 byte = 8 bits), so the maximum address that can be expressed is "2" to the 24th power, and 1
Only addresses up to 6,777,216 can be specified. In other words, this memory card can only be loaded with a storage capacity of 16 megabytes. Note that, as described above, in order to designate the 3-byte register, it is sufficient to have two lines as address lines.

[0005]

[Problem to be Solved by the Invention] In this way, the conventional I/O bus type memory card according to the above guidelines
In the case of a hard disk, the maximum storage capacity is only 16 megabytes, so there is a drawback that when used as a medium for storing large amounts of data, such as in an electronic still camera, the capacity becomes insufficient. Therefore, in order to secure a maximum storage capacity of 16 megabytes or more, it is conceivable to add an address register within the IC memory card. For example, if the address register is 4 bytes, the maximum address that can be handled is 2 to the 32nd power = 4,294,967,296.
This means that a large amount of memory capacity can be handled. However, in this case, the number of control registers is 5, and the number of pins is 3.
This has the disadvantage that the number of pins on the C memory card increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory card that eliminates the above-mentioned drawbacks and can significantly increase storage capacity without increasing the number of pins.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an attribute for storing physical information of the card in a memory card used while being connected to a certain information device. It is possible to set the address of the main memory or the common memory that stores data, and also has multiple address registers corresponding to the memory capacity with the same bit width as the data bus of those memories, and these address registers are set in bit correspondence. It is equipped with an address control register that allows you to specify an address register and specify whether to access attribute memory or common memory. After writing memory control data to the address control register, A memory card is proposed which is characterized in that an address can be written in a register.

[0008]

[Operation] In the present invention, the combination of control signals is changed, each bit of the address control register is made to correspond one-to-one with the address register, and the address register is specified with the address control register, and then the address register is specified with the address register. The address can be set.

[0009]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the internal structure of the memory card of the present invention. FIG. 2 is a diagram showing the correspondence of signals to pins of the same memory card, and basically follows the above-mentioned guidelines.

The memory card 1 shown in FIG. 1 includes an attribute memory 2, a common memory 3, a control circuit 4 for controlling these, a power supply control circuit 5, and a backup battery 6. The attribute memory 2 is a memory that stores physical information of the card, and is connected to the control circuit 4 through control lines, address lines, and data bus lines.

The common memory 3 is a memory for storing data, and is connected to the control circuit 4 via control lines, address lines, and data bus lines in the same way as described above. The control circuit 4 sends a card enable CE, control signals C0 and C1, a read signal RD, a write signal WR, and a ready signal RDY/BSY to an external circuit (for example, a card controller).
, write inhibit signal WP, data/address bus D0~
D7 is connected for input/output.

Here, as shown in FIG. 2, the memory card has pin numbers "1, 20" connected to GND, and pin numbers "2 to 9" connected to GND.
” to data/address buses D0 to D7, number “10” to power supply Vcc, number “11” to program supply Vpp
, ready signal RDY/BSY to number “12”, number “1”
Card enable CE is set to "3", control signals C0 and C1 are set to numbers "14 and 15", read signal RD is set to number "16",
Write signal WR to number "17", write prohibition signal WP to number "18", battery check V to number "19"
bat is assigned. Further, in FIG. 2, control signals C0 and C1 at numbers "14 and 15" are control signals used in the embodiment of the present invention, and details of the control contents will be explained in the explanation of FIG. 4 below. Note that the power supply control circuit 5
is connected to the external power supply through the power line Vcc and GND, and is also configured to be able to give a signal Vbat indicating the battery status to the external circuit.Furthermore, it is internally connected to the backup battery 6, and the attribute - supplies power to the memory 2, common memory 3, and control circuit 4;

FIG. 3 is an explanatory diagram schematically showing an embodiment of the present invention. The circuit shown in this figure is configured inside the control circuit 4, and consists of an address control register 40 and seven address registers 41-47. Address registers 41 to 47 are 7 of the address control registers 40.
Each bit corresponds to an address register 41 to 47, and when the corresponding bit of the address control register 40 is set to "1", the corresponding address register is selected. That is, the first bit of the address control register 40 controls the address register 41, the second bit controls the address register 42, the third bit controls the address register 43, and the fourth bit controls the address register 44. ,
The 5th bit specifies the address register 45, the 6th bit specifies the address register 46, the 7th bit specifies the address register 47, and the 8th bit specifies either attribute memory 2 or common memory 3. This is for specifying which one to access.

FIG. 4 is an explanatory diagram shown to explain the functional assignment of control signals C0 and C1 of the present invention. Control signal C
0, C1, R/W is “0” “0” “R”, “0” “0”
”“W”, “0”“1”“R”” and ““1”“0”“
If it becomes "R", no control will be performed, but the control signals C0 and C1 become "
“0” “1” “W”” address control register 4
0 write control. Control signal C0, C1, R/W
When it becomes "1", "0", and "W", address write control is performed. Control signals C0, C1, R/W are ““1” “1”
When it becomes "R", it is controlled to read memory data, and when it becomes "1" and "1""R", it is controlled to write memory data.

The operation of such an embodiment will be explained. Figure 5
6 is a time chart shown to explain the read timing of the memory card, and FIG. 6 is a time chart shown to explain the write timing of the memory card.

{Reading operation of the common memory 3 of the memory card} First, the reading operation of the common memory 3 of the memory card 1 will be explained with reference to FIG. The card controller (not shown) inputs card enable CE "1" to the memory card 1 (time t0).

Next, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R/W are set to “1”.
0""W" (see also FIG. 4, the same applies hereinafter)", the address control register 40 is made writable (from time t1 to t2), and a predetermined address register designation data is written to the address control register 40. (time t
1 to t2). At this time, the 8th bit of the address control register 40 is set to "0". As a result, any one of the address registers 41 to 47 is designated.

Next, by the card controller, the image shown in FIG.
As shown in , the control signals C0, C1, and R/W are “0”.
1""W"" ((times t3 to t4), an address is written to any of the address registers 41 to 47 set in the address control register 40 (times t3 to t4).

Next, the card controller sets the control signals C0, C1, and R/W to "1" and "1" as shown in FIG.
"R" (from time t5), data can be read from the common memory 3 for the set address (from time t5). At this time, by automatically updating the addresses of the address control register 40 and the address registers 41 to 47 each time data is read for the set address,
Once reading starts, there is no need to specify the address again, and data at consecutive addresses can be read. If the 8th bit of the address control register 40 is set to "1", the data in the attribute memory 2 can be read out in the same manner as described above.

{Write operation of the common memory 3 of the memory card} Next, the write operation of the common memory 3 of the memory card 1 will be explained with reference to FIG. The card controller (not shown) inputs card enable CE "1" to the memory card 1 (time t0).

Next, the card controller is shown in FIG.
As shown in the figure, the control signals C0, C1, and R/W are set to “1”.
0""W"" (see also FIG. 4, the same applies hereinafter) makes the address control register 40 writable (from time t1 to t2), and stores a predetermined address register designation data in this address control register 40. (time t
1 to t2). At this time, the 8th bit of the address control register 40 is set to "0". As a result, any one of the address registers 41 to 47 is designated.

[0022] Next, by the card controller, the
As shown in , the control signals C0, C1, and R/W are “0”.
1” “W”” (time t3 to t4), the address register 4 set in the address control register 40
Addresses are written from 1 to 47. (Time t
3-t4).

Next, the card controller sets the control signals C0, C1, and R/W to "1" and "1" as shown in FIG.
"W" (time t5), data can be written to the common memory 3 at the set address (from time t5). At this time, each time data is written to the set address, the address control register 4 is
By automatically updating the addresses of 0 and address registers 41 to 47, there is no need to specify them again once writing starts. If the 8th bit of the address control register 40 is set to "1", data can be written into the attribute memory 2 by operating in the same manner as described above.

The present embodiment operates in this way, and the memory capacity can be expanded to a maximum of 2 to the 56th power bytes without increasing the number of pins and without any electrical problems.

[0025]

As described above, according to the present invention, the combination of control signals is changed and each bit of the address control register is made to correspond one-to-one to the address register.
In addition, since the address can be set in the address register after specifying the address register in the address control register, the memory capacity can be increased without increasing the number of pins on the memory card. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory card of the present invention.

FIG. 2 is an explanatory diagram for explaining the correspondence of signals to pins of the memory card of the present invention.

FIG. 3 is a diagram for explaining main parts of an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a configuration example of a control signal used in an embodiment of the present invention.

FIG. 5 is a time chart diagram for explaining a read operation of a memory card.

FIG. 6 is a time chart diagram for explaining a write operation of a memory card.

[Explanation of symbols]

1 Memory card 2 Attribute memory 3 Common memory 4 Control circuit 5 Power control circuit 6 Backup battery 40 Address control register 41-47 Address register

Claims (1)

[Claims] Claim 1: In a memory card used by being connected to a certain information device, an address of an attribute memory for storing physical information of the card or a common memory for storing data can be set, In addition, it is possible to specify multiple address registers according to the memory capacity with the same bit width as the data bus of these memories, and to specify the address register by associating these address registers with bits. The memory control register is equipped with an address control register that allows you to specify which memory is to be accessed.
1. A memory card characterized in that an address can be written into a designated address register after data is written into the memory card.