JPH04335298A - Static ram circuit - Google Patents

Abstract

PURPOSE:To realize a high integration and to reduce a layout area by reducing the number of load elements. CONSTITUTION:Loads of bit lines B1 and B2, which vary resistance values by operating modes, are configured by the circuit including P channel MOS transistors MP1 and MP2. Three level values are set for the gate voltage of the P channel MOS transistors MP1 and MP2 during a write in period, a recovery period after the write period and the read period and change the conductance for the corresponding period.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static RAM circuit, and more particularly to a static RAM circuit in which the resistance of a bit line load is variable depending on the operating state.

0002

2. Description of the Related Art Conventionally, such a static RAM circuit has a bit line load circuit constituting a plurality of P-channel MOS transistors (hereinafter referred to as P-MOS) and a plurality of N-channel MOS transistors (hereinafter referred to as N-MOS). ) are connected to the bit line pair.

FIG. 3 is a bit line load circuit diagram of a static RAM circuit for explaining a conventional example. As shown in FIG. 3, in the conventional static RAM circuit, a memory cell 1 is connected to the intersection of a word line WD and bit lines B1 and B2 (B1 and B2 are complementary to each other), and the static RAM The bit line load circuit has multiple P
-MOS MP6 to MP9 and multiple N-MOS M
It is composed of N3 and MN4. In such a static circuit, at the time of reading, the content of the memory cell 1 selected by the word line WD is read out to the bit line pair B1, B2, and the read/write control signal input terminal 3 receives a low level read signal. A write control signal is input, and a high-level write recovery control signal is also input to the write recovery control signal input terminal 4. As a result, P-MOS MP6 and MP7 become conductive (on), and P-MOS MP8 and MP9 become non-conductive (off). Therefore, in the lead state,
P-MOS MP6 and N-MOSMN3, and P-
A load circuit is configured by connecting MOS MP7 and N-MOS MN4 in parallel.

On the other hand, in the write state, data on the bit line pair B1, B2 of the selected row is transferred to the word line W.
It is written to memory cell 1 selected by D, but
At this time, a high level is input to the read/write control signal input terminal 3 and the write recovery control signal input terminal 4
Since a high level is input to P-MOS MP6
, MP7 and P-MOS MP8, MP9 are turned off, and a load circuit is configured only with N-MOS MN3, MN4. The internal resistance of the N-MOS MN3 and MN4 during conduction is set to be sufficiently larger than that of the P-MOS.

[0005] Also, during reading for a certain period of time immediately after writing, the write recovery control signal 4 becomes low level, so P-MOS MP8, MP8 is turned on, and P-MOS MP6, MP8 and P-M
It becomes a load circuit in which OS MP7, MP9 and N-MOS MN3 and MN4 are connected in parallel. These P-MO
The internal resistance of S MP8 and MP9 during conduction is P-MOS
It is set sufficiently smaller than MP6 and MP7.

In this way, the bit line load during reading is
As a result of reading data from the memory cell 1, the bit lines B1 and B2, which have fallen to a low level, must be pulled back to a high level for the next cycle of reading, so a somewhat large conductance is required. Furthermore, in the recovery state immediately after writing, the bit lines B1 and B2, which were set to a lower level than in the read state due to writing, are pulled back to a high level, so a larger conductance than in the read state is required. On the other hand, the bit line load during writing only needs to be maintained at a level on the high level side of unselected rows so that the level of the bit line does not drop due to leakage current. Therefore, it is advantageous for the bit line load conductance during writing to be as small as possible in order to reduce current consumption. Also, the conduction resistance of each transistor is (P-MOS
MP8, MP9): (P-MOS MP6, MP7
): (N-MOS MN3, MN4) = 1:10:2
The size of the transistor is set so that the ratio is 0.

[0007]

[Problems to be Solved by the Invention] In the conventional static RAM circuit described above, the bit line load circuit is composed of three transistors per bit line, so the number of load elements is large, which hinders high integration. It has the disadvantage of becoming. Furthermore, an N-channel transistor that is connected to a bit line and needs to have a small conductance must have a long channel length, and a P-channel transistor that needs to have a sufficiently large conductance must have a large transistor size. Therefore, in any case, there is a drawback that the layout area becomes large.

An object of the present invention is to provide a static RAM circuit which can achieve high integration by reducing the number of load elements and can also reduce the layout area.

[0009]

[Means for solving the problems] Static R of the present invention
In the AM circuit, a bit line load whose resistance value is variable depending on the operation mode is configured with a circuit including a P channel MOS transistor, and the gate voltage of the P channel MOS transistor is changed from the high level voltage of the bit line to the P channel MOS transistor during writing. The threshold voltage of the channel transistor is set slightly lower than the value minus the threshold voltage, and when recovering immediately after writing, it is set to the ground level or a lower voltage, and when reading, it is set to the voltage between the high level value of the bit line and the ground level. Configured by setting it to a value.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a bit line load circuit diagram of a static RAM circuit for explaining one embodiment of the present invention. As shown in FIG. 1, this embodiment includes a plurality of word lines WD and a plurality of pairs of bit lines B1, . 2, a P-MOS MP1 connected to the bit line B1 for load resistance, and a P-MOS MP2 connected to the bit line 2. -MOS
A load resistance control signal input terminal 2 is connected to the common gate of MP1 and MP2. To this load resistance control signal input terminal 2, the power supply voltage (VDD) -1.0V is applied during writing, (VDD) -2.0V is applied during reading, and 0V is applied during write recovery, and the bit line load P
-Controls MOS MP1 and MP2.

In such a static RAM circuit,
During writing, the P-MOS MP1 and MP2 connected to the load resistance control signal input terminal 2 are almost non-conductive, resulting in a sufficiently small conductance. Further, during write recovery, P-MOS MP1 and MP2 are almost completely conductive, and a sufficiently large conductance can be obtained. On the other hand, when reading, P-MOS MP1
, the internal resistance of MP2 takes an intermediate value between that during write and during write recovery. At this time, the internal resistance is set to an optimal value for recovery from low level to high level during reading. In this way, P-MOS M in each state
The conduction resistance of P1 and MP2 is P-MOS so that the ratio is 10:20:1 during read: write: recovery.
The transistor sizes of MP1 and MP2 are set.

FIG. 2 is a diagram of a load resistance control signal generation circuit that generates the load resistance control signal in FIG. As shown in FIG. 2, this generation circuit generates a ternary load control signal from the read/write control signal from the read/write control signal input terminal 3 and the write recovery control signal from the write recovery control signal input terminal 4. First, when reading, a low level is input to the read/write control signal input terminal 3,
Furthermore, since a low level is input to the write recovery control signal input terminal 4, a VDD level is input to the gate of the P-MOS MP4. Therefore, the load control signal output terminal 9 is connected from the power supply voltage VDD to the P-MOS MP
4. Subtract the threshold voltage of MP5 and N-MOS MN2, and further apply a minute voltage △V by P-MOS MP4.
The lowered value will be output. The value of ΔV can be arbitrarily selected depending on the size ratio of transistors MP4, MP5, and MN2.

On the other hand, during writing, a high level is input to the read/write control signal input terminal 3, a low level is input to the write recovery control signal input terminal 4, and P-
Since the ground level is input to the gate of MOS MP4, the load resistance control signal output terminal 5 is connected from VDD to P-MOS MP4, MP5 and N-MOS MN2.
The value obtained by subtracting the threshold voltage is output. Furthermore, during write recovery, a low level is input to the read/write control signal input terminal 3 and a high level is input to the write recovery control signal input terminal 4, so that the ground level is output to the load resistance control signal output terminal 9. Ru.

[0015] In this embodiment, the bit line load is explained as one P-channel transistor, but the present invention is not limited to this. It's okay.

[0016]

As explained above, in the static RAM circuit of the present invention, the P-channel transistor of the bit line load circuit consisting of a variable load including a P-channel transistor is connected to the power supply voltage VDD, the ground level, and the intermediate point between VDD and the ground level. This is a variable bit line load method that changes the load resistance of the bit line during read, write, and write recovery by controlling with a three-level signal, reducing the number of bit line load elements. This has the effect of increasing the degree of integration and reducing the layout area.

[Brief explanation of drawings]

FIG. 1 is a bit line load circuit diagram of a static RAM circuit for explaining one embodiment of the present invention.

FIG. 2 is a diagram of a load resistance control signal generation circuit that generates the load resistance control signal in FIG. 1;

[Fig. 3] Static RA to explain a conventional example
It is a bit line load circuit diagram of M circuit.

[Explanation of symbols]

1 Memory cell 2 Load resistance control signal input terminal 3 Read/write control signal input terminal 4 Write recovery control signal input terminal 5 Load resistance control signal output terminal WD Word line B1, B2 Bit line

Claims (1)

[Claims] 1. A bit line load whose resistance value is made variable depending on the operation mode is constituted by a circuit including a P-channel MOS transistor, and the gate voltage of the P-channel MOS transistor is changed from the high level voltage of the bit line to the bit line load during writing. The threshold voltage of the P-channel transistor is set slightly lower than the value minus the threshold voltage, and when recovering immediately after writing, it is set to the ground level or a lower voltage, and when reading, it is set to the voltage between the high level value of the bit line and the ground level. A static RAM circuit characterized in that it is set to a value of .