JPH0433475A - Horizontal phase synchronizing circuit - Google Patents

Horizontal phase synchronizing circuit

Info

Publication number
JPH0433475A
JPH0433475A JP14114390A JP14114390A JPH0433475A JP H0433475 A JPH0433475 A JP H0433475A JP 14114390 A JP14114390 A JP 14114390A JP 14114390 A JP14114390 A JP 14114390A JP H0433475 A JPH0433475 A JP H0433475A
Authority
JP
Japan
Prior art keywords
horizontal
output
synchronization
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14114390A
Other languages
Japanese (ja)
Other versions
JPH0720204B2 (en
Inventor
Takaaki Ishii
孝明 石井
Nobukazu Hosoya
細矢 信和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2141143A priority Critical patent/JPH0720204B2/en
Publication of JPH0433475A publication Critical patent/JPH0433475A/en
Publication of JPH0720204B2 publication Critical patent/JPH0720204B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the display from being fluctuated even in the case of on-screen indication at non-signal input by giving an output of a voltage controlled oscillator to a clock input of a horizontal counter at detection of a synchronizing signal and giving an output of a fixed oscillator at non-detection of a synchronizing signal. CONSTITUTION:In the case of non-signal input in which no video signal is inputted to a video input terminal 5, since no horizontal synchronizing signal is obtained from a synchronizing separator circuit 6, a phase lock is unlocked from a PLL circuit and a synchronizing detection circuit 11 detects asynchronizing state. Then a lst changeover switch 15 is thrown to the position of a contact (b) and an output of a fixed oscillator 12 is a clock input to the horizontal counter 13. Since the PLL circuit is always active even at non-signal input, horizontal synchronization is applied momentarily when a succeeding video signal is inputted and when the synchronization state is detected by the synchronizing detection circuit 11, the output of a voltage controlled oscillator 7 is selected immediately for the clock input of the horizontal counter 13. Thus, the image is not fluctuated even in the case of ON-screen display at non-signal input and stable display is obtained.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は液晶テレビや液晶プロジェクタに用いて好適な
水平位相同期回路に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a horizontal phase synchronization circuit suitable for use in liquid crystal televisions and liquid crystal projectors.

(ロ)従来の技術 液晶テレビや液晶プロジェクタに使用される液晶パネル
の駆動回路としては例えば第3図に示すものがある。
(b) Prior Art An example of a drive circuit for a liquid crystal panel used in a liquid crystal television or a liquid crystal projector is shown in FIG.

同図は液晶TV装置に用いられるアクティブマトリクス
液晶パネルによる液晶表示装置の駆動回路を示す図であ
り、この様な回路は例えば特開昭57−41078号公
報に記載されている。
This figure shows a driving circuit for a liquid crystal display device using an active matrix liquid crystal panel used in a liquid crystal TV device, and such a circuit is described in, for example, Japanese Patent Laid-Open No. 57-41078.

同図において、アクティブマトリクス型の液晶パネル(
1)は×方向にn列、Y方向にm行の画素ヲ有シ、mX
n個のアモルファスシリコン(a−si)よりなるTP
T (薄膜トランジスタ) (la)及び液晶電極(1
b)が図示の如くマトリクス状に接続され、各行(G1
.G2−Gm)及び各列(Dl、 [)2・・−Dn)
は夫々、行ドライバ(2)及び列ドライバ(3)に接続
されている。前記行ドライバはm段のシフトレジスタ(
2a)及び出力回路(2b)により構成され、前記列ド
ライバはn段のシフトレジスタ(3a)、サンプルホー
ルド回路(3b)及び出力回路(3c)により構成され
る。(4)は同期制御回路であり、水平同期信号(Hp
)及び垂直同期信号(Vp)に基づいて、第1、第2ス
タートパルス(STI )(Sr1)及び第1、第2ク
ロツクパルス(CPI)(CF2)を作成する。
In the figure, an active matrix liquid crystal panel (
1) has n columns of pixels in the x direction and m rows of pixels in the y direction, mX
TP made of n amorphous silicon (a-si)
T (thin film transistor) (la) and liquid crystal electrode (1
b) are connected in a matrix as shown in the figure, and each row (G1
.. G2-Gm) and each column (Dl, [)2...-Dn)
are connected to a row driver (2) and a column driver (3), respectively. The row driver is an m-stage shift register (
2a) and an output circuit (2b), and the column driver is composed of an n-stage shift register (3a), a sample and hold circuit (3b), and an output circuit (3c). (4) is a synchronization control circuit, which is a horizontal synchronization signal (Hp
) and the vertical synchronization signal (Vp), first and second start pulses (STI) (Sr1) and first and second clock pulses (CPI) (CF2) are generated.

第4図は行ドライバの各波形を示す図であり同図(a)
は映像信号を表わし、垂直同期信号(Vp)及び水平同
期信号(Hp)が重畳されている。図中、Tは垂直同期
信号区間、T、は垂直帰線区間、T。
FIG. 4 is a diagram showing each waveform of the row driver, and the figure (a)
represents a video signal, on which a vertical synchronization signal (Vp) and a horizontal synchronization signal (Hp) are superimposed. In the figure, T is a vertical synchronizing signal period, T is a vertical retrace period, T.

は映像信号区間である。is the video signal section.

シフトレジスタ(2a)には第4図(b)(c)に示す
垂直同期信号に同期した第1スタートパルス(STI)
及び水平同期信号に同期した第1クロツクパルス(CP
I)が与えられ、各行G3、G、−・・には(d )(
e )(f)に示す如(IH(1水平期間)づつずらさ
れた電圧波形が印加される。この電圧波形により水平帰
線区間において各行のT P T (la)を順次オン
させ各画素に液晶駆動電圧を印加する。
The shift register (2a) receives a first start pulse (STI) synchronized with the vertical synchronization signal shown in Fig. 4 (b) and (c).
and the first clock pulse (CP
I) is given, and each row G3, G, --... has (d)(
e) As shown in (f), a voltage waveform shifted by IH (one horizontal period) is applied. This voltage waveform turns on T P T (la) in each row sequentially in the horizontal retrace interval, and applies it to each pixel. Apply liquid crystal drive voltage.

一方、列ドライバ(3)の各部波形は第5図に示すよう
になる。列ドライブは各IH区間において同じ動作をく
りかえす。第7図(a)はT、におけるIH区間を引き
延ばして描いた映像信号である。図中、T、は水平同期
信号区間及び水平帰線区間、T、は映像情報の含まれる
区間である。
On the other hand, the waveforms of each part of the column driver (3) are as shown in FIG. The column drive repeats the same operation in each IH section. FIG. 7(a) is a video signal drawn by extending the IH section at T. In the figure, T is a horizontal synchronizing signal interval and a horizontal retrace interval, and T is an interval in which video information is included.

シフトレジスタ(3a)には第5図(b)(c)に示す
水平同期信号に同期した第2スタートパルス(Sr1)
及びその周期τ= T 、 / nの周波数の第2クロ
ツクパルスが与えられ、シフトレジスタ(3a)の各段
の出力には同図(d )(e )(f )に示すように
順次τづつずらされたパルスが出力される。サンプルホ
ールド回路(3b)の各段は対応する各段の前記シフト
レジスタの出力により制御され、該出力の立下がりによ
り映像信号の電圧値をサンプルし次のサンプル時まで(
IHの間)ホールドする。出力回路(3c)はサンプル
ホールド回路の出力を受けて緩衝増巾し・列電極を駆動
する。
The shift register (3a) receives a second start pulse (Sr1) synchronized with the horizontal synchronization signal shown in FIGS. 5(b) and (c).
A second clock pulse with a period of τ = T, /n is applied, and the output of each stage of the shift register (3a) is sequentially shifted by τ as shown in (d), (e), and (f) of the same figure. The output pulse is output. Each stage of the sample and hold circuit (3b) is controlled by the output of the shift register of the corresponding stage, and the voltage value of the video signal is sampled by the falling edge of the output, and the voltage value of the video signal is sampled until the next sample (
Hold during IH). The output circuit (3c) receives the output of the sample and hold circuit, buffers and amplifies it, and drives the column electrodes.

上述の回路において列ドライバ(3)に供給される第2
タロツクパルスは受信した水平同期信号に位相同期した
n倍のf)l(fllは水平周波数)とする必要があり
、この様なりロック発生のための回路は、特公昭63−
46636号公報(H04N5/66)にも示されるよ
うに、入力映像信号の水平同期信号にPLLループによ
り位相同期する水平位相同期回路が使用される。
In the circuit described above the second
The tarlock pulse needs to be n times f)l (fll is the horizontal frequency) which is phase synchronized with the received horizontal synchronization signal.
As also shown in Publication No. 46636 (H04N5/66), a horizontal phase synchronization circuit is used which performs phase synchronization with a horizontal synchronization signal of an input video signal using a PLL loop.

また、上述の水平位相同期回路の出力によりオンスクリ
ーン表示の位置制御信号等が作成される。
Further, a position control signal for on-screen display, etc. is created by the output of the above-mentioned horizontal phase synchronization circuit.

しかしながら、上述の水平位相同期回路では、無信号入
力時にはPLLループが水平同期信号にロックすること
ができない。従って、無信号時にオンスクリーン表示を
した場合、文字信号の像がゆれてしまい、良好な表示が
行なえないという欠点があった。
However, in the horizontal phase synchronization circuit described above, the PLL loop cannot be locked to the horizontal synchronization signal when no signal is input. Therefore, when on-screen display is performed when there is no signal, the image of the character signal is distorted, resulting in a disadvantage that good display cannot be performed.

(ハ)発明が解決しようとする課題 本発明は上述の点に鑑み為されたものであり、無信号入
力時にオンスクリーン表示を行っても表示がゆれること
のない水平位相同期回路を提供するものである。
(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points, and provides a horizontal phase synchronization circuit that does not cause display fluctuation even when on-screen display is performed when no signal is input. It is.

(ニ)課題を解決するための手段 本発明は少なくとも水平同期信号を取り出す同期分離回
路と、電圧制御型発振器と、 この電圧制御型発振器の出力を分周する分周器と、 前記水平同期信号と前記分周器出力とを比較する位相比
較器と、 入力されるクロックをカウントし水平周波数の水平駆動
パルスを作成する水平カウンタと、前記電圧制御型発振
器の基本発振周波数と略等しい周波数で発振する固定発
振器と、 前記水平同期信号と前記分周器出力とを入力とし同期状
態を検出する同期検出回路と、この同期検出回路出力に
より前記電圧制御型発振器出力若しくは前記固定発振器
出力を選択して前記水平カウンタのタロツク入力とする
第1切換スイッチとからなる水平位相同期回路である。
(D) Means for Solving the Problems The present invention provides at least a synchronization separation circuit for extracting a horizontal synchronization signal, a voltage-controlled oscillator, a frequency divider for frequency-dividing the output of the voltage-controlled oscillator, and the horizontal synchronization signal. and the frequency divider output; a horizontal counter that counts input clocks and creates horizontal drive pulses at a horizontal frequency; a fixed oscillator that receives the horizontal synchronization signal and the frequency divider output, and a synchronization detection circuit that receives the horizontal synchronization signal and the frequency divider output and detects a synchronization state; This is a horizontal phase synchronization circuit consisting of a first changeover switch which is used as a tally clock input of the horizontal counter.

(ホ)作 用 本発明では、水平カウンタのクロック入力を同期信号検
出時には電圧制御型発振器出力とし、同期信号非検出時
には固定発振器出力とする様に作用する。
(E) Function The present invention operates so that the clock input of the horizontal counter is set to the voltage-controlled oscillator output when a synchronizing signal is detected, and is set to the fixed oscillator output when the synchronizing signal is not detected.

(へ)実施例 以下、図面に従い本発明の一実施例を説明する。(f) Example An embodiment of the present invention will be described below with reference to the drawings.

第1図は本実施例における水平位相同期回路のブロック
図、第2図は同タイムチャートであり、図中、(5)は
映像信号入力端子、(6)は映像信号から水平同期信号
を分離する同期分離回路である。(7)は基本発振周波
数がnf、、の電圧制御型発振器、(8)はこの発振器
出力を1 / n分周する分周器、(9)はこの分周器
出力と前記水平同期信号とを位相比較する位相比較器、
(10)はこの位相比較器出力を平滑して前記電圧制御
型発振器(7)を制御するローパスフィルタであり、こ
れらによりPLL回路が構成される。
Figure 1 is a block diagram of the horizontal phase synchronization circuit in this embodiment, and Figure 2 is the same time chart. In the figure, (5) is a video signal input terminal, and (6) is a horizontal synchronization signal that separates the video signal This is a synchronous separation circuit. (7) is a voltage-controlled oscillator with a basic oscillation frequency of nf, (8) is a frequency divider that divides the output of this oscillator by 1/n, and (9) is a frequency divider that divides the output of this oscillator by 1/n. a phase comparator, which compares the phase of
(10) is a low-pass filter that smoothes the output of this phase comparator to control the voltage-controlled oscillator (7), and these constitute a PLL circuit.

また、(11)は前記水平同期信号と前記分周器出力と
を比較し前記分周器出力が正規の水平周波数になってい
るか否かを検出する同期検出回路、(12)は前記電圧
制御型発振器の基本発振周波数と略等しい発振周波数を
有する固定発振器、(13)は入力されるクロックをカ
ウントし、水平周波数の水平駆動パルスを作成する水平
カウンタ、(15)は前記同期検出回路(11)からの
同期検出信号により制御され、同期時、前記電圧制御型
発振器出力を、非同期時、前記固定発振器出力を選択し
て前記水平カウンタのタロツク入力とする第1切換スイ
ッチ、(16)は同じく前記同期検出信号により制御さ
れ、同期時、前記分周器(8)で作成される水平周期の
リセットパルスを、非同期時、前記水平カウンタのセル
フリセットパルスを選択して前記水平カウンタのリセッ
ト入力とする第2切換スイッチである。
Further, (11) is a synchronization detection circuit that compares the horizontal synchronization signal and the frequency divider output and detects whether or not the frequency divider output has a regular horizontal frequency; (12) is the voltage control circuit; A fixed oscillator having an oscillation frequency substantially equal to the basic oscillation frequency of the oscillator, (13) a horizontal counter that counts input clocks and creates a horizontal drive pulse of a horizontal frequency, and (15) the synchronization detection circuit (11). ), and selects the voltage-controlled oscillator output during synchronization and selects the fixed oscillator output during non-synchronization, and selects the output from the fixed oscillator as the tally input of the horizontal counter; Controlled by the synchronization detection signal, during synchronization, the horizontal period reset pulse created by the frequency divider (8) is selected, and during non-synchronization, the self-reset pulse of the horizontal counter is selected and used as the reset input of the horizontal counter. This is the second selector switch.

次に上記回路の動作について第2図と共に説明する。Next, the operation of the above circuit will be explained with reference to FIG.

まず、映像入力端子(5)に映像信号が入力されると、
同期分離回路(6)で水平同期信号(イ)が分離され、
位相比較器(9)及び同期検出回路(11)へ供給され
る。ここで、PLL回路が動作し前記電圧制御発振器出
力は前記水平同期信号(イ)に位相が同期する。
First, when a video signal is input to the video input terminal (5),
The horizontal synchronization signal (a) is separated by the synchronization separation circuit (6),
The signal is supplied to a phase comparator (9) and a synchronization detection circuit (11). Here, the PLL circuit operates and the voltage controlled oscillator output is synchronized in phase with the horizontal synchronization signal (a).

また、前記同期検出回路では前記分周器(8)出力(ロ
)と前記水平同期信号(イ)とが比較され、“H”の同
期検出信号(ニ)が出力される。すると、第1切換スイ
ッチ(15)は接点(a)側に切換わり前記電圧制御型
発振器出力が水平カウンタ(13)のクロック入力とさ
れる。更に、第2切換スイッチ(16)は接点(c)側
に切換わり前記分周器(8)のリセットパルス(ハ)が
前記水平カウンタのリセット入力となる。そして、前記
水平カウンタでは前記水平同期信号と位相同期し、位相
やパルス幅が異なる複数の水平駆動パルス(へ)())
(チ)が作成され、オンスクリーン表示の表示位置制御
や、列ドライバ(図示省略)に供給されるクロックパル
スに利用される。
Further, the synchronization detection circuit compares the output (b) of the frequency divider (8) with the horizontal synchronization signal (a), and outputs an "H" synchronization detection signal (d). Then, the first changeover switch (15) is switched to the contact (a) side, and the output of the voltage controlled oscillator is used as the clock input of the horizontal counter (13). Further, the second changeover switch (16) is switched to the contact (c) side, and the reset pulse (c) of the frequency divider (8) becomes the reset input of the horizontal counter. Then, the horizontal counter generates a plurality of horizontal drive pulses (to) ()) that are phase-synchronized with the horizontal synchronization signal and have different phases and pulse widths.
(h) is created and used for display position control of on-screen display and clock pulses supplied to column drivers (not shown).

次に映像入力端子(6)に映像信号が入力されない無信
号入力時、前記同期分離回路(6)からjよ水平同期信
号が得られなくなるためPLL回路は位相クロックがは
ずれると共に前記同期検出回路(11)は非同期状態を
検出して同期検出信号(ニ)は“L”となる。従って、
前記第1切換スイッチ(15)は接点(b)側に切換わ
り前記固定発振器(12)出力が前記水平カウンタ(1
3)のクロック入力となる。更に、第2切換スイッチ(
16)は接点(d)側に切換わり前記水平カウンタ(1
3)のリセット入力にはこの水平カウンタ内で作成され
るセルフリセットパルス(ホ)となる。
Next, when no video signal is input to the video input terminal (6), no horizontal synchronization signal can be obtained from the synchronization separation circuit (6), so the phase clock of the PLL circuit is lost and the synchronization detection circuit ( 11) detects an asynchronous state and the synchronization detection signal (d) becomes "L". Therefore,
The first changeover switch (15) is switched to the contact (b) side, and the output of the fixed oscillator (12) is switched to the horizontal counter (1).
3) becomes the clock input. Furthermore, the second changeover switch (
16) switches to the contact (d) side and the horizontal counter (1
The reset input of 3) is a self-reset pulse (e) generated within this horizontal counter.

よって、水平カウンタ(13)は固定発@器(12)か
らの安定したnf++のクロックをカウントして前記水
平駆動パルスを作成するためこの状態でオンスクリーン
表示を行っても像ゆれが発生することなく安定な表示が
得られる。
Therefore, since the horizontal counter (13) counts the stable nf++ clock from the fixed oscillator (12) to create the horizontal drive pulse, image shaking may occur even if on-screen display is performed in this state. A stable display can be obtained.

尚、この無信号入力時においてもPLL回路は常に動作
しているため、次に映像信号が入力された時、瞬時に水
平同期をかけることができ、同期検出回路(11)にて
同期状態が検出されれば直ちに水平カウンタ(13)の
クロック入力は電圧制御型発振器(7)出力に切換わり
、入力の水平同期信号に位相ロックした水平駆動パルス
によりオンスクリーン表示を行なうことができる。
The PLL circuit is always operating even when no signal is input, so the next time a video signal is input, horizontal synchronization can be applied instantaneously, and the synchronization detection circuit (11) detects the synchronization state. Immediately upon detection, the clock input of the horizontal counter (13) is switched to the output of the voltage controlled oscillator (7), and on-screen display can be performed using horizontal drive pulses phase-locked to the input horizontal synchronizing signal.

(ト)発明の効果 上述の如く本発明に依れば、無信号入力時にオンスクリ
ーン表示を行っても像がゆれることなく安定した表示を
得ることができる。
(g) Effects of the Invention As described above, according to the present invention, even if on-screen display is performed when no signal is input, a stable display can be obtained without image fluctuation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における水平位相同期回路の
ブロック図、第2図は同タイムチャートである。 また、第3図は従来の液晶パネルの駆動回路を示す図、
第4図及び第5図は同タイムチャートである。 (7)・・・電圧制御型発振器、(11)・・・同期検
出回路、(12)・・・固定発振器、(13)・・・水
平カウンタ、(15)(16)・・・第1、第2切換ス
イッチ。
FIG. 1 is a block diagram of a horizontal phase synchronization circuit according to an embodiment of the present invention, and FIG. 2 is a time chart thereof. In addition, FIG. 3 is a diagram showing a conventional liquid crystal panel drive circuit.
FIG. 4 and FIG. 5 are the same time charts. (7)...Voltage controlled oscillator, (11)...Synchronization detection circuit, (12)...Fixed oscillator, (13)...Horizontal counter, (15) (16)...First , second changeover switch.

Claims (2)

【特許請求の範囲】[Claims] (1)少なくとも水平同期信号を取り出す同期分離回路
と、 電圧制御型発振器と、この電圧制御型発振器の出力を分
周する分周器と、 前記水平同期信号と前記分周器出力とを比較する位相比
較器と、 入力されるクロックをカウントし水平周波数の水平駆動
パルスを作成する水平カウンタと、前記電圧制御型発振
器の基本発振周波数と略等しい周波数で発振する固定発
振器と、 前記水平同期信号と前記分周器出力とを入力とし同期状
態を検出する同期検出回路と、 この同期検出回路出力により前記電圧制御型発振器出力
若しくは前記固定発振器出力を選択して前記水平カウン
タのクロック入力とする第1切換スイッチとからなる水
平位相同期回路。
(1) A synchronization separation circuit that extracts at least a horizontal synchronization signal, a voltage-controlled oscillator, a frequency divider that divides the output of the voltage-controlled oscillator, and a comparison between the horizontal synchronization signal and the frequency divider output. a phase comparator, a horizontal counter that counts input clocks and creates a horizontal drive pulse of a horizontal frequency, a fixed oscillator that oscillates at a frequency substantially equal to the basic oscillation frequency of the voltage controlled oscillator, and the horizontal synchronization signal. a synchronization detection circuit that receives the frequency divider output as an input and detects a synchronization state; and a first circuit that selects the voltage-controlled oscillator output or the fixed oscillator output based on the output of the synchronization detection circuit and uses the output as a clock input for the horizontal counter. A horizontal phase synchronization circuit consisting of a changeover switch.
(2)前記同期検出回路出力により前記分周器で作成さ
れるリセットパルス若しくは前記水平カウンタのセルフ
リセットパルスを選択して前記水平カウンタのリセット
入力とする第2切換スイッチを備える請求項1記載の水
平位相同期回路。
(2) A second changeover switch that selects a reset pulse created by the frequency divider or a self-reset pulse of the horizontal counter based on the output of the synchronization detection circuit and sets the selected one as the reset input of the horizontal counter. Horizontal phase synchronization circuit.
JP2141143A 1990-05-29 1990-05-29 Horizontal phase synchronization circuit Expired - Lifetime JPH0720204B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2141143A JPH0720204B2 (en) 1990-05-29 1990-05-29 Horizontal phase synchronization circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2141143A JPH0720204B2 (en) 1990-05-29 1990-05-29 Horizontal phase synchronization circuit

Publications (2)

Publication Number Publication Date
JPH0433475A true JPH0433475A (en) 1992-02-04
JPH0720204B2 JPH0720204B2 (en) 1995-03-06

Family

ID=15285168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2141143A Expired - Lifetime JPH0720204B2 (en) 1990-05-29 1990-05-29 Horizontal phase synchronization circuit

Country Status (1)

Country Link
JP (1) JPH0720204B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8885470B2 (en) 2005-04-08 2014-11-11 Qualcomm Incorporated Methods and systems for resizing multimedia content based on quality and rate information

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8885470B2 (en) 2005-04-08 2014-11-11 Qualcomm Incorporated Methods and systems for resizing multimedia content based on quality and rate information

Also Published As

Publication number Publication date
JPH0720204B2 (en) 1995-03-06

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