JPH04334218A - Multiplexing device - Google Patents

Abstract

PURPOSE:To obtain a multiplexing device where the number of the intra-device wirings of a data signal and a clock signal on a transmission-side and a reception-side in the digital multiplex device is reduced. CONSTITUTION:Tristate gate circuits 50, 70 and 90 are respectively provided on intra-device signal interface parts of plural channel parts 3, a multiplexing part 10 and a separation part 20. Then, the data signal and the clock signal on the transmission-side and the reception-side are alternately communicated by transmission/reception control signals 120 and 130 from a control part 40. Since the data signal and the clock signal on the transmission-side and the reception-side are communicated by using the same intra-device wiring, the number of the intra-device wirings can be reduced compared with that of a conventional multiplexing device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital synchronous multiplexing device, and more particularly to a device for multiplexing and demultiplexing digital signals.

0002

2. Description of the Related Art A conventional multiplexing device, as shown in FIG. The clocks are transmitted and received separately.

0003

However, in this conventional system, as the number of multiplexed channels increases, the number of exchanges between data signals and clock signals increases. Furthermore, when parallel transmission of signals is required due to byte multiplexing, the number of signals increases further, complicating signal wiring within the device, and causing problems in signal transmission characteristics.

In view of the above-mentioned drawbacks, the technical problem of the present invention is to provide a multiplexing device that reduces the number of wiring lines for data signals and clock signals on the transmitting side and receiving side within the device of a digital multiplexing device. It is to provide.

[0005]

According to the present invention, there is provided a plurality of channel sections having channel tri-state gate circuits on the transmitting side and receiving side, a multiplexing section having multiple tri-state gate circuits, and a separate tri-state gate circuit. the channel tri-state gate circuit, the multiple tri-state gate circuit, and the separate tri-state gate circuit are connected to each other for each channel, and the channel tri-state gate circuit on the transmitting side and the receiving side A multiplexing device is provided, comprising a control section that alternately operates the gate circuits in accordance with transmission and reception control signals to alternately communicate data signals and clock signals between the transmitting side and the receiving side. .

Further, according to the present invention, in the multiplexer, the transmitting side channel tri-state gate circuit converts the input low-speed signal at twice the signal speed based on the read clock signal from the multiplexer. the receiver channel tri-state gate circuit converts the signal back to the original low speed signal speed based on the double speed data signal and the clock signal from the separation unit. A multiplexing device is obtained, which is characterized in that it has.

Further, according to the present invention, in the multiplexing device, the multiplexing section converts the double speed data signals from the plurality of channel sections to the normal speed and then multiplexes the data signals, It has a multiplexing circuit that sends out a multiplexed signal, and the separation unit separates the multiplexed signal into the original low-speed signal and then converts it into the double data signal according to the reception control signal. , a multiplexing device is obtained, characterized in that the multiplexing device transmits data to the plurality of channel units.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

As shown in FIG. 1, a plurality of channel sections 3
The inputs and outputs of the channel tri-state gate 90 on the transmitting side and the receiving side in 0, the inputs and outputs of the multiplexing tri-state gate circuit 50 of the multiplexing section 10 and the separating tri-state gate circuit 70 of the separating section 20, connected to each channel.

The transmitting side tristate gate circuit and the receiving side tristate gate circuit of the channel tristate gate 90 are controlled to function alternately by a transmitting control signal 120 and a receiving control signal 130 from the control section 40, respectively. There is.

As described above, in order to share the internal signal wiring for data signals and clock signals between the transmitting side and the receiving side,
The signal rate required is twice that required by conventional multiplexers.

Therefore, the transmitting circuit 100 of the channel section 30
is provided with a conversion circuit that processes the input low-speed signal at twice the signal speed according to the read clock signal from the multiplexer 10 within the time that the tri-state gate circuit functions. Similarly, the receiving circuit 110 is provided with a conversion circuit that returns the double-speed data signal and clock signal from the separation section 20 to the original low-speed signal speed.

The multiplexing circuit 60 of the multiplexing section 10 converts the double speed data signal from the channel section 30 once to the normal speed, multiplexes it, and sends out the multiplexed signal to the transmission path. After the demultiplexing circuit 80 of the demultiplexing section 20 demultiplexes the multiplexed signal from the transmission path into normal low-speed signal speed signals, the demultiplexing circuit 80 demultiplexes the multiplexed signal from the transmission path into two signals according to the reception control signal 130 from the control section 40.
It is converted into a double data signal and sent to the channel section 30.

[0014]

Effects of the Invention As explained above, the present invention performs multiplexing and demultiplexing by using tri-state gate circuits provided in the multiplexing section, the demultiplexing section, and the channel section to transmit data and clock signals necessary for multiplexing and demultiplexing within the device. By alternately performing operation and separation operation, the internal wiring of data and clock signals can be reduced to 1/2.
It has the effect of reducing the number to 2.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a block diagram showing an example of a conventional multiplexing device.

[Explanation of symbols]

10 Multiplexing section 20 Separating section 30 Channel section 40 Control section 50 Multiplexing tri-state gate circuit 60
Multiplexing circuit 70 Separation section tri-state gate circuit 80
Separation circuit 90 Channel section tri-state gate circuit 1
00 Transmission circuit 110 Receiving circuit 120 Transmission control signal 130 Reception control signal

Claims (3)

[Claims] 1. A plurality of channel sections having transmitter and receiver channel tri-state gate circuits, a multiplexing section having multiple tri-state gate circuits, and a separating section having separate tri-state gate circuits; The channel tristate gate circuit, the multiplex tristate gate circuit, and the separate tristate gate circuit are connected to each other for each channel, and each of the channel tristate gate circuits on the transmitting side and the receiving side is controlled by a transmission/reception control signal. 1. A multiplexing device comprising: a control section which is operated alternately to cause data signals and clock signals to be communicated alternately between a transmitting side and a receiving side. 2. The multiplexing device according to claim 1,
The transmitting side channel tri-state gate circuit has a conversion circuit that processes an input low-speed signal at twice the signal speed based on a read clock signal from the multiplexer,
Multiplexing characterized in that the receiving side channel tri-state gate circuit has a conversion circuit that returns to the original low speed signal speed based on the double speed data signal and the clock signal from the separation section. Device. 3. The multiplexing device according to claim 2,
The multiplexing section includes a multiplexing circuit that converts the double-speed data signals from the plurality of channel sections to a normal speed, multiplexes the signals, and sends out a multiplexed signal, and the demultiplexing section , a multiplexing device characterized in that, after separating the multiplexed signal into the original low-speed signal, the multiplexed signal is converted into the double data signal and sent to the plurality of channel sections according to the reception control signal. .