JPH04334093A - Manufacture of multilayered wiring board - Google Patents

Manufacture of multilayered wiring board

Info

Publication number
JPH04334093A
JPH04334093A JP10301991A JP10301991A JPH04334093A JP H04334093 A JPH04334093 A JP H04334093A JP 10301991 A JP10301991 A JP 10301991A JP 10301991 A JP10301991 A JP 10301991A JP H04334093 A JPH04334093 A JP H04334093A
Authority
JP
Japan
Prior art keywords
oxide film
cu2o
wiring board
cuo
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10301991A
Other languages
Japanese (ja)
Other versions
JP3123109B2 (en
Inventor
Risaburo Yoshida
吉田 利三郎
Akira Muraki
村木 明良
Yasuhiro Sakuma
佐久間 保弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP10301991A priority Critical patent/JP3123109B2/en
Publication of JPH04334093A publication Critical patent/JPH04334093A/en
Application granted granted Critical
Publication of JP3123109B2 publication Critical patent/JP3123109B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To obtain the manufacturing method of a multilayered wiring board wherein imperfect bonding of a wiring layer and an adhesive insulating layer of a circuit board for an inner layer can be prevented, and treatment agent in the course of manufacturing is hard to be left on the interface of the above layers. CONSTITUTION:When a multilayered wiring board is manufactured by forming an oxide film 2 composed of CuO and Cu2O on the surface by oxidizing a wiring layer 1 of a circuit board for an inner layer which circuit board has the wiring layer 1 of a copper foil, and by laminating a plurality of said circuit boards via adhesive insulating layers, oxidizing is performed under the condition that the ratio Cu2O/CuO in the oxide film becomes higher than or equal to 80%. When the percentage of Cu2O having large acid resistance is increased, the acid resistance of the oxide film 2 is also increased, so that the oxide film 2 of the wiring layer 1 is hard to be dissolved, when oxidizing is suitably performed in the course of manufacturing a multilayered wiring board. Thereby haloing phenomenon wherein metal copper of the wiring layer 2 is partially exposed can be restrained.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、接着性絶縁層を介し積
層された複数枚の内層用回路板を備える多層配線板とそ
の製造方法に係り、特に、内層用回路板に設けられた銅
箔製の配線層と上記接着性絶縁層との接着不良が防止で
きると共に製造工程途上で適用された適宜処理剤が上記
配線層と接着性絶縁層との界面に残留し難い多層配線板
とその製造方法に関する。
[Field of Industrial Application] The present invention relates to a multilayer wiring board comprising a plurality of inner layer circuit boards laminated with adhesive insulating layers interposed therebetween, and a method for manufacturing the same. A multilayer wiring board capable of preventing poor adhesion between a foil wiring layer and the adhesive insulating layer, and in which an appropriate treatment agent applied during the manufacturing process is difficult to remain at the interface between the wiring layer and the adhesive insulating layer, and the same. Regarding the manufacturing method.

【0002】0002

【従来の技術】この種の多層配線板は、例えば、図4〜
図10に示すような各工程を経て製造されている。以下
その概略を説明すると、図4に示すように銅箔により形
成された配線層を有する複数枚の内層用回路板aを外層
用銅箔a1と共に接着性絶縁層(プリプレグ)bを介し
積層して一体化し、かつ、適宜穿設手段により図5に示
すようなスルーホールcを穿設(ドリリング)した後、
このスルーホールcの内壁面を銅箔にて覆うため銅によ
るスルーホールめっき処理を施して図6に示すようなめ
っき層dを積層体表面とスルーホールc内壁面にそれぞ
れ形成する。
[Prior Art] This type of multilayer wiring board is, for example, shown in FIGS.
It is manufactured through various steps as shown in FIG. To explain the outline below, as shown in FIG. 4, a plurality of inner layer circuit boards a having wiring layers formed of copper foil are laminated together with an outer layer copper foil a1 via an adhesive insulating layer (prepreg) b. After integrating the parts and drilling a through hole c as shown in FIG. 5 using an appropriate drilling means,
In order to cover the inner wall surface of the through hole c with copper foil, a through hole plating process with copper is performed to form a plating layer d as shown in FIG. 6 on the surface of the laminate and the inner wall surface of the through hole c, respectively.

【0003】次いで、このめっき層dの面上にスルーホ
ールc周辺の一部と配線層形成部位を除きフォトレジス
ト層eをパターン状に形成する(図7参照)と共に、こ
のフォトレジスト層eから露出する部位に銅・はんだめ
っき層fを形成(図8参照)し、かつ、上記フォトレジ
スト層eを除去した後、この銅・はんだめっき層fをマ
スクにして図9に示すように上記めっき層d等をエッチ
ングにより除去し、更にこれ等面上にソルダー・レジス
ト層gを成膜して図10に示すような多層配線板hを製
造する方法が採られている。
Next, a photoresist layer e is formed in a pattern on the surface of this plating layer d, excluding a part around the through hole c and the wiring layer formation area (see FIG. 7), and a photoresist layer e is formed from this photoresist layer e. After forming a copper/solder plating layer f on the exposed portion (see FIG. 8) and removing the photoresist layer e, the copper/solder plating layer f is used as a mask to remove the plating as shown in FIG. A method is adopted in which layers d and the like are removed by etching, and a solder resist layer g is further formed on these surfaces to produce a multilayer wiring board h as shown in FIG.

【0004】ところで、上記複数枚の内層用回路板aを
接着性絶縁層(プリプレグ)bを介して積層する際、内
層用回路板aに設けられた配線層が表面平滑な銅箔によ
り構成されているため上記接着性絶縁層bとの接着強度
が不十分となり配線層と接着性絶縁層bとが経時的に剥
離し易い欠点があった。
By the way, when the plurality of inner layer circuit boards a are laminated via adhesive insulating layers (prepreg) b, the wiring layer provided on the inner layer circuit board a is made of copper foil with a smooth surface. As a result, the adhesive strength with the adhesive insulating layer b is insufficient, resulting in a drawback that the wiring layer and the adhesive insulating layer b tend to separate over time.

【0005】このため、従来においては図11の(A)
〜(B)に示すように銅箔より成る配線層iの表面を、
例えば、水酸化ナトリウム(NaOH)が15〜25g
/l程度溶解されたアルカリ性亜塩素酸ナトリウム水溶
液等で酸化処理してCuOとCu2 Oより成る針状結
晶の酸化膜jを形成し、上記配線層iの表面を粗面化さ
せて接着性絶縁層bとの接着強度の向上を図る方法が採
られている。
For this reason, in the past, (A) in FIG.
~ As shown in (B), the surface of the wiring layer i made of copper foil is
For example, 15-25g of sodium hydroxide (NaOH)
An acicular crystal oxide film j consisting of CuO and Cu2O is formed by oxidation treatment with an alkaline sodium chlorite aqueous solution dissolved at a concentration of about /l, and the surface of the wiring layer i is roughened to form an adhesive insulator. A method has been adopted to improve the adhesive strength with layer b.

【0006】[0006]

【発明が解決しようとする課題】このような方法を採る
ことで全体的には配線層iと接着性絶縁層bとの接着強
度の向上が図れる反面、CuOとCu2 Oとで構成さ
れた酸化膜jはアルカリ溶液に対し耐性を有するものの
酸には比較的容易に溶解されてしまうため、多層配線板
の製造工程途上において図12(A)に示すようにスル
ーホールcの内壁面から露出する積層面が酸性の処理剤
に触れた場合(例えば上述したスルーホールめっき処理
の際、化学銅めっきに対する触媒性を付与するため塩酸
酸性のパラジウム・錫水溶液にて処理するような場合)
、その接触部位の酸化膜jが図12(B)に示すように
酸により溶解して上記配線層iの金属銅が露出され、図
13に示すようにピンク色のリングrがスルーホールc
の周縁に沿って形成される“ハローイング”と称される
現象が発生することがあった。
[Problem to be solved by the invention] By adopting such a method, the overall adhesive strength between the wiring layer i and the adhesive insulating layer b can be improved; Although the film j is resistant to alkaline solutions, it is relatively easily dissolved in acids, so it is exposed from the inner wall surface of the through hole c during the manufacturing process of the multilayer wiring board, as shown in FIG. 12(A). When the laminated surface comes into contact with an acidic treatment agent (for example, during the above-mentioned through-hole plating treatment, when the layer is treated with an acidic palladium/tin aqueous solution of hydrochloric acid to impart catalytic properties to chemical copper plating)
As shown in FIG. 12(B), the oxide film j at the contact portion is dissolved by acid to expose the metal copper of the wiring layer i, and the pink ring r is connected to the through hole c as shown in FIG.
A phenomenon called "haloing", which is formed along the periphery of the disk, sometimes occurs.

【0007】そして、この現象が発生すると図14に示
すようにスルーホールc内壁面の配線層iと接着性絶縁
層bとの界面に空隙sが形成されてしまうためこれ等間
の接着強度の低下が起こって経時的に剥離し易くなる問
題点があり、かつ、この空隙s内に上記処理剤が残留し
易くなるため多層配線板としての信頼性を著しく低下さ
せる問題点があった。
When this phenomenon occurs, a gap s is formed at the interface between the wiring layer i on the inner wall surface of the through hole c and the adhesive insulating layer b, as shown in FIG. There is a problem that deterioration occurs and the treatment agent tends to peel over time, and the processing agent tends to remain in the voids s, resulting in a problem that the reliability as a multilayer wiring board is significantly lowered.

【0008】このような技術的背景の下において本発明
者等が上記酸化膜jに耐酸性を付与する方法を鋭意研究
したところ、従来法において酸化膜jが耐酸性を示さな
い原因は酸により容易に溶解されるCuOが上記酸化膜
j中に多量に存在するためで、このCuOの比率を下げ
比較的耐酸性を有するCu2 Oの比率を上げることに
より酸化膜jに耐酸性を付与できることを見出し本発明
を完成するに至ったものである。
Against this technical background, the inventors of the present invention have conducted intensive research on a method for imparting acid resistance to the oxide film j, and have found that the reason why the oxide film j does not exhibit acid resistance in the conventional method is due to the presence of acid. This is because a large amount of CuO, which is easily dissolved, exists in the oxide film j, and it is possible to impart acid resistance to the oxide film j by lowering the ratio of CuO and increasing the ratio of Cu2O, which has relatively acid resistance. Heading This is what led to the completion of the present invention.

【0009】因みに、従来法における酸化膜中のCu2
 OのCuOに対する比(Cu2 O/CuO×100
)は30〜40%程度であり、また、上記ハローイング
の発生量(図13中、直径0.35mmのスルーホール
c周縁からの距離Lで示されるリングの幅により表示さ
れる)は平均で130〜150μm以上であり数百μm
になることもあった。
Incidentally, Cu2 in the oxide film in the conventional method
Ratio of O to CuO (Cu2O/CuO×100
) is about 30 to 40%, and the amount of haloing (indicated by the width of the ring indicated by the distance L from the periphery of the through hole c with a diameter of 0.35 mm in Fig. 13) is on average. 130 to 150 μm or more and several hundred μm
Sometimes it became.

【0010】そこで、本発明の課題とするところは、上
記ハローイングの発生量を100μm以下にすることに
より内層用回路板に設けられた銅箔製の配線層と上記接
着性絶縁層との接着不良が防止できると共に製造工程途
上で適用された適宜処理剤が上記配線層と接着性絶縁層
との界面に残留し難い多層配線板とその製造方法を提供
することにある。
[0010] Therefore, an object of the present invention is to improve the adhesion between the copper foil wiring layer provided on the inner layer circuit board and the adhesive insulating layer by reducing the amount of haloing generated to 100 μm or less. It is an object of the present invention to provide a multilayer wiring board which can prevent defects and which prevents a suitable treatment agent applied during the manufacturing process from remaining on the interface between the wiring layer and the adhesive insulating layer, and a method for manufacturing the same.

【0011】[0011]

【課題を解決するための手段】すなわち請求項1に係る
発明は、CuOとCu2 Oの酸化膜が表面に形成され
た銅箔製の配線層を有する内層用回路板が接着性絶縁層
を介し複数積層されて成る多層配線板を前提とし、上記
酸化膜中におけるCu2 O/CuOの比率が80%以
上に設定されていることを特徴とするものであり、他方
、請求項2に係る発明は、CuOとCu2 Oの酸化膜
が表面に形成された銅箔製の配線層を有する内層用回路
板が接着性絶縁層を介し複数積層されて成る多層配線板
を前提とし、上記酸化膜中におけるCu2 O/CuO
の比率が80%以上でその酸化膜の膜厚が0.4μm〜
0.8μmに設定されていることを特徴とするものであ
る。
[Means for Solving the Problems] In other words, the invention according to claim 1 is such that an inner layer circuit board having a wiring layer made of copper foil on the surface of which an oxide film of CuO and Cu2O is formed is connected via an adhesive insulating layer. The present invention is based on a multilayer wiring board formed by laminating a plurality of layers, and is characterized in that the ratio of Cu2O/CuO in the oxide film is set to 80% or more. , assumes a multilayer wiring board consisting of a plurality of inner layer circuit boards laminated with adhesive insulating layers interposed therebetween, each having a wiring layer made of copper foil with an oxide film of CuO and Cu2O formed on the surface. Cu2O/CuO
The ratio of 80% or more and the thickness of the oxide film is 0.4 μm ~
It is characterized by being set to 0.8 μm.

【0012】また、請求項3に係る発明は、銅箔により
形成された配線層を有する内層用回路板の上記配線層を
酸化処理してその表面にCuOとCu2 Oからなる酸
化膜を形成し、かつ、酸化処理されたこれ等複数枚の内
層用回路板を接着性絶縁層を介し積層して多層配線板を
製造する方法を前提とし、酸化膜中におけるCu2 O
/CuOの比率が80%以上となる条件で上記酸化処理
を施すことを特徴とするものであり、他方、請求項4に
係る発明は、銅箔により形成された配線層を有する内層
用回路板の上記配線層を酸化処理してその表面にCuO
とCu2 Oからなる酸化膜を形成し、かつ、酸化処理
されたこれ等複数枚の内層用回路板を接着性絶縁層を介
し積層して多層配線板を製造する方法を前提とし、酸化
膜中におけるCu2 O/CuOの比率が80%以上で
その酸化膜の膜厚が0.4μm〜0.8μmとなる条件
で上記酸化処理を施すことを特徴とするものである。
Further, the invention according to claim 3 is characterized in that the wiring layer of the inner layer circuit board having the wiring layer formed of copper foil is oxidized to form an oxide film consisting of CuO and Cu2O on the surface thereof. , and based on the method of manufacturing a multilayer wiring board by laminating a plurality of these oxidized inner layer circuit boards with adhesive insulating layers interposed therebetween, Cu2O in the oxide film is
The invention is characterized in that the oxidation treatment is performed under conditions such that the ratio of /CuO is 80% or more.On the other hand, the invention according to claim 4 provides an inner layer circuit board having a wiring layer formed of copper foil. The wiring layer is oxidized and CuO is deposited on its surface.
The method is based on the method of manufacturing a multilayer wiring board by forming an oxide film consisting of The oxidation treatment is performed under conditions such that the ratio of Cu2O/CuO is 80% or more and the thickness of the oxide film is 0.4 μm to 0.8 μm.

【0013】このような技術的手段において上記配線層
を酸化処理するための処理液としては、従来同様、アル
カリ性亜塩素酸ナトリウム水溶液やアルカリ性過硫酸カ
リ水溶液等がそのまま適用でき、また、その処理方法も
従来同様、予め脱脂処理された内層用回路板を上記処理
液に浸漬することによって行われる。
As the treatment liquid for oxidizing the wiring layer in such technical means, alkaline sodium chlorite aqueous solution, alkaline potassium persulfate aqueous solution, etc. can be used as is, as in the past, and the treatment method Similarly to the conventional method, the inner layer circuit board, which has been previously degreased, is immersed in the above-mentioned treatment liquid.

【0014】この場合、酸化膜中におけるCu2 O/
CuOの比率が80%以上になるようにその処理温度を
従来の90〜95℃からこれより低い70〜85℃程度
に、また、処理時間を従来の4分30秒からこれより短
い時間に設定することが望ましい。また、上記アルカリ
性亜塩素酸ナトリウム水溶液やアルカリ性過硫酸カリ水
溶液のアルカリ濃度を従来より高く設定することにより
簡単に達成することができる。
In this case, Cu2O/
The processing temperature was set from the conventional 90-95°C to a lower 70-85°C so that the CuO ratio was 80% or more, and the processing time was set from the conventional 4 minutes 30 seconds to a shorter time. It is desirable to do so. Moreover, it can be easily achieved by setting the alkaline concentration of the alkaline sodium chlorite aqueous solution or alkaline potassium persulfate aqueous solution higher than conventional ones.

【0015】尚、この様な条件で酸化処理を施した場合
にCu2 O/CuOの比率が80%以上となる理由に
ついては未だ十分に解明されてないが、上記条件に設定
すると『Cu2 O→CuO』の反応が抑制されCuO
の比率が下がることに起因しているものと推察している
[0015] The reason why the Cu2O/CuO ratio becomes 80% or more when oxidation treatment is carried out under these conditions is not yet fully elucidated, but when the above conditions are set, "Cu2O→ CuO” reaction is suppressed and CuO
We speculate that this is due to a decrease in the ratio of

【0016】また、2段階処理により上記Cu2 Oの
比率をより高めた酸化膜を形成してもよい。すなわち、
アルカリ性亜塩素酸ナトリウム水溶液やアルカリ性過硫
酸カリ水溶液等のアルカリ性酸化処理液で1回目の酸化
処理を施して銅箔表面にCu2 OとCuOの酸化膜を
形成する。この場合、Cu2 Oの結晶は酸化膜の表面
側から内側へ成長する傾向があるのに対しCuOの結晶
は酸化膜の内側から表面側へ成長する傾向があるため、
酸化膜の表面側はCuOの結晶で覆われ酸化膜の内側に
Cu2 Oの結晶が多く存在する傾向にある。従って、
この酸化膜表面をエッチング処理してその表面側に多量
に存在するCuO結晶を除去することにより酸化膜中の
Cu2 Oの比率を高めることができる。次に、1回目
のアルカリ性酸化処理液よりそのアルカリ濃度が高いア
ルカリ性酸化処理液で2回目の酸化処理を施すことによ
り酸化膜中のCu2 Oの比率を更に高めることが可能
となる。尚、最初の酸化処理と2回目の酸化処理とを共
にアルカリ濃度の高いアルカリ性酸化処理液で行っても
も当然のことながらよい。また、1回目の酸化処理で形
成した酸化膜のエッチング条件としてはこの酸化膜を溶
解しうる酸性溶液、例えば、希硫酸等のオキソ酸、希塩
酸に代表される塩基酸、ハロゲン化水素酸、アンモニア
水等が適用できる。また、このエッチングの処理時間は
その酸化膜の厚さが0.2μm前後、好ましくは0.1
5〜0.20μm程度残るまで、例えば、十数秒ないし
30秒間程度とする。
[0016] Furthermore, an oxide film having a higher proportion of Cu2O may be formed by a two-step process. That is,
A first oxidation treatment is performed using an alkaline oxidation treatment solution such as an alkaline sodium chlorite aqueous solution or an alkaline potassium persulfate aqueous solution to form an oxide film of Cu2O and CuO on the surface of the copper foil. In this case, Cu2O crystals tend to grow from the surface of the oxide film to the inside, whereas CuO crystals tend to grow from the inside of the oxide film to the surface.
The surface side of the oxide film tends to be covered with CuO crystals, and many Cu2O crystals exist inside the oxide film. Therefore,
By etching the surface of this oxide film to remove a large amount of CuO crystals present on the surface side, the ratio of Cu2O in the oxide film can be increased. Next, by performing a second oxidation treatment using an alkaline oxidation treatment liquid whose alkaline concentration is higher than that of the first alkaline oxidation treatment liquid, it becomes possible to further increase the ratio of Cu2O in the oxide film. It goes without saying that both the first oxidation treatment and the second oxidation treatment may be performed using an alkaline oxidation treatment solution with a high alkali concentration. In addition, the etching conditions for the oxide film formed in the first oxidation treatment include acidic solutions that can dissolve this oxide film, such as oxoacids such as dilute sulfuric acid, basic acids such as dilute hydrochloric acid, hydrohalic acid, and ammonia. Water etc. can be applied. In addition, the processing time for this etching is such that the thickness of the oxide film is approximately 0.2 μm, preferably 0.1 μm.
For example, about ten to 30 seconds until about 5 to 0.20 μm remains.

【0017】次に、上記酸化膜の膜厚については特に制
限はなく、従来同様、1.0μm前後の適宜値に設定可
能である。但し、この膜厚が大きくなると膜端部の露出
面積も大きくなり酸性の処理剤に触れた場合のサイドエ
ッチを受け易くなるため、好ましくは薄く設定した方が
よい。請求項2及び4に係る発明はこの様な観点からな
されたもので、酸化膜の膜厚を0.4μm〜0.8μm
程度に設定することで上記サイドエッチを受け難くなり
ハローイング現象が更に抑制される利点を有している。
Next, there is no particular restriction on the thickness of the oxide film, and it can be set to an appropriate value of about 1.0 μm, as in the prior art. However, as the film thickness increases, the exposed area at the end of the film also increases, making it more susceptible to side etching when it comes into contact with an acidic treatment agent, so it is preferable to set the film thinner. The inventions according to claims 2 and 4 have been made from such a viewpoint, and the thickness of the oxide film is set to 0.4 μm to 0.8 μm.
By setting the thickness to a certain level, it is less susceptible to the side etching and has the advantage of further suppressing the haloing phenomenon.

【0018】尚、上述の酸化処理がなされた内層用回路
板を積層した後における多層配線板の製造工程は任意で
あり、例えば、上述した従来法と同様な工程を経て製造
してもよいし他の工程を経てもよい。また、適用される
内層用回路板については、その一面側にのみ配線層を有
するものでもあるいは両面側にそれぞれ配線層を有する
ものでもよく任意である。
[0018] The manufacturing process of the multilayer wiring board after laminating the inner layer circuit boards that have been subjected to the oxidation treatment described above is optional, and for example, it may be manufactured through the same process as the conventional method described above. Other steps may also be performed. Further, the inner layer circuit board to which the present invention is applied may be one having a wiring layer only on one side or one having wiring layers on both sides.

【0019】[0019]

【作用】請求項1に係る発明によれば、配線層の表面に
形成された酸化膜中におけるCu2 O/CuOの比率
が80%以上に設定されており、また、請求項3に係る
発明によれば、酸化膜中におけるCu2 O/CuOの
比率が80%以上となる条件で配線層の酸化処理を施し
ていることから、耐酸性の大きいCu2 Oの割合が増
大する分その酸化膜の耐酸性が向上するため、多層配線
板の製造工程途上において適宜酸処理を施しても上記配
線層の酸化膜が溶解され難くなり、配線層の金属銅が部
分的に露出するハローイング現象を抑制することが可能
になる。
[Operation] According to the invention according to claim 1, the ratio of Cu2O/CuO in the oxide film formed on the surface of the wiring layer is set to 80% or more. According to the above, since the wiring layer is oxidized under conditions such that the ratio of Cu2O/CuO in the oxide film is 80% or more, the acid resistance of the oxide film increases as the proportion of Cu2O, which has high acid resistance, increases. As the properties are improved, the oxide film of the wiring layer becomes difficult to dissolve even if acid treatment is performed appropriately during the manufacturing process of the multilayer wiring board, and the haloing phenomenon in which the metallic copper of the wiring layer is partially exposed is suppressed. becomes possible.

【0020】他方、請求項2に係る発明によれば、配線
層の表面に形成された酸化膜中におけるCu2 O/C
uOの比率が80%でその酸化膜の膜厚が0.4μm〜
0.8μmに設定されており、また、請求項4に係る発
明によれば、酸化膜中におけるCu2 O/CuOの比
率が80%以上でその酸化膜の膜厚が従来法における膜
厚より小さな0.4μm〜0.8μmとなる条件で酸化
処理を施していることから、酸化膜の耐酸性が向上しし
かも酸化膜の膜厚も薄くサイドエッチが起り難いため、
多層配線板の製造工程途上において適宜酸処理を施して
も上記配線層の酸化膜が更に溶解され難くなり、配線層
の金属銅が部分的に露出するハローイング現象をより確
実に抑制することが可能になる。
On the other hand, according to the invention according to claim 2, Cu2O/C in the oxide film formed on the surface of the wiring layer
The ratio of uO is 80% and the thickness of the oxide film is 0.4 μm ~
According to the invention according to claim 4, the ratio of Cu2O/CuO in the oxide film is 80% or more and the thickness of the oxide film is smaller than that in the conventional method. Since the oxidation treatment is performed under the conditions of 0.4 μm to 0.8 μm, the acid resistance of the oxide film is improved, and the thickness of the oxide film is also thin, making it difficult for side etching to occur.
Even if appropriate acid treatment is performed during the manufacturing process of the multilayer wiring board, the oxide film of the wiring layer becomes more difficult to dissolve, and the haloing phenomenon in which the metallic copper of the wiring layer is partially exposed can be more reliably suppressed. It becomes possible.

【0021】[0021]

【実施例】以下、本発明の実施例について図面を参照し
て詳細に説明する。
Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

【0022】[実施例1]まず、表裏両面に銅箔が貼着
されたガラス・エポキシ銅貼積層板(340mm×51
0mm×1.6mm)を用い、従来同様、フォトエッチ
ング処理により上記銅箔をパターニングして内層用回路
板を製造した。
[Example 1] First, a glass/epoxy copper laminate (340 mm x 51
0 mm x 1.6 mm), the copper foil was patterned by photo-etching in the same manner as before to manufacture an inner layer circuit board.

【0023】次に、ニュウトラル・クリーン68(商標
、シップレー社製)の25%溶液を用い60℃の条件で
上記内層用回路板の両面側に形成された銅箔製の配線層
を脱脂処理し、かつ、水洗した後、エッチ(Etch)
746(商標、シップレー社製)を15%及びH2 O
2 を10%含む処理液を用いて60秒間のソフトエッ
チング処理を施しかつ水洗し、更に、硫酸を主成分とす
る固形酸(44g/l)を用いて酸洗しかつ水洗した。
Next, the copper foil wiring layers formed on both sides of the inner layer circuit board were degreased using a 25% solution of Neutral Clean 68 (trademark, manufactured by Shipley) at 60°C. , and after washing with water, etch
746 (trademark, manufactured by Shipley) at 15% and H2O
A soft etching process was performed for 60 seconds using a treatment solution containing 10% of 2, followed by washing with water, followed by pickling using a solid acid containing sulfuric acid as a main component (44 g/l) and washing with water.

【0024】この様に前処理された内層用回路板の配線
層を以下の条件で酸化処理し図1に示すように配線層1
の表面にCu2 OとCuOから成る酸化膜2を形成し
た。
The wiring layer of the inner layer circuit board pretreated in this way is oxidized under the following conditions to form wiring layer 1 as shown in FIG.
An oxide film 2 made of Cu2O and CuO was formed on the surface.

【0025】     酸化処理液の組成:Na3 PO4 ・12H
2 O    17g/l             
         NaOH            
        31g/l            
          NaClO2         
        43g/l          処理
液温度:85℃            処理時間:4
分尚、図1中、21はCuOを主成分とする酸化膜を、
また、22はCu2 Oを主成分とする酸化膜をそれぞ
れ示している。
Composition of oxidation treatment liquid: Na3 PO4 ・12H
2 O 17g/l
NaOH
31g/l
NaClO2
43g/l Treatment liquid temperature: 85℃ Treatment time: 4
In addition, in Fig. 1, 21 is an oxide film whose main component is CuO.
Further, 22 indicates an oxide film containing Cu2O as a main component.

【0026】また、上記酸化膜2の膜厚はオージェ分光
分析により1.0μmであることがまたCu2 O/C
uOの比率は薄膜用X線回析装置により80%であるこ
とが確認された。
Furthermore, the thickness of the oxide film 2 was found to be 1.0 μm by Auger spectroscopy.
The uO ratio was confirmed to be 80% using a thin film X-ray diffraction apparatus.

【0027】次いで、上記酸化膜2が形成された内層用
回路板を乾燥させた後、複数枚の内層用回路板を外層用
銅箔とともに接着性絶縁層を介して重合し、加熱加圧し
て多層配線板を製造した。
Next, after drying the inner layer circuit board on which the oxide film 2 has been formed, the plurality of inner layer circuit boards are polymerized together with the outer layer copper foil via an adhesive insulating layer, and heated and pressed. A multilayer wiring board was manufactured.

【0028】そして、従来と同様にこの多層配線板をド
リルにより孔開け加工して直径0.35mmのスルーホ
ールを形成し、かつ、従来同様酸洗等を行った後、スル
ーホールめっき処理(無電解銅めっき・パネルめっき)
を施してスルーホール内壁面と多層配線板表面に20μ
mの銅めっき層を形成し、更に、水洗、酸洗等の常套処
理を施し、かつ、従来同様のフォトレジスト層形成処理
、20μmの電解銅めっき処理、エッチング処理、ソル
ダー・レジスト層形成処理等を経て多層配線板を製造し
た。
Then, as in the conventional case, this multilayer wiring board was drilled to form a through hole with a diameter of 0.35 mm, and after performing pickling etc. as in the conventional case, through hole plating treatment (no electrolytic copper plating/panel plating)
20μ on the inner wall surface of the through hole and the surface of the multilayer wiring board.
Form a copper plating layer of m thick, and then perform conventional treatments such as water washing and pickling, as well as conventional photoresist layer formation treatment, 20 μm electrolytic copper plating treatment, etching treatment, solder resist layer formation treatment, etc. Through this process, a multilayer wiring board was manufactured.

【0029】この様にして求められた多層配線板のハロ
ーイング発生量について測定したところ、図2に示すよ
うにピンクリングの幅Lの値は約80μmで従来法に較
べて極めて低減され、従って、本発明を適用したことに
より配線層と接着性絶縁層との接着強度が強固でかつ配
線層と接着性絶縁層との界面に適宜処理剤が残留し難い
多層配線板が求められることが確認できた。
When the amount of haloing generated in the multilayer wiring board obtained in this way was measured, as shown in FIG. 2, the value of the width L of the pink ring was about 80 μm, which was extremely reduced compared to the conventional method. By applying the present invention, it was confirmed that there is a need for a multilayer wiring board in which the adhesive strength between the wiring layer and the adhesive insulating layer is strong and the appropriate treatment agent does not easily remain at the interface between the wiring layer and the adhesive insulating layer. did it.

【0030】[実施例2]以下に示す条件で酸化処理を
行った以外は実施例1と略同一である。
[Example 2] This was substantially the same as Example 1 except that the oxidation treatment was carried out under the conditions shown below.

【0031】     酸化処理液の組成:Na3 PO4 ・12H
2 O    17g/l             
         NaOH            
        31g/l            
          NaClO2         
        43g/l          処理
液温度:80℃            処理時間:4
分尚、上記酸化膜2の膜厚はオージェ分光分析により0
.6μmであることがまたCu2 O/CuOの比率は
薄膜用X線回析装置により140%であることが確認さ
れた。
Composition of oxidation treatment liquid: Na3 PO4 ・12H
2 O 17g/l
NaOH
31g/l
NaClO2
43g/l Treatment liquid temperature: 80℃ Treatment time: 4
Furthermore, the film thickness of the oxide film 2 was determined to be 0 by Auger spectroscopy.
.. It was confirmed that the thickness was 6 μm, and the Cu2O/CuO ratio was 140% using a thin film X-ray diffraction apparatus.

【0032】そして、この様にして求められた多層配線
板のハローイング発生量について測定したところ、ピン
クリングの幅Lの値は約70μm以下であり従来法に較
べて極めて低減され、かつ、実施例1よりも良好である
ことが確認できた。
When the amount of haloing generated in the multilayer wiring board obtained in this way was measured, the value of the width L of the pink ring was approximately 70 μm or less, which was extremely reduced compared to the conventional method. It was confirmed that this was better than Example 1.

【0033】[実施例3]以下の条件で酸化処理を2段
階で行った以外は実施例1と略同一である。
[Example 3] This was substantially the same as Example 1 except that the oxidation treatment was performed in two stages under the following conditions.

【0034】 (第一段階)     酸化処理液の組成:Na3 PO4 ・12H
2 O    17g/l             
         NaOH            
        21g/l            
          NaClO2         
        43g/l          処理
液温度:90℃            処理時間:4
分30秒上記条件で酸化処理を施し図3(A)に示すよ
うに配線層1の表面にCu2OとCuOから成る厚さ1
.0μmの酸化膜2を形成しかつ水洗した。
(First stage) Composition of oxidation treatment solution: Na3 PO4 ・12H
2 O 17g/l
NaOH
21g/l
NaClO2
43g/l Processing liquid temperature: 90°C Processing time: 4
After performing oxidation treatment under the above conditions for 30 seconds, the surface of the wiring layer 1 is coated with a thickness 1 consisting of Cu2O and CuO, as shown in FIG. 3(A).
.. An oxide film 2 of 0 μm was formed and washed with water.

【0035】次に、この酸化処理された内層用回路板を
10%のH2 SO4 水溶液に20〜30秒間浸漬し
、図3(B)に示すように上記酸化膜2の厚さが0.2
μmになるまでエッチング処理し、かつ、水洗した。
Next, this oxidized inner layer circuit board is immersed in a 10% H2 SO4 aqueous solution for 20 to 30 seconds, and as shown in FIG. 3(B), the thickness of the oxide film 2 is 0.2
It was etched to a thickness of μm and washed with water.

【0036】次いで、以下に示す条件で第二段階の酸化
処理を施し、図3(C)に示すような酸化膜20を形成
しかつ水洗した。
Next, a second stage oxidation treatment was performed under the conditions shown below to form an oxide film 20 as shown in FIG. 3(C), and the film was washed with water.

【0037】 (第二段階)     酸化処理液の組成:Na3 PO4 ・12H
2 O    17g/l             
         NaOH            
        31g/l            
          NaClO2         
        43g/l          処理
液温度:80℃            処理時間:4
分尚、上記酸化膜20の膜厚はオージェ分光分析により
0.6μmであることがまたCu2 O/CuOの比率
は薄膜用X線回析装置により150%であることが確認
された。
(Second stage) Composition of oxidation treatment solution: Na3 PO4 ・12H
2 O 17g/l
NaOH
31g/l
NaClO2
43g/l Treatment liquid temperature: 80℃ Treatment time: 4
Furthermore, it was confirmed that the thickness of the oxide film 20 was 0.6 μm by Auger spectroscopy, and that the Cu2O/CuO ratio was 150% by an X-ray diffraction apparatus for thin films.

【0038】そして、この様にして求められた多層配線
板のハローイング発生量について測定したところ、ピン
クリングの幅Lの値は約60μm以下であり実施例2と
同様に良好であることが確認できた。
When the amount of haloing generated in the multilayer wiring board thus obtained was measured, it was confirmed that the value of the width L of the pink ring was about 60 μm or less, which was as good as in Example 2. did it.

【0039】[比較例]以下に示す条件で酸化処理を行
った以外は実施例1と略同一である。
[Comparative Example] This was substantially the same as Example 1 except that the oxidation treatment was carried out under the conditions shown below.

【0040】     酸化処理液の組成:Na3 PO4 ・12H
2 O    17g/l             
         NaOH            
        21g/l            
          NaClO2         
        43g/l          処理
液温度:95℃            処理時間:4
分30秒尚、上記酸化膜2の膜厚はオージェ分光分析に
より1.0μmであることがまたCu2 O/CuOの
比率は薄膜用X線回析装置により33%であることが確
認された。
Composition of oxidation treatment liquid: Na3 PO4 ・12H
2 O 17g/l
NaOH
21g/l
NaClO2
43g/l Treatment liquid temperature: 95℃ Treatment time: 4
30 seconds It was confirmed that the thickness of the oxide film 2 was 1.0 μm by Auger spectroscopy, and the Cu2O/CuO ratio was 33% by an X-ray diffraction apparatus for thin films.

【0041】そして、この比較例に係る多層配線板のハ
ローイング発生量について測定したところ、ピンクリン
グの幅Lの値は約140μmであり上記実施例1〜3の
多層配線板と較べ極めて劣っていることが確認できた。
When the amount of haloing generated in the multilayer wiring board according to this comparative example was measured, the value of the width L of the pink ring was about 140 μm, which was extremely inferior to the multilayer wiring boards of Examples 1 to 3. I was able to confirm that there was.

【0042】[0042]

【発明の効果】請求項1及び3に係る発明によれば、耐
酸性の大きいCu2Oの割合が増大する分その酸化膜の
耐酸性が向上するため、多層配線板の製造工程途上にお
いて適宜酸処理を施しても配線層の酸化膜が溶解され難
くなり配線層の金属銅が部分的に露出するハローイング
現象を抑制することが可能になる。
According to the invention according to claims 1 and 3, the acid resistance of the oxide film is improved as the proportion of Cu2O, which has high acid resistance, increases, so that acid treatment can be performed as appropriate during the manufacturing process of the multilayer wiring board. Even if it is applied, the oxide film of the wiring layer is difficult to dissolve, making it possible to suppress the haloing phenomenon in which the metal copper of the wiring layer is partially exposed.

【0043】他方、請求項2及び4に係る発明によれば
、酸化膜の耐酸性が向上ししかも酸化膜の膜厚も薄くサ
イドエッチが起り難いため、多層配線板の製造工程途上
において適宜酸処理を施しても上記配線層の酸化膜が更
に溶解され難くなり配線層の金属銅が部分的に露出する
ハローイング現象をより確実に抑制することが可能にな
る。
On the other hand, according to the inventions according to claims 2 and 4, the acid resistance of the oxide film is improved and the thickness of the oxide film is also thin so that side etching is difficult to occur. Even if the treatment is performed, the oxide film of the wiring layer becomes more difficult to dissolve, and it becomes possible to more reliably suppress the haloing phenomenon in which the metal copper of the wiring layer is partially exposed.

【0044】従って、上記配線層と接着性絶縁層との接
着不良が防止できると共に配線層と接着性絶縁層との界
面に上記酸処理剤等が残留し難くなるため多層配線板と
しての信頼性を著しく向上できる効果を有している。
Therefore, poor adhesion between the wiring layer and the adhesive insulating layer can be prevented, and the acid treatment agent and the like are less likely to remain at the interface between the wiring layer and the adhesive insulating layer, improving reliability as a multilayer wiring board. It has the effect of significantly improving the

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】実施例に係る内層用回路板の一部拡大断面図。FIG. 1 is a partially enlarged sectional view of an inner layer circuit board according to an embodiment.

【図2】実施例に係る多層配線板の一部拡大斜視図。FIG. 2 is a partially enlarged perspective view of the multilayer wiring board according to the example.

【図3】図3(A)〜(C)は2回の酸化処理により酸
化膜を形成する工程説明図。
FIGS. 3(A) to 3(C) are process explanatory diagrams of forming an oxide film through two oxidation treatments.

【図4】従来の多層配線板の製造工程途上の斜視図。FIG. 4 is a perspective view of a conventional multilayer wiring board in the middle of a manufacturing process.

【図5】従来の多層配線板の製造工程途上の斜視図。FIG. 5 is a perspective view of a conventional multilayer wiring board in the middle of a manufacturing process.

【図6】従来の多層配線板の製造工程途上の斜視図。FIG. 6 is a perspective view of a conventional multilayer wiring board in the middle of a manufacturing process.

【図7】従来の多層配線板の製造工程途上の斜視図。FIG. 7 is a perspective view of a conventional multilayer wiring board in the middle of a manufacturing process.

【図8】従来の多層配線板の製造工程途上の斜視図。FIG. 8 is a perspective view of a conventional multilayer wiring board in the middle of a manufacturing process.

【図9】従来の多層配線板の製造工程途上の斜視図。FIG. 9 is a perspective view of a conventional multilayer wiring board in the middle of a manufacturing process.

【図10】製造された従来の多層配線板の概略斜視図。FIG. 10 is a schematic perspective view of a manufactured conventional multilayer wiring board.

【図11】図11(A)〜(B)は従来の配線層表面を
酸化処理する工程説明図。
FIGS. 11A and 11B are explanatory diagrams of a conventional process of oxidizing the surface of a wiring layer.

【図12】図12(A)〜(B)はスルーホール形成後
における従来の多層配線板の一部拡大断面図。
12A and 12B are partially enlarged sectional views of a conventional multilayer wiring board after forming through holes.

【図13】スルーホール形成後における従来の多層配線
板の一部拡大斜視図。
FIG. 13 is a partially enlarged perspective view of a conventional multilayer wiring board after forming through holes.

【図14】図13のW−W面の部分断面図。FIG. 14 is a partial sectional view taken along the line W-W in FIG. 13;

【符号の説明】[Explanation of symbols]

1    配線層 2    酸化膜 1. Wiring layer 2 Oxide film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】  CuOとCu2 Oの酸化膜が表面に
形成された銅箔製の配線層を有する内層用回路板が接着
性絶縁層を介し複数積層されて成る多層配線板において
、上記酸化膜中におけるCu2 O/CuOの比率が8
0%以上に設定されていることを特徴とする多層配線板
1. A multilayer wiring board in which a plurality of inner layer circuit boards each having a wiring layer made of copper foil with an oxide film of CuO and Cu2O formed on the surface thereof are laminated with an adhesive insulating layer interposed therebetween, wherein the oxide film is The ratio of Cu2O/CuO inside is 8
A multilayer wiring board characterized in that the wiring board is set to 0% or more.
【請求項2】  CuOとCu2 Oの酸化膜が表面に
形成された銅箔製の配線層を有する内層用回路板が接着
性絶縁層を介し複数積層されて成る多層配線板において
、上記酸化膜中におけるCu2 O/CuOの比率が8
0%以上でその酸化膜の膜厚が0.4μm〜0.8μm
に設定されていることを特徴とする多層配線板。
2. A multilayer wiring board comprising a plurality of inner layer circuit boards laminated with an adhesive insulating layer interposed therebetween, each having a wiring layer made of copper foil on the surface of which an oxide film of CuO and Cu2O is formed. The ratio of Cu2O/CuO inside is 8
If it is 0% or more, the thickness of the oxide film is 0.4 μm to 0.8 μm.
A multilayer wiring board characterized by being set to.
【請求項3】  銅箔により形成された配線層を有する
内層用回路板の上記配線層を酸化処理してその表面にC
uOとCu2 Oからなる酸化膜を形成し、かつ、酸化
処理されたこれ等複数枚の内層用回路板を接着性絶縁層
を介し積層して多層配線板を製造する方法において、酸
化膜中におけるCu2 O/CuOの比率が80%以上
となる条件で上記酸化処理を施すことを特徴とする多層
配線板の製造方法。
3. The wiring layer of the inner layer circuit board having the wiring layer formed of copper foil is oxidized and the surface thereof is coated with carbon.
In a method of manufacturing a multilayer wiring board by forming an oxide film consisting of uO and Cu2O and laminating a plurality of these oxidized inner layer circuit boards via an adhesive insulating layer, A method for manufacturing a multilayer wiring board, characterized in that the oxidation treatment is performed under conditions such that the ratio of Cu2O/CuO is 80% or more.
【請求項4】  銅箔により形成された配線層を有する
内層用回路板の上記配線層を酸化処理してその表面にC
uOとCu2 Oからなる酸化膜を形成し、かつ、酸化
処理されたこれ等複数枚の内層用回路板を接着性絶縁層
を介し積層して多層配線板を製造する方法において、酸
化膜中におけるCu2 O/CuOの比率が80%以上
でその酸化膜の膜厚が0.4μm〜0.8μmとなる条
件で上記酸化処理を施すことを特徴とする多層配線板の
製造方法。
4. The wiring layer of the inner layer circuit board having the wiring layer formed of copper foil is oxidized and the surface thereof is coated with carbon.
In a method of manufacturing a multilayer wiring board by forming an oxide film consisting of uO and Cu2O and laminating a plurality of these oxidized inner layer circuit boards via an adhesive insulating layer, A method for manufacturing a multilayer wiring board, characterized in that the oxidation treatment is performed under conditions such that the ratio of Cu2O/CuO is 80% or more and the thickness of the oxide film is 0.4 μm to 0.8 μm.
JP10301991A 1991-05-09 1991-05-09 Multilayer wiring board and its manufacturing method Expired - Fee Related JP3123109B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10301991A JP3123109B2 (en) 1991-05-09 1991-05-09 Multilayer wiring board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10301991A JP3123109B2 (en) 1991-05-09 1991-05-09 Multilayer wiring board and its manufacturing method

Publications (2)

Publication Number Publication Date
JPH04334093A true JPH04334093A (en) 1992-11-20
JP3123109B2 JP3123109B2 (en) 2001-01-09

Family

ID=14342940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10301991A Expired - Fee Related JP3123109B2 (en) 1991-05-09 1991-05-09 Multilayer wiring board and its manufacturing method

Country Status (1)

Country Link
JP (1) JP3123109B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011079330A (en) * 2007-12-14 2011-04-21 Denso Corp Resin-metal bonded article and method for producing the same
JPWO2015040998A1 (en) * 2013-09-20 2017-03-02 三井金属鉱業株式会社 Copper foil, copper foil with carrier foil and copper clad laminate
CN112204171A (en) * 2018-06-20 2021-01-08 纳美仕有限公司 Roughened copper foil, copper-clad laminate, and printed wiring board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011079330A (en) * 2007-12-14 2011-04-21 Denso Corp Resin-metal bonded article and method for producing the same
JP4883425B2 (en) * 2007-12-14 2012-02-22 株式会社デンソー Resin metal bonded product and manufacturing method thereof
US8394503B2 (en) 2007-12-14 2013-03-12 Toadenka Corporation Resin-metal bonded article and method for producing the same
JPWO2015040998A1 (en) * 2013-09-20 2017-03-02 三井金属鉱業株式会社 Copper foil, copper foil with carrier foil and copper clad laminate
CN112204171A (en) * 2018-06-20 2021-01-08 纳美仕有限公司 Roughened copper foil, copper-clad laminate, and printed wiring board
CN112204171B (en) * 2018-06-20 2023-09-29 纳美仕有限公司 Coarsening copper foil, copper-clad laminate and printed circuit board

Also Published As

Publication number Publication date
JP3123109B2 (en) 2001-01-09

Similar Documents

Publication Publication Date Title
TWI395531B (en) Printed circuit board, manufacturing method thereof, and semiconductor device
JP4695675B2 (en) Method for manufacturing printed wiring board
TWI436706B (en) A method of manufacturing a printed wiring board, and a printed wiring board obtained from the manufacturing method
JP3123109B2 (en) Multilayer wiring board and its manufacturing method
JP2000261149A (en) Mutilayer printed wiring board and manufacture thereof
EP0298422B1 (en) Wiring method
JP2006066889A (en) Printed circuit board, manufacturing method thereof, and semiconductor device
JP3123107B2 (en) Method for manufacturing multilayer wiring board
US4781788A (en) Process for preparing printed circuit boards
JP3123108B2 (en) Method for manufacturing multilayer wiring board
JP3364933B2 (en) Multilayer printed wiring board and copper foil for inner layer electric circuit
JP2768122B2 (en) Method for manufacturing multilayer wiring board
JP2768123B2 (en) Method for manufacturing multilayer wiring board
EP0488299B1 (en) Method of manufacturing a multi-layered wiring board
JPH0636470B2 (en) Method for treating copper circuit of circuit board for inner layer
US11523515B2 (en) Method for manufacturing wiring substrate
JP3185516B2 (en) Method for manufacturing multilayer wiring board
JPH0136997B2 (en)
JPH03129793A (en) Treating method for circuit board substrate
JPH06216520A (en) Manufacture of multilayer printed board
JPH04208596A (en) Manufacture of multilayer printed circuit board
JPH05206639A (en) Treating method for copper circuit of circuit board
JPS6016494A (en) Method of producing printed circuit board
JPH0496292A (en) Manufacture of board for multilayer printed circuit
JPH05308192A (en) Board for multilayer printed wiring board

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081027

Year of fee payment: 8

LAPS Cancellation because of no payment of annual fees