JPH04334068A - Manufacture of nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase writing speed without deteriorating erasing speed, by forming a first conductivity type diffusion layer by injecting first conductivity impurities in a drain forming region of the semiconductor substrate surface, at an angle inclined to the normal direction of the semiconductor substrate. CONSTITUTION:A photo resist film 9 having an aperture is formed on a drain forming region in an element forming region. By using the photo resist mask 9 as a mask, impurities of the same conductivity type as that of a semiconductor substrate 1, e.g. B<+>, are implanted at an angle of 30-60 degrees inclined to the normal direction of the semiconductor substrate 1, and a P<+> type diffusion layer 10 is formed selectively on the semiconductor substrate 1 surface. Thereby, without heat-treating said substrate 1 for a long time, the P<+> type diffusion layer 10 can be stretched as far as the region just under a floating gate 5a, and the junction strength of a source diffusion layer can be lowered, so that the writing speed of a storage transistor can be increased without deteriorating the erasing speed thereof.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing a floating gate electrode type nonvolatile semiconductor device that can be electrically written and erased.

0002

2. Description of the Related Art Conventionally, electrically programmable and erasable nonvolatile semiconductor memory devices (EEPROMs) have a Fowler-Nordheim method for programming and erasing.
The most common method is to use type tunnel current. However, in such a system, since a 1-bit memory cell is composed of two transistors, a selection transistor and a memory transistor, the cell area becomes large, making it difficult to increase the capacity of a nonvolatile semiconductor memory device.

[0003] Therefore, as a countermeasure to the above-mentioned disadvantage, a Flash EEPROM has been proposed. Although this Flash EEPROM cannot be rewritten in bytes like conventional EEPROMs and is a so-called batch erasing type, it is a method that combines large capacity cells such as ultraviolet erasable EPROMs with "electrical erasing". Attention has been paid.

FIGS. 13 to 19 show conventional FlashEEP
FIG. 3 is a cross-sectional view showing, in order of steps, a method for manufacturing a self-aligned gate type memory transistor that can have the smallest cell area among ROMs.

First, as shown in FIG.
A channel stopper region 2 in which impurities of the same conductivity type as that of the semiconductor substrate 1 are diffused is selectively formed in the element isolation region on the surface of the semiconductor substrate 1, and a relatively thick element isolation insulator is formed on the channel stopper region 2. A film 3 is selectively formed, and a gate insulating film 4 having a thickness of about 50 to 150 Å is formed by a thermal oxidation method in a region on the surface of the semiconductor substrate 1 where an element is to be formed.

Next, as shown in FIG. 14, a polysilicon film 5 having a thickness of about 1000 to 3000 Å and containing impurities (for example, phosphorus) is patterned on the gate insulating film 4. Next, a gate insulating film 6 having a thickness of about 100 to 300 Å is formed on the surface of the polysilicon film 5 by thermal oxidation or chemical vapor deposition. Next, a polysilicon film 7 containing impurities (for example, phosphorus) is formed on the polysilicon film 5 and the element insulating film 3.

Next, as shown in FIG. 15, the polysilicon film 7 is patterned using the photoresist film 8 patterned on the polysilicon film 7 as a mask to form a control gate electrode 7a on the gate insulating film 6. .

Next, as shown in FIG. 16, the gate insulating film 6 and polysilicon film 5 are patterned to form a floating gate electrode 5a in alignment with the control gate electrode 7a, and then the photoresist film 8 is removed. .

Next, as shown in FIG. 17, a photoresist film 9 having an opening in the region where the drain is to be formed in the region where the element is to be formed is formed, and using this photoresist film 9 as a mask, the conductivity of the semiconductor substrate 1 is A P+ type diffusion layer 10 is selectively formed on the surface of the semiconductor substrate 1 by implanting an impurity of the same conductivity type as the type (for example, boron) at an angle of 0 degrees to the normal direction of the semiconductor substrate 1. . In this case, in order to form the P+ type diffusion layer 10 deeply, approximately 950
Heat treatment is performed on the semiconductor substrate 1 at a temperature of 1100°C to 1100°C.

Next, as shown in FIG. 18, using the element isolation insulating film 3 and the control gate insulating film 7a as masks, a conductivity type opposite to that of the semiconductor substrate 1 is applied to the region where the element is to be formed on the surface of the semiconductor substrate 1. A drain diffusion layer 11 and a source diffusion layer 12 are selectively formed on the surface of the semiconductor substrate 1 by diffusing impurities (for example, arsenic or phosphorus).

Next, as shown in FIG. 19, after forming an interlayer insulating film 13 on the entire surface, contact holes are formed in the interlayer insulating film 13 and the gate insulating film 4 directly above the drain diffusion layer 11 and source diffusion layer 12. A wiring electrode 14 is formed on the interlayer insulating film 13 to be electrically connected to the drain diffusion layer 11 and the source diffusion layer 12 through the contact hole. After that, a cover insulating film 14 is formed on the entire surface.

Next, the operation of the memory transistor configured as described above will be explained. First, when writing, a high voltage is applied to the drain diffusion layer 11 and the control gate electrode 7a, and hot electrons generated in the pinch-off region in the channel are transferred to the floating gate electrode 5a in the same way as in a normal ultraviolet erasable EPROM. inject. That is, the write operation is performed by so-called hot electron injection to increase the threshold voltage VTM of the memory transistor. As a method of increasing the speed of this write operation, the drain diffusion layer 11
A method of forming a P+ type diffusion layer 10 around (Tanaka,
IEEE ISSCC84“A Programmab
le 256K CMOS EPROM with O
n-Chip Test Circuits”, 19
Published in 1984 and published in Japanese Unexamined Patent Publication No. 13901/1984). On the other hand, in the erase operation, a high voltage is applied to the source diffusion layer 12 while the control gate electrode 7a is grounded,
Electrons within the floating gate electrode 5a are emitted using the er-Nordheim type tunneling current, thereby lowering the threshold voltage VTM of the memory transistor.

[0013]

However, in the conventional method of manufacturing a nonvolatile semiconductor memory device described above, the impurity concentration of the P+ type diffusion layer 10 is increased in order to further increase the writing speed of the nonvolatile semiconductor memory device. Then,
The source diffusion layer 12 and the P+ type diffusion layer 10 end up being joined together. In this case, there is a problem that the junction breakdown voltage of the source diffusion layer 12 decreases, a desired erase voltage cannot be obtained during the erase operation, and the erase speed becomes slow.

[0014] Also, around the drain diffusion layer 11, P+
Since the type diffusion layer 10 is formed, the drain diffusion layer 1
The junction capacitance of 1 becomes extremely large, and the operating speed of the nonvolatile semiconductor memory device also becomes slow.

The present invention has been made in view of these problems, and provides a method for manufacturing a nonvolatile semiconductor memory device that can increase the write speed of the nonvolatile semiconductor memory device without reducing its erase speed. The purpose is to provide

[0016]

Means for Solving the Problems A method of manufacturing a nonvolatile semiconductor memory device according to the present invention includes the steps of selectively forming an element isolation region on the surface of a first conductivity type semiconductor substrate; a step of forming a first gate insulating film in a region where an element is to be formed; and a step of forming a first gate insulating film on the first gate insulating film.
forming a second gate insulating film on the surface of the first polysilicon film; and patterning a second polysilicon film on the second gate insulating film. forming a floating gate electrode made of the first polysilicon film by patterning the second gate insulating film and the first polysilicon film using the control gate electrode as a mask; forming the first conductive conductor on the surface of the semiconductor substrate at an angle oblique to the normal direction of the semiconductor substrate using a photoresist film having an opening in the region where the drain is to be formed in the region where the element is to be formed as a mask; and selectively forming a source diffusion layer and a drain diffusion layer by diffusing second conductivity type impurities into the element formation region on the surface of the semiconductor substrate. It is characterized by

[0017]

[Operation] In the present invention, after forming a first gate insulating film in a region where an element is to be formed on the surface of a semiconductor substrate of a first conductivity type, a first polysilicon film is formed on the first gate insulating film. A floating gate electrode, a second gate insulating film, and a control gate electrode made of a second polysilicon film are stacked and formed. Thereafter, using a photoresist film having an opening in the region where the drain is to be formed in the region where the element is to be formed as a mask, the first conductivity type is coated on the surface of the semiconductor substrate at an angle oblique to the normal direction of the semiconductor substrate. By implanting impurities, a first conductivity type diffusion layer is selectively formed in the drain formation region on the surface of the semiconductor substrate. In this case, since the angle at which the first conductivity type impurity is implanted is inclined, the first conductivity type diffusion layer can extend to a region immediately below the floating gate electrode. Next, a source diffusion layer and a drain diffusion layer are selectively formed by diffusing second conductivity type impurities into the element formation region on the surface of the semiconductor substrate.

In the present invention, when forming the first conductivity type diffusion layer, the impurity implantation angle is tilted and unlike the conventional method, heat treatment is not performed, so that the first conductivity type diffusion layer is formed in a predetermined region. can be formed at a concentration of Therefore, the source diffusion layer and the first conductivity type diffusion layer are not bonded to each other, and it is possible to prevent the junction breakdown voltage of the source diffusion layer from decreasing, thereby increasing the erasing speed of the nonvolatile semiconductor memory device. The writing speed can be increased without decreasing it. Furthermore, since the first conductivity type diffusion layer can be formed only at the end of the drain diffusion layer on the channel side, the capacitance between the drain diffusion layer and the semiconductor substrate can be extremely reduced compared to the conventional method. can,
The operating speed of the nonvolatile semiconductor memory device can be further increased.

Further, in the present invention, if the angle at which the impurity of the first conductivity type is implanted is less than 30 degrees with respect to the normal direction of the semiconductor substrate, the first conductivity type diffusion layer is formed in the floating gate electrode. If the angle exceeds 60 degrees, an unimplanted region is likely to be formed. Therefore, it is preferable that the impurity of the first conductivity type is implanted at an angle of 30 to 60 degrees with respect to the normal direction of the semiconductor substrate.

In particular, when manufacturing a non-volatile semiconductor memory device having a plurality of memory transistors etc. on the same semiconductor substrate, the step of implanting the impurity of the first conductivity type is carried out in the normal direction of the semiconductor substrate. It is preferable to perform this while rotating the semiconductor substrate as a rotation axis. In this case, no unimplanted region is formed, and the first conductivity type diffusion layer can be reliably provided for all memory transistors and the like.

[0021]

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIGS. 1 to 7 are cross-sectional views showing step-by-step a method for manufacturing a memory transistor according to a first embodiment of the present invention.

First, as shown in FIG. 1, a channel stopper region 2 in which an impurity of the same conductivity type as that of the semiconductor substrate 1 is diffused is selectively formed in an element isolation region on the surface of a semiconductor substrate 1. A device isolation insulating film 3 having a relatively thick film thickness is selectively formed on the channel stopper region 2, and a gate insulating film having a film thickness of, for example, about 50 to 150 Å is formed by thermal oxidation on the region where the device is to be formed on the surface of the semiconductor substrate 1. A film 4 is formed.

Next, as shown in FIG. 2, the gate insulating film 4 is
A polysilicon film 5 containing impurities (for example, phosphorus) and having a thickness of, for example, about 1000 to 3000 Å is patterned thereon. Next, a gate insulating film 6 having a thickness of about 100 to 300 Å, for example, is formed on the surface of the polysilicon film 5 by thermal oxidation or chemical vapor deposition. Next, a polysilicon film 7 containing impurities (for example, phosphorus) is formed on the polysilicon film 5 and the element insulating film 3.

Next, as shown in FIG. 3, the polysilicon film 7 is patterned using the photoresist film 8 patterned on the polysilicon film 7 as a mask to form a control gate electrode 7a on the gate insulating film 6. .

Next, as shown in FIG. 4, gate insulating film 6 and polysilicon film 5 are formed in alignment with control gate electrode 7a.
After patterning to form the floating gate electrode 5a,
Photoresist film 8 is removed.

Next, as shown in FIG. 5, a photoresist film 9 having an opening in the region where the drain is to be formed in the region where the element is to be formed is formed, and the conductivity of the semiconductor substrate 1 is formed using this photoresist film 9 as a mask. By implanting an impurity of the same conductivity type as the type (for example, boron) at an angle of 30 to 60 degrees with respect to the normal direction of the semiconductor substrate 1, a P+ type diffusion layer 10 is selectively formed on the surface of the semiconductor substrate 1. Form. As a result, the P+ type diffusion layer 10 can be extended to the area immediately below the floating gate electrode 5a without subjecting the semiconductor substrate 1 to long-term heat treatment, unlike the conventional method. In this case, while rotating the semiconductor substrate 1 with the normal direction of the semiconductor substrate 1 as the rotation axis,
It is preferable to implant impurities into the surface of the substrate.

Next, as shown in FIG. 6, using the element isolation insulating film 3 and the control gate insulating film 7a as masks, a conductivity type opposite to that of the semiconductor substrate 1 is applied to the region where the element is to be formed on the surface of the semiconductor substrate 1. A drain diffusion layer 11 and a source diffusion layer 12 are selectively formed on the surface of the semiconductor substrate 1 by diffusing impurities (for example, arsenic or phosphorus).

Next, as shown in FIG. 7, after forming the interlayer insulating film 13 on the entire surface, the interlayer insulating film 13 and the gate insulating film 4 are formed directly above the drain diffusion layer 11 and the source diffusion layer 12.
A contact hole is provided in , and a wiring electrode 14 electrically connected to the drain diffusion layer 11 and the source diffusion layer 12 through the contact hole is patterned on the interlayer insulating film 13 . After that, a cover insulating film 14 is formed on the entire surface.

In this embodiment, the P+ type diffusion layer 10
Since the impurity implantation angle is tilted during formation and no heat treatment is performed, the P+ type diffusion layer 10 can be formed in a predetermined region at a predetermined concentration. Therefore, if the gate dimensions of the control gate electrode 7a and the floating gate electrode 5a are L, the source diffusion layer 12 and the P+ type diffusion layer 10 will not be connected to each other as shown in FIG. Therefore, it is possible to prevent the junction breakdown voltage of the source diffusion layer 12 from decreasing, so that the writing speed of the memory transistor can be increased without reducing the erasing speed of the memory transistor.

Furthermore, according to this embodiment, since the P+ type diffusion layer 10 can be formed only at the end of the drain diffusion layer 11 on the channel side, the capacitance between the drain diffusion layer 11 and the semiconductor substrate 1 can be reduced. can be made extremely smaller than in the past, and the operating speed of the memory transistor can be further increased.

On the other hand, in the conventional memory transistor, the impurity implanted into the surface of the semiconductor substrate 1 is diffused by heat treatment to form the P+ type diffusion layer 10 at the end of the drain diffusion layer 11. The P+ type diffusion layer 10 is formed to spread to other regions. Therefore, when the gate dimensions of the control gate electrode 7a and the floating gate electrode 5a are L, the source diffusion layer 12 and the P+ type diffusion layer 10 are bonded to each other as shown in FIG. Also,
When trying to increase the impurity concentration of the P+ type diffusion layer 10 at the channel side end of the drain diffusion layer 11, the P+
The depth of the type diffusion layer 10 becomes deeper, and the drain diffusion layer 11 becomes deeper.
The junction capacitance becomes large.

FIG. 4 is a graph showing the erase characteristics when the gate dimension of the memory transistors according to this embodiment and the conventional example is L, in which the horizontal axis represents the logarithm of the erase time T;
The vertical axis indicates the threshold voltage VTM. As is clear from FIG. 4, the memory transistor according to this embodiment can erase stored information in a much shorter time than the memory transistor according to the conventional example.

FIGS. 11 and 12 are cross-sectional views showing a method for manufacturing a memory transistor according to a second embodiment of the present invention in the order of steps. Note that this example shows the case where two memory transistors are provided on a semiconductor substrate, so
In FIGS. 11 and 12, the same parts as those in FIGS. 1 to 7 are given the same reference numerals, and detailed explanations of those parts will be omitted.

That is, in this embodiment, two memory transistors each having a control gate electrode 7a and a floating gate electrode 5a are arranged side by side on the semiconductor substrate 1 so as to share their drain diffusion layer. . In this case, as shown in FIG. 11, if the angle of ion implantation when forming the P+ type diffusion layer 10 is tilted in a specific direction, the ion implantation is locally blocked by the photoresist film 9, etc., so that the semiconductor substrate 1 An unimplanted region in which the P+ type diffusion layer 10 does not exist is formed on the surface. Therefore, by performing ion implantation from the opposite direction to the specific direction, a P+ type diffusion layer 10 is formed in the non-implanted region of the surface of the semiconductor substrate 1. In order to realize such a method, it is necessary to tilt the normal direction of the semiconductor substrate 1 at a predetermined angle with respect to the ion implantation angle, and then rotate the semiconductor substrate 1 with the normal direction as the rotation axis. preferable.

According to this embodiment, in the same way as the first embodiment, the erasing speed of the memory transistor is not reduced;
To increase the writing speed and to ensure that a P+ type diffusion layer 10 is provided for all memory transistors when a plurality of memory transistors sharing a drain diffusion layer are formed on the same semiconductor substrate 1. Can be done.

[0037]

As explained above, according to the present invention, impurities of the first conductivity type are implanted into the region where the drain is to be formed on the surface of the semiconductor substrate at an angle oblique to the normal direction of the semiconductor substrate. Since the first conductivity type diffusion layer is formed by the method, the formation area and impurity concentration of the first conductivity type diffusion layer can be easily controlled, unlike the conventional case where the first conductivity type diffusion layer is formed by heat treatment. be able to. Therefore, the source diffusion layer and the first conductivity type diffusion layer are not bonded to each other, and it is possible to prevent the junction breakdown voltage of the source diffusion layer from decreasing, thereby reducing the erasing speed of the nonvolatile semiconductor memory device. It is possible to increase the writing speed without having to Furthermore, since the first conductivity type diffusion layer can be formed only at the end of the drain diffusion layer on the channel side, the capacitance between the drain diffusion layer and the semiconductor substrate can be made extremely small compared to the conventional method. Therefore, the operating speed of the nonvolatile semiconductor memory device can be further increased.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing one step of a method for manufacturing a memory transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing one step of the method for manufacturing a memory transistor according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing one step of the method for manufacturing a memory transistor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing one step of the method for manufacturing a memory transistor according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing one step of the method for manufacturing a memory transistor according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing one step of the method for manufacturing a memory transistor according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing one step of the method for manufacturing a memory transistor according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a memory transistor according to the first example.

FIG. 9 is a cross-sectional view showing a memory transistor according to a conventional example.

FIG. 10 is a graph diagram showing erase characteristics of memory transistors according to the first embodiment and a conventional example.

FIG. 11 is a cross-sectional view showing one step of a method for manufacturing a memory transistor according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing one step of a method for manufacturing a memory transistor according to a second embodiment of the present invention.

FIG. 13 is a cross-sectional view showing one step in a conventional method for manufacturing a memory transistor.

FIG. 14 is a cross-sectional view showing one step in a conventional method for manufacturing a memory transistor.

FIG. 15 is a cross-sectional view showing one step in a conventional method for manufacturing a memory transistor.

FIG. 16 is a cross-sectional view showing one step in a conventional method for manufacturing a memory transistor.

FIG. 17 is a cross-sectional view showing one step in a conventional method for manufacturing a memory transistor.

FIG. 18 is a cross-sectional view showing one step of a conventional method for manufacturing a memory transistor.

FIG. 19 is a cross-sectional view showing one step in a conventional method for manufacturing a memory transistor.

[Explanation of symbols]

1; Semiconductor substrate 2; Channel stopper area 3; Element isolation insulating film 4, 6; Gate insulating film 5, 7; Polysilicon film 5a; floating gate electrode 7a; Control gate electrode 8,9; Photoresist film 10; P+ type diffusion layer 11; Drain diffusion layer 12; Source diffusion layer 13; Interlayer insulation film 14; Wiring electrode 15; Cover insulation film

Claims (3)

[Claims] 1. A step of selectively forming an element isolation region on a surface of a semiconductor substrate of a first conductivity type; and a step of forming a first gate insulating film in a region where an element is to be formed on the surface of the semiconductor substrate. a step of forming a first polysilicon film on the first gate insulating film; a step of forming a second gate insulating film on the surface of the first polysilicon film;
forming a control gate electrode by patterning a second polysilicon film on the gate insulating film; and patterning the second gate insulating film and the first polysilicon film using the control gate electrode as a mask. The steps include providing a floating gate electrode made of the first polysilicon film, and using a photoresist film having an opening in the region where the drain is to be formed in the region where the element is to be formed as a mask in the normal direction of the semiconductor substrate. implanting the impurity of the first conductivity type into the surface of the semiconductor substrate at an inclined angle; and diffusing the impurity of the second conductivity type into the region where the element is to be formed on the surface of the semiconductor substrate, thereby forming a source diffusion layer. and a step of selectively forming a drain diffusion layer. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the impurity of the first conductivity type is implanted at an angle of 30 to 60 degrees with respect to the normal direction of the semiconductor substrate. manufacturing method. 3. The nonvolatile non-volatile material according to claim 1, wherein the step of implanting the first conductivity type impurity is performed while rotating the semiconductor substrate with the normal direction of the semiconductor substrate as a rotation axis. A method for manufacturing a semiconductor memory device.