JPH04334042A - Semiconductor chip and probe device for measuring semiconductor chip property - Google Patents

Semiconductor chip and probe device for measuring semiconductor chip property

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Publication number
JPH04334042A
JPH04334042A JP3133558A JP13355891A JPH04334042A JP H04334042 A JPH04334042 A JP H04334042A JP 3133558 A JP3133558 A JP 3133558A JP 13355891 A JP13355891 A JP 13355891A JP H04334042 A JPH04334042 A JP H04334042A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
integrated circuit
measurement
measured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3133558A
Other languages
Japanese (ja)
Inventor
Ichiyoshi Kondou
近藤 伊知良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3133558A priority Critical patent/JPH04334042A/en
Publication of JPH04334042A publication Critical patent/JPH04334042A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to measure a semiconductor circuit in parallel. CONSTITUTION:A pad 111a required for the measurement of a semiconductor circuit 102 is laid out so as to face one side of a semiconductor chip 101 whereas measurement probes 112 to 115 are placed in contact in parallel (Fig. 1(b)), thereby measuring four semiconductor chips in parallel. This construction makes it possible to reduce the time of P/W of the semiconductor chip substantially in inverse proportion to the number of chips to be measured in parallel.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、並列測定を行う特性測
定対象の半導体集積回路を搭載した半導体チップ及び、
その半導体チップの特性測定に用いるプローブ装置に関
する。
[Industrial Field of Application] The present invention relates to a semiconductor chip equipped with a semiconductor integrated circuit whose characteristics are to be measured in parallel;
The present invention relates to a probe device used to measure the characteristics of the semiconductor chip.

【0002】0002

【従来の技術】半導体チップ内に搭載された半導体集積
回路が、データを電気的に書き込み、そのデータを紫外
線の照射により消去する構造の不揮発性半導体記憶集積
回路、あるいは、データの書き込み及び消去を電気的に
行う構造の不揮発性半導体記憶集積回路である場合には
、P/W又は選別において、1バイト当りの書き込み、
あるいは消去の時間が数ミリセコンド必要になるため、
1キロバイトの記憶容量で数セコンドのテスト時間が必
要となる。そのため、半導体チップ相互間で半導体記憶
集積回路のみを選択して、該半導体記憶集積回路に対す
る並列測定を並行して行うことは、出荷時の測定作業を
能率よく行うことができ、ひいては、半導体チップを安
価に製造するために重要なことがらとなっている。
[Prior Art] Non-volatile semiconductor memory integrated circuits have a structure in which a semiconductor integrated circuit mounted on a semiconductor chip electrically writes data and erases the data by irradiating ultraviolet light, or In the case of a non-volatile semiconductor memory integrated circuit with an electrical structure, writing per byte,
Or, since the erasing time requires several milliseconds,
A test time of several seconds is required with a storage capacity of 1 kilobyte. Therefore, by selecting only semiconductor memory integrated circuits between semiconductor chips and performing parallel measurements on the semiconductor memory integrated circuits in parallel, measurement work at the time of shipment can be carried out efficiently, and as a result, semiconductor chips This is an important point for manufacturing at low cost.

【0003】ところで、前記半導体記憶集積回路が単品
として半導体チップに搭載されている場合には何ら問題
がないが、マイクロコンピューター等に用いる半導体チ
ップでは、半導体記憶集積回路のみが単品として搭載さ
れる場合は少なく、他の半導体集積回路等と混在して搭
載される場合が多い。従来、上記のように混在する場合
に、半導体記憶集積回路のパッドを集めて半導体チップ
の特定位置に配置することは行われていなかった。
By the way, there is no problem when the semiconductor memory integrated circuit is mounted as a single item on a semiconductor chip, but when only the semiconductor memory integrated circuit is mounted as a single item on a semiconductor chip used for a microcomputer, etc. There are few semiconductor integrated circuits, and they are often mounted together with other semiconductor integrated circuits. Conventionally, when pads of semiconductor memory integrated circuits are mixed as described above, pads of semiconductor memory integrated circuits have not been collected and arranged at specific positions on a semiconductor chip.

【0004】そのため、図3(a)に示す半導体チップ
301上の全てのパッド302に、図3(b)に示すよ
うに測定プローブ304,305,306,307を接
触させ、プローブ304と305、306と307には
同一の信号を与えて測定を可能にしている。
Therefore, all the pads 302 on the semiconductor chip 301 shown in FIG. 3(a) are brought into contact with measurement probes 304, 305, 306, 307 as shown in FIG. 3(b), and the probes 304, 305, The same signal is given to 306 and 307 to enable measurement.

【0005】[0005]

【発明が解決しようとする課題】したがって、従来マイ
クロコンピュータ等に用いる半導体チップ相互間の半導
体記憶集積回路のみを選択して、複数の半導体チップの
半導体記憶集積回路に対する並列測定を並行して行うこ
とができず、測定作業が非能率となり、ひいては、この
種の半導体チップを安価に製造することができないとい
う問題があった。
[Problem to be Solved by the Invention] Therefore, it is necessary to select only the semiconductor memory integrated circuits between semiconductor chips used in conventional microcomputers, etc., and perform parallel measurements on the semiconductor memory integrated circuits of a plurality of semiconductor chips in parallel. There was a problem in that this type of semiconductor chip could not be manufactured at low cost, resulting in inefficient measurement work.

【0006】本発明の目的は、前記課題を解決した半導
体チップ及び半導体チップ特性測定用プローブ装置を提
供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor chip and a probe device for measuring semiconductor chip characteristics that solve the above-mentioned problems.

【0007】[0007]

【課題を解決するための手段】前記目的を達成するため
、本発明に係る半導体チップにおいては、並列測定を行
う特性測定対象の半導体集積回路と、その他の半導体集
積回路等とが混在してなる半導体チップであって、特性
測定対象の半導体集積回路は、測定プローブを接触させ
る測定に必要なパッドが半導体チップの一辺に沿わせて
配列されたものである。
[Means for Solving the Problems] In order to achieve the above object, a semiconductor chip according to the present invention includes a semiconductor integrated circuit whose characteristics are to be measured in parallel, and other semiconductor integrated circuits, etc. BACKGROUND ART A semiconductor integrated circuit, which is a semiconductor chip and whose characteristics are to be measured, has pads necessary for measurement, which are brought into contact with a measurement probe, arranged along one side of the semiconductor chip.

【0008】また、前記特性測定対象の半導体集積回路
は、データを電気的に書き込み、そのデータを紫外線の
照射により消去する構造の不揮発性半導体記憶集積回路
、あるいはデータの書き込み及び消去を電気的に行う構
造の不揮発性半導体集積回路である。
The semiconductor integrated circuit to be measured is a non-volatile semiconductor memory integrated circuit having a structure in which data is written electrically and the data is erased by irradiation with ultraviolet rays, or a non-volatile semiconductor memory integrated circuit in which data is written and erased electrically. It is a non-volatile semiconductor integrated circuit with a structure that

【0009】また、本発明に係る半導体チップ特性測定
用プローブ装置においては、半導体チップに搭載され、
並列測定が必要な特性測定対象の半導体集積回路の測定
に必要なパッドに測定プローブを接触させ、該測定プロ
ーブを通して半導体チップの動作に必要な電源又は信号
の送受を行うプローブ装置であって、特性測定対象の半
導体集積回路の測定プローブが接触するパッドは、半導
体チップの一辺に沿わせて配列されたものであり、測定
プローブは、前記パッドの列に対応して配列されたもの
であり、少なくとも2組備えており、2組の測定プロー
ブは、隣接した半導体チップの配列方向に位置決めして
配置されているものである。
Further, in the probe device for measuring semiconductor chip characteristics according to the present invention, the probe device mounted on the semiconductor chip,
A probe device that brings a measurement probe into contact with a pad necessary for measuring a semiconductor integrated circuit whose characteristics require parallel measurement, and sends and receives power or signals necessary for the operation of the semiconductor chip through the measurement probe, The pads that the measurement probes of the semiconductor integrated circuit to be measured come into contact with are arranged along one side of the semiconductor chip, and the measurement probes are arranged corresponding to the rows of pads, and at least Two sets of measurement probes are provided, and the two sets of measurement probes are positioned and arranged in the arrangement direction of adjacent semiconductor chips.

【0010】0010

【作用】半導体チップ内に搭載され並列測定すべき特性
測定対象の半導体集積回路は、測定プローブが接触する
パッドが半導体チップの一辺に沿って配列されており、
一方プローブ装置の測定プローブは、前記パッド列に対
応して配列され、少なくとも2組備えられている。した
がって、隣接した半導体チップの並列測定すべき特性測
定対象の半導体集積回路の測定に必要なパッドに2組の
測定プローブを並列に接触させて、隣接した半導体チッ
プ相互間での半導体集積回路の並列測定を行うことが可
能となる。
[Operation] The semiconductor integrated circuit that is mounted on a semiconductor chip and whose characteristics are to be measured in parallel has pads that the measurement probe comes into contact with are arranged along one side of the semiconductor chip.
On the other hand, at least two sets of measurement probes of the probe device are arranged corresponding to the pad rows. Therefore, parallel measurement of semiconductor integrated circuits between adjacent semiconductor chips is carried out by contacting two sets of measurement probes in parallel to the pads necessary for measuring the semiconductor integrated circuit to be measured. It becomes possible to perform measurements.

【0011】[0011]

【実施例】以下、本発明の実施例を図により説明する。[Embodiments] Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

【0012】(実施例1)図1(a)は、本発明の実施
例1を示す半導体チップの平面図、(b)は並列測定す
る状態を示す図である。
(Embodiment 1) FIG. 1(a) is a plan view of a semiconductor chip showing Embodiment 1 of the present invention, and FIG. 1(b) is a diagram showing a state of parallel measurement.

【0013】図において、本発明に係る半導体チップ1
01は、並列測定を行う必要がある特性測定対象の半導
体集積回路102、その他半導体集積回路103,10
4,105、106とが混在して搭載してあり、その相
互間に接続配線107〜110が付設してある。
In the figure, a semiconductor chip 1 according to the present invention is shown.
01 is a semiconductor integrated circuit 102 whose characteristics need to be measured in parallel, and other semiconductor integrated circuits 103 and 10.
4, 105, and 106 are installed in a mixed manner, and connecting wires 107 to 110 are provided between them.

【0014】さらに、特性測定対象の半導体集積回路1
02に対して電源又は信号の送受を行うパッド111a
,111a,111a…は、半導体チップ101の長辺
101a,に沿って配列してある。また、半導体集積回
路103,104,105に対して電源又は信号の送受
を行うパッド111b,111b…,111c,111
c…,111d,111d…が半導体チップ101の長
辺101b又は短辺101c,101dに沿って配列し
てある。
Furthermore, the semiconductor integrated circuit 1 whose characteristics are to be measured
Pad 111a for transmitting and receiving power or signals to and from 02
, 111a, 111a, . . . are arranged along the long side 101a of the semiconductor chip 101. In addition, pads 111b, 111b..., 111c, 111 transmit and receive power or signals to and from the semiconductor integrated circuits 103, 104, 105.
c..., 111d, 111d... are arranged along the long side 101b or the short sides 101c, 101d of the semiconductor chip 101.

【0015】前記特性測定対象の半導体集積回路102
は、データを電気的に書き込み、そのデータを紫外線の
照射により消去する構造の不揮発性半導体記憶集積回路
、あるいはデータの書き込み及び消去を電気的に行う構
造の不揮発性半導体記憶集積回路からなる。
Semiconductor integrated circuit 102 whose characteristics are to be measured
The non-volatile semiconductor memory integrated circuit has a structure in which data is written electrically and the data is erased by irradiation with ultraviolet rays, or the non-volatile semiconductor memory integrated circuit has a structure in which data is written and erased electrically.

【0016】また、本発明に係る半導体チップ特性測定
用プローブ装置は、特性測定対象の半導体集積回路10
2のパッド111a、又は半導体集積回路103,10
4,105のパッド111b,111c,111dに接
触させる測定プローブ112,113,114,115
を少なくとも2組以上(実施例では4組)をパッド11
1a又は111b,111e,111dに対応して備え
ており、これらの組の測定プローブ112,113,1
14,115を、隣接した半導体チップ101の配列方
向に位置決めして配置したものである。
Further, the probe device for measuring semiconductor chip characteristics according to the present invention can be used to measure the characteristics of a semiconductor integrated circuit 10.
No. 2 pad 111a or semiconductor integrated circuit 103, 10
Measurement probes 112, 113, 114, 115 to be brought into contact with pads 111b, 111c, 111d of 4,105
At least two or more sets (four sets in the embodiment) of the pad 11
1a or 111b, 111e, 111d, and these sets of measurement probes 112, 113, 1
14 and 115 are positioned and arranged in the arrangement direction of adjacent semiconductor chips 101.

【0017】図1(b)は、図1(a)の半導体チップ
101が半導体基板上に配置され、特性測定用のプロー
ブ装置の測定プローブが測定に必要なパッドに接触され
ている状態を示すものである。本実施例では、半導体チ
ップ101を4個並列に測定する場合を示している。図
1(b)に示す例では、隣接した半導体チップ101相
互間の図1(a)に示す半導体集積回路102を並列に
測定している。図1(a)においては、半導体チップ上
に電源線,接地線は、特に記入していないが、並列測定
している半導体集積回路102のみだけでなく、必要に
応じて他の半導体集積回路に供給する必要がある。また
、電源電圧及び接地電圧を与えるプローブ用パッドは、
必要に応じて複数存在することもあり、さらに図1(b
)でプローブ用の接触用パッドの中には、後工程でボン
ディングされない測定専用のパッドがあってもよい。図
1(b)において、測定プローブ113,114,11
5,116には、同一の信号が入力されている。図1(
b)に示したA及びBは、それぞれ図1(a)に示した
半導体チップ101の辺の長さに等しい。
FIG. 1(b) shows a state in which the semiconductor chip 101 of FIG. 1(a) is placed on a semiconductor substrate, and a measurement probe of a probe device for measuring characteristics is in contact with a pad necessary for measurement. It is something. This embodiment shows a case where four semiconductor chips 101 are measured in parallel. In the example shown in FIG. 1(b), the semiconductor integrated circuits 102 shown in FIG. 1(a) between adjacent semiconductor chips 101 are measured in parallel. In FIG. 1(a), the power supply line and ground line on the semiconductor chip are not particularly drawn, but they can be connected not only to the semiconductor integrated circuit 102 being measured in parallel but also to other semiconductor integrated circuits as necessary. need to be supplied. In addition, the probe pad that provides the power supply voltage and ground voltage is
There may be more than one if necessary, and in addition, Figure 1 (b
), among the contact pads for the probe, there may be pads dedicated to measurement that are not bonded in a subsequent process. In FIG. 1(b), measurement probes 113, 114, 11
The same signal is input to 5 and 116. Figure 1 (
A and B shown in b) are each equal to the length of the side of the semiconductor chip 101 shown in FIG. 1(a).

【0018】(実施例2)図2(a),(b),(c)
は、本発明の実施例2を示す図である。
(Example 2) FIGS. 2(a), (b), (c)
FIG. 2 is a diagram showing Example 2 of the present invention.

【0019】本実施例では、図2(a)に示すように、
半導体チップ201上には、半導体集積回路202〜2
06、それらを相互に接続する配線207〜210に設
けられ、さらにチップ周辺には、測定プローブを接触さ
せるパッド211a,211b,211c,211dが
チップ201の長辺201a,201b又は短辺201
c,201dに沿って設けられている。また図2(b)
,(c)に示すように、プローブ装置の測定プローブ2
12〜215、218〜220は、パッド211a,2
11b,211c,211dに対応して配列されている
。図2(b),図2(c)は半導体チップ201が半導
体基板上に配置されている状態で、特性測定用のプロー
ブ装置の測定プローブがパッドに接触されている状態を
示すものである。
In this embodiment, as shown in FIG. 2(a),
On the semiconductor chip 201 are semiconductor integrated circuits 202 to 2.
06, pads 211a, 211b, 211c, and 211d are provided on the wirings 207 to 210 that interconnect them, and around the chip, pads 211a, 211b, 211c, and 211d are provided on the long sides 201a and 201b of the chip 201 or on the short sides 201 and 211d, which are in contact with measurement probes.
c, along 201d. Also, Figure 2(b)
, (c), the measurement probe 2 of the probe device
12-215, 218-220 are pads 211a, 2
11b, 211c, and 211d. FIGS. 2(b) and 2(c) show a state in which the semiconductor chip 201 is placed on a semiconductor substrate and a measurement probe of a probe device for measuring characteristics is in contact with a pad.

【0020】本実施例では、半導体チップ201を4個
並列に測定する場合を示している。図2(b)の例では
、図2(a)の半導体集積回路202同士を並列に測定
している。また図2(c)の例では、図2(a)の半導
体集積回路204と205とを並列測定している。本実
施例では、半導体チップの異なる辺に複数の半導体集積
回路の測定パッドを配置し、異なるプローブ装置を用意
することにより、複数の半導体集積回路を並列に測定す
ることが可能である。図2(c)のように、半導体チッ
プの一辺に面するパッドのうち、並列測定に用いないも
のがあってもよい。
This embodiment shows a case where four semiconductor chips 201 are measured in parallel. In the example of FIG. 2(b), the semiconductor integrated circuits 202 of FIG. 2(a) are measured in parallel. In the example of FIG. 2(c), the semiconductor integrated circuits 204 and 205 of FIG. 2(a) are measured in parallel. In this embodiment, by arranging the measurement pads of a plurality of semiconductor integrated circuits on different sides of a semiconductor chip and preparing different probe devices, it is possible to measure a plurality of semiconductor integrated circuits in parallel. As shown in FIG. 2C, some pads facing one side of the semiconductor chip may not be used for parallel measurement.

【0021】図2(b),(c)において、測定プロー
ブ213,214,215,216と、218,219
,220,221とはそれぞれ同一の信号線が接続され
る。
In FIGS. 2(b) and 2(c), measurement probes 213, 214, 215, 216 and 218, 219
, 220, and 221 are connected to the same signal line, respectively.

【0022】[0022]

【発明の効果】以上説明したように本発明は、並列測定
を行う半導体集積回路の測定プローブが接触するパッド
を半導体チップの一辺に面するように配置するようにし
たので、並列測定を行う半導体集積回路の測定のための
測定時間をn個並列測定する場合には、1/nに短縮す
ることができ、特に電気的に記憶内容が可変な不揮発性
半導体記憶集積回路の特性測定に有効である。
Effects of the Invention As explained above, in the present invention, the pads that the measurement probes of semiconductor integrated circuits that perform parallel measurements come into contact with are arranged so as to face one side of the semiconductor chip. When measuring n integrated circuits in parallel, the measurement time can be reduced to 1/n, and is particularly effective for measuring the characteristics of non-volatile semiconductor memory integrated circuits whose storage contents are electrically variable. be.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】(a)は、本発明の実施例1に係る半導体集積
回路の配置図、(b)は、半導体集積回路にプローブ用
装置を接触させた状態の平面図である。
FIG. 1(a) is a layout diagram of a semiconductor integrated circuit according to a first embodiment of the present invention, and FIG. 1(b) is a plan view of a state in which a probe device is brought into contact with the semiconductor integrated circuit.

【図2】(a)は、本発明の実施例2に係る半導体集積
回路の配置図、(b),(c)は、半導体集積回路にプ
ローブ装置を接触させた状態の平面図である。
FIG. 2(a) is a layout diagram of a semiconductor integrated circuit according to a second embodiment of the present invention, and FIGS. 2(b) and 2(c) are plan views of a state in which a probe device is brought into contact with the semiconductor integrated circuit.

【図3】(a)は、従来技術の半導体集積回路の配置図
、(b)は、半導体集積回路にプローブ装置を接触させ
た状態の平面図である。
FIG. 3(a) is a layout diagram of a conventional semiconductor integrated circuit, and FIG. 3(b) is a plan view of a state in which a probe device is brought into contact with the semiconductor integrated circuit.

【符号の説明】[Explanation of symbols]

101,201  半導体チップ 102〜106,202〜206  半導体集積回路1
11a,111b,111c,111d,211,21
1a,211b,211c,211d  測定ブロープ
が接触するパッド 112〜115,212〜215,218〜220  
測定プローブ
101, 201 semiconductor chips 102-106, 202-206 semiconductor integrated circuit 1
11a, 111b, 111c, 111d, 211, 21
1a, 211b, 211c, 211d Pads 112-115, 212-215, 218-220 with which the measuring probe comes into contact
measurement probe

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  並列測定を行う特性測定対象の半導体
集積回路と、その他の半導体集積回路等とが混在してな
る半導体チップであって、特性測定対象の半導体集積回
路は、測定プローブを接触させる測定に必要なパッドが
半導体チップの一辺に沿わせて配列されたものであるこ
とを特徴とする半導体チップ。
[Claim 1] A semiconductor chip consisting of a semiconductor integrated circuit whose characteristics are to be measured in parallel and other semiconductor integrated circuits, etc., in which the semiconductor integrated circuit whose characteristics are to be measured is brought into contact with a measurement probe. A semiconductor chip characterized in that pads necessary for measurement are arranged along one side of the semiconductor chip.
【請求項2】  前記特性測定対象の半導体集積回路は
、データを電気的に書き込み、そのデータを紫外線の照
射により消去する構造の不揮発性半導体記憶集積回路、
あるいはデータの書き込み及び消去を電気的に行う構造
の不揮発性半導体集積回路であることを特徴とする請求
項1に記載の半導体チップ。
2. The semiconductor integrated circuit whose characteristics are to be measured is a non-volatile semiconductor memory integrated circuit having a structure in which data is written electrically and the data is erased by irradiation with ultraviolet light;
2. The semiconductor chip according to claim 1, wherein the semiconductor chip is a nonvolatile semiconductor integrated circuit having a structure in which writing and erasing of data is performed electrically.
【請求項3】  半導体チップに搭載され、並列測定が
必要な特性測定対象の半導体集積回路の測定に必要なパ
ッドに測定プローブを接触させ、該測定プローブを通し
て半導体チップの動作に必要な電源又は信号の送受を行
うプローブ装置であって、特性測定対象の半導体集積回
路の測定プローブが接触するパッドは、半導体チップの
一辺に沿わせて配列されたものであり、測定プローブは
、前記パッドの列に対応して配列されたものであり、少
なくとも2組備えており、2組の測定プローブは、隣接
した半導体チップの配列方向に位置決めして配置されて
いることを特徴とする半導体チップ特性測定用プローブ
装置。
3. A measurement probe is brought into contact with a pad necessary for measuring a semiconductor integrated circuit mounted on a semiconductor chip and whose characteristics need to be measured in parallel, and power or signals necessary for the operation of the semiconductor chip are measured through the measurement probe. The pads that the measurement probes of the semiconductor integrated circuit whose characteristics are to be measured come into contact with are arranged along one side of the semiconductor chip, and the measurement probes are arranged along one side of the semiconductor chip. A probe for measuring characteristics of a semiconductor chip, comprising at least two sets of probes arranged in a corresponding manner, the two sets of measurement probes being positioned and arranged in the arrangement direction of adjacent semiconductor chips. Device.
JP3133558A 1991-05-09 1991-05-09 Semiconductor chip and probe device for measuring semiconductor chip property Pending JPH04334042A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3133558A JPH04334042A (en) 1991-05-09 1991-05-09 Semiconductor chip and probe device for measuring semiconductor chip property

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3133558A JPH04334042A (en) 1991-05-09 1991-05-09 Semiconductor chip and probe device for measuring semiconductor chip property

Publications (1)

Publication Number Publication Date
JPH04334042A true JPH04334042A (en) 1992-11-20

Family

ID=15107618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3133558A Pending JPH04334042A (en) 1991-05-09 1991-05-09 Semiconductor chip and probe device for measuring semiconductor chip property

Country Status (1)

Country Link
JP (1) JPH04334042A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449740B1 (en) 1998-08-05 2002-09-10 Nec Corporation Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449740B1 (en) 1998-08-05 2002-09-10 Nec Corporation Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode

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