JPH0433156B2 - - Google Patents
Info
- Publication number
- JPH0433156B2 JPH0433156B2 JP59030525A JP3052584A JPH0433156B2 JP H0433156 B2 JPH0433156 B2 JP H0433156B2 JP 59030525 A JP59030525 A JP 59030525A JP 3052584 A JP3052584 A JP 3052584A JP H0433156 B2 JPH0433156 B2 JP H0433156B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- solder
- wiring conductor
- forming
- solder layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 229920001721 polyimide Polymers 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 description 39
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 239000002245 particle Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000013020 steam cleaning Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、電子機器に使用される回路板へのは
んだ層形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for forming a solder layer on a circuit board used in electronic equipment.
従来例の構成とその問題点
印刷回路板の配線層へのはんだ層の形成には、
従来、はんだ層形成部分を開口した樹脂レジスト
層を用いて、その開口部分を溶融はんだに接触さ
せて付着整形する方法が用いられる。この場合、
樹脂レジスト層は、たとえば、スクリーン印刷法
により、選択的に塗布し、適当な硬化処理を施し
て、定着固定されるもので、配線層へのはんだ層
形成後、同層上に装着電子部品をはんだ付けした
のちにも保護層として残存させることが多い。し
かしながら、この樹脂レジスト層上には、はんだ
層形成過程で飛散付着した粒状の微細はんだ物が
残存することがある。これを除去するために、フ
レオン、トリクレン、クロロセン等の蒸気洗浄手
段を用いることもあるが、この洗浄過程で全ての
残存物を確実に除去することは難しく、また、樹
脂レジスト層の電気的絶縁性能の劣化も無視でき
ない。Conventional structure and its problems When forming a solder layer on the wiring layer of a printed circuit board,
Conventionally, a method has been used in which a resin resist layer with openings in the solder layer forming portion is used, and the opening portion is brought into contact with molten solder to adhere and shape the resin resist layer. in this case,
The resin resist layer is selectively applied by, for example, a screen printing method, and then fixed and fixed by an appropriate curing treatment. After forming a solder layer on the wiring layer, electronic components are mounted on the same layer. It is often left as a protective layer even after soldering. However, fine granular solder particles scattered during the solder layer formation process may remain on this resin resist layer. In order to remove this, steam cleaning means such as freon, trichlene, and chlorocene are sometimes used, but it is difficult to reliably remove all the residue during this cleaning process, and the electrical insulation of the resin resist layer The deterioration in performance cannot be ignored either.
発明の目的
本発明は、上述の従来例にみられた問題点を解
消するもので、はんだ層形成過程で飛散付着した
粒状の微細はんだ物を確実に除去することが可能
なはんだ層形成方法を提供するものである。OBJECT OF THE INVENTION The present invention solves the problems seen in the above-mentioned conventional examples, and provides a solder layer forming method that can reliably remove granular fine solder particles scattered and attached during the solder layer forming process. This is what we provide.
発明の構成
本発明は、配線導体層を配設した絶縁基板上
に、前記配線導体層の所定部分を選択的に露出す
るように成形された開口部を有する耐溶融はんだ
性のレジストフイルムを少なくとも２層合体して
接着し、前記開口部に溶融はんだ層を被着したの
ち、前記レジストフイルムの上層を剥離除去する
工程をそなえたもので、これにより、洗浄過程な
しに、レジスト層上に付着した残存物を除くこと
ができる。Structure of the Invention The present invention provides at least a molten solder resistant resist film having an opening formed to selectively expose a predetermined portion of the wiring conductor layer on an insulating substrate on which a wiring conductor layer is disposed. The method includes a step of combining and adhering the two layers, applying a molten solder layer to the opening, and then peeling off and removing the upper layer of the resist film. It is possible to remove the residue left behind.
実施例の説明
第１図〜第３図は本発明実施例の過程を示す工
程順断面図である。これら各図を参照して、本発
明を実施例により詳しくのべる。DESCRIPTION OF THE EMBODIMENTS FIGS. 1 to 3 are sequential cross-sectional views showing the steps of an embodiment of the present invention. With reference to these figures, the present invention will be described in more detail by way of examples.
まず、第１図のように、絶縁基板１に配線導体
層２をパターン形成し、この上に、配線導体層２
の所定部分を露出させて、２層のポリイミドフイ
ルム３，４を重ねて張り合わせる。ポリイミドフ
イルム３，４は、それぞれ、厚さ５〜50μｍで、
その一面に、シリコン樹脂あるいはポリイミド樹
脂のオリゴマーを１〜5μｍの厚さに塗布して、
同面を絶縁基板１上に接着して、重ね合わせるこ
とにより積層化されたものである。なお、ポリイ
ミドフイルム３，４は、予め配線導体層２の所定
部分が露出されるように、たとえば、鋭利な刃物
で切断加工して、開口部５を形成したものを用い
る。 First, as shown in FIG. 1, the wiring conductor layer 2 is patterned on the insulating substrate 1, and the wiring conductor layer 2
Two layers of polyimide films 3 and 4 are laminated together with a predetermined portion exposed. The polyimide films 3 and 4 each have a thickness of 5 to 50 μm,
On one side, apply silicone resin or polyimide resin oligomer to a thickness of 1 to 5 μm,
The same side is bonded onto an insulating substrate 1 and stacked by overlapping. Note that the polyimide films 3 and 4 used are those in which openings 5 are formed in advance by cutting with a sharp knife, for example, so that a predetermined portion of the wiring conductor layer 2 is exposed.
次に、この基板１上の配線導体層２を溶融はん
だ浴に浸して、第２図のように、その露出面に、
はんだ層６を形成する。このはんだ層６の形成過
程で、ポリイミドフイルム４の表面に微細はんだ
物７が付着する。 Next, the wiring conductor layer 2 on the substrate 1 is immersed in a molten solder bath, and as shown in FIG.
A solder layer 6 is formed. During the process of forming the solder layer 6, fine solder particles 7 adhere to the surface of the polyimide film 4.
第３図は、ポリイミドフイルム４を剥離除去し
たもので、この状態で、はんだ層６の形成が完了
する。経験によると、粘着物質にシリコン樹脂あ
るいはポリイミド樹脂のオリゴマーを用いて接着
すると、絶縁基板１と下層のポリイミドフイルム
３との接着力は強く、一方、下層ポリイミドフイ
ルム３と上層ポリイミドフイルム４との接着力
は、それより弱いから、両層間での剥離は比較的
容易に行なわれる。なお、最終的には、下層のポ
リイミドフイルム３を保護層として残存させるこ
とができる。 FIG. 3 shows the polyimide film 4 peeled off and removed, and in this state the formation of the solder layer 6 is completed. According to experience, when adhesive material is bonded using silicone resin or polyimide resin oligomer, the adhesive force between the insulating substrate 1 and the lower layer polyimide film 3 is strong, while the bond between the lower layer polyimide film 3 and the upper layer polyimide film 4 is strong. Since the force is weaker than that, peeling between both layers is relatively easy. Note that, in the end, the lower polyimide film 3 can remain as a protective layer.
発明の効果
本発明によれば、予め、開口部の形成された複
数の耐溶融はんだ性のレジストフイルムを積層し
て回路基板面に張り合わせ、開口部に露出した配
線導体層上をはんだ層で被つたのち、上層のレジ
ストフイルムを剥離除去することにより、同レジ
スト上に飛散付着した残存物を取り除くことがで
きる。したがつて、本発明によれば、高品質のは
んだ層を形成し得るとともに、この回路板に電子
部品を装着した完成品も、高品質を達成すること
ができる。Effects of the Invention According to the present invention, a plurality of melted solder-resistant resist films having openings formed therein are laminated in advance and pasted on the circuit board surface, and the wiring conductor layer exposed in the openings is covered with a solder layer. After that, by peeling and removing the upper resist film, it is possible to remove the residue scattered on the resist. Therefore, according to the present invention, a high-quality solder layer can be formed, and a finished product obtained by mounting electronic components on this circuit board can also achieve high quality.
第１図〜第３図は本発明実施例の工程順断面図
である。
１……絶縁基板、２……配線導体層、３……下
層ポリイミドフイルム、４……上層ポリイミドフ
イルム、５……開口部、６……はんだ層、７……
微細はんだ物。
1 to 3 are cross-sectional views in the order of steps of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Wiring conductor layer, 3... Lower layer polyimide film, 4... Upper layer polyimide film, 5... Opening, 6... Solder layer, 7...
Fine solder items.
Claims (1)
線導体層の所定部分が選択的に露出するように形
成された開口部を有する耐溶融はんだ性のレジス
トフイルムを少なくとも２層合体して接着し、前
記開口部に溶融はんだ層を被着したのち、前記レ
ジストフイルムの上層を剥離除去する工程をそな
えたはんだ層形成方法。 ２ 耐溶融はんだ性のレジストフイルムがポリイ
ミドフイルムでなる特許請求の範囲第１項記載の
はんだ層形成方法。[Scope of Claims] 1. At least a molten solder resistant resist film having an opening formed to selectively expose a predetermined portion of the wiring conductor layer is provided on an insulating substrate on which a wiring conductor layer is disposed. A method for forming a solder layer, comprising the steps of combining and adhering two layers, applying a molten solder layer to the opening, and then peeling off and removing the upper layer of the resist film. 2. The method of forming a solder layer according to claim 1, wherein the molten solder resistant resist film is a polyimide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3052584A JPS60175485A (en) | 1984-02-20 | 1984-02-20 | Method of forming solder layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3052584A JPS60175485A (en) | 1984-02-20 | 1984-02-20 | Method of forming solder layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60175485A JPS60175485A (en) | 1985-09-09 |
| JPH0433156B2 true JPH0433156B2 (en) | 1992-06-02 |
Family
ID=12306221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3052584A Granted JPS60175485A (en) | 1984-02-20 | 1984-02-20 | Method of forming solder layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60175485A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0682707B2 (en) * | 1988-10-21 | 1994-10-19 | 日本電気株式会社 | Semiconductor device |
| JP4748889B2 (en) * | 2000-12-26 | 2011-08-17 | イビデン株式会社 | Manufacturing method of multilayer printed wiring board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5787195A (en) * | 1980-11-20 | 1982-05-31 | Kenwood Corp | Printed circuit |
-
1984
- 1984-02-20 JP JP3052584A patent/JPS60175485A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5787195A (en) * | 1980-11-20 | 1982-05-31 | Kenwood Corp | Printed circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60175485A (en) | 1985-09-09 |
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