JPH04331527A - Buffer malfunction monitor system - Google Patents

Abstract

PURPOSE:To detect abnormality by a single buffer in a transmission line regardless of a counter station by providing the buffer, read/write control part and HEC check part. CONSTITUTION:A buffer 1 stores an ATM cell. On the read side of the buffer, an HEC check part 3 is provided to execute a CRC check. When error is generated, a signal is outputted and according to the signal, the malfunction of the buffer is detected. In this case, a read/write control part 2 generates the R/W address or clock, etc., of the buffer 1. The buffer can be composed of a RAM in an address designating system or an ES memo in a clock control system. In the first case, a normal operating state can be restored after detecting the malfunction of the buffer by resetting an address and in the latter case, it is enabled by resetting the inside of a memory by stopping the clock. Thus, the abnormality can be detected for the unit of the buffer in the transmission line regardless of the counter station.

Description

[Detailed description of the invention]

0001

[Industrial Field of Application] The present invention is directed to ATM (Asynchronous
The present invention relates to a buffer malfunction monitoring method in a device that performs transmission using a ronous transfer mode. As recommended by the CCITT, in ATM transmission, information is sent and received in units of 53 octets called cells, regardless of the type of media being transmitted.

[0002] The first five octets of a cell are called an ATM header, and it contains a VPI (Vi
Virtual Path Identifier), VCI (Virtual Channel Identifier) that indicates the channel number
Identifier), H indicating the CRC operation result
It consists of parts such as EC (Header Error Control).

FIG. 4 shows an example of ATM cell transmission. Data sent from terminals 7 and 8 connected to transmission device 4 is converted into ATM cells by cell converters 13 and 14, and sent to demultiplexer 19. The demultiplexer 19 multiplexes data from these multiple terminals. This multiplexed data is sent to the transmission device 5, and is separated into data for the terminal 10 and data for the transmission device 6 at the demultiplexer 20 based on the information in the ATM header. Here, data from terminal 9 is also multiplexed at the same time, and eventually terminal 7
and 9 will be sent to the transmission device 6. The demultiplexer 21 that receives these data separates the data destined for the terminals 11 and 12 and sends the separated data to the terminals.

[0004] Transmission by the ATM method is performed as described above, but in the part that multiplexes and demultiplexes cells, even if another cell is input during processing of one cell, it is made to wait until the processing is completed. There is a need. Therefore, a buffer is provided in that area to prevent cells from being lost.

[0005]

2. Description of the Related Art In order to configure this buffer, RA
How to control Read/Write addresses using M etc., Re using FIFO (first in, first out) memory
There is a method of controlling using an ad/write clock (see FIG. 5). However, due to some reason such as noise, the Rea
If the value of the d or Write address deviates or the clocks overlap or disappear, the read ATM cell will become abnormal. Conventionally, when such a situation occurs, the abnormality can only be recognized in the form that the header of the abnormal ATM cell becomes different and the cell does not reach the opposite station. In other words, even if an abnormality occurs in a buffer on the transmission path, the abnormality is recognized only after the data reaches the receiving side via a larger number of buffers.

[0006]

[Problems to be Solved by the Invention] Therefore, a terminal can only recognize an abnormality by detecting that there is no response from the opposite terminal and recognizing it as an abnormality. Therefore, it takes a long time to detect an abnormality. was on. The present invention has been made in consideration of the above circumstances, and it is an object of the present invention to be able to detect an abnormality by using a buffer unit in a transmission path alone, regardless of the opposite station.

[0007]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a buffer, which stores ATM cells. Reference numeral 2 denotes a Read/Write control unit, which generates Read/Write addresses for the buffer 1, clocks, and the like. Reference numeral 3 denotes an HEC check section, which performs CRC calculation on the ATM header and detects errors.

[0008] The present invention is an ATM transmission method in which cells are once stored in a buffer provided in an ATM node and then sent out when the transmission line is empty. and
This is a buffer malfunction monitoring method characterized by outputting a signal when an error occurs, and using that signal to detect buffer malfunction.

[0009] The above buffer has an addressing scheme of R.
It can be configured with AM or clock-controlled ES memory. In the former configuration, by resetting the address, and in the latter case, by stopping the clock and resetting the memory, a buffer malfunction can be detected and then restored to a normal operating state.

0010

[Operation] In the present invention, as shown by reference numeral 3 in FIG.
Taking advantage of the fact that when the Read/Write control signal is abnormal, a data shift occurs and the CRC calculation result becomes an error, the Read/Write control unit 2 is notified when an error is detected, thereby returning the Read/Write control signal to its initial state. It works to restore normal operation.

[0011]

EXAMPLES The present invention will be described in detail below based on examples shown in the drawings. Note that the present invention is not limited to this. FIG. 2 is a configuration diagram showing one embodiment of the present invention, and A
It shows a buffer using RAM in a transmission device based on the TM system.

In the figure, the same components as those shown in FIG. 1 are denoted by the same symbols, and 1a is a RAM and
It stores TM cells. 1b is a flip-flop (hereinafter abbreviated as F/F), which latches the read data from the RAM 1a. 2a is a counter, which generates a high-order write address to the RAM 1a. 2b is a 53-decimal counter, R
This generates the octet number of the Write cell to AM1a. 2c is a counter, which generates the upper part of the Read address from the RAM 1a. 2d is a 53-decimal counter that generates the octet number of the Read cell from the RAM 1a. 2e is a write data buffer for enabling write data. In other words, the write data buffer is
Wr to prevent data being ead/written from colliding.
This is to allow input data to be entered only when ite. 2f is a selector and Write/Read
This is for selecting an address.

FIG. 3 is a time chart according to the present invention, which corresponds to the operation of the configuration shown in FIG. The counter 2a is output from the clock (Write CLK) synchronized with the input data and the signal (WriteHEAD) indicating the beginning of the cell.
and 2b generates a RAM write address. In addition, a clock (Read C
LK) and a signal for giving the cell start timing (
Read HEAD) to R at counters 2c and 2d.
Generates a read address for AM1a. These address signals are sent to the selector 2 according to the Read/Write switching timing signal (R/W signal).
f is selected and output as the address of RAM 1a. That is, when the R/W signal is "High", the address on the "1" side is output, so it becomes Read. On the other hand, R/W
When the signal is "Low", the "0" side address is output, so it becomes Write.

At the same time, the signal Write HEAD is 1
The clock enters F/F2g at the beginning position of the first cell, the output of F/F2g becomes “High”, and NAND2
i is enabled and input to WE of RAM1a. The same applies to OUTPUT enable. The data read from the RAM 1a is latched and adjusted by the F/F 1b, and then input to the HEC check section 3. C here
If the RC calculation result is OK, continue outputting, but
In the case of NG, it is recognized that the control signal is abnormal, and an error signal ERRDET "Low" is output. When this signal is output, all the counters 2a to 2d are reset and return to their initial states. Then, when the beginning of the next signal arrives, the count is restarted to restore the normal state. in this way,
After resetting the counter, F/F2g and 2h, NAND2i and 2j write WE (Write Enable) and OE (Output) of RAM1a up to the beginning of the first selector.
This is to prevent the occurrence of tEnable).

The configuration of the above-described embodiment can be provided in any buffer in the transmission path, so the reliability of data transmission improves as the number of buffers provided increases. For example, in the case of a transmitter, one location is provided on the output side, and in the case of a relay, one location is provided on each of the input and output sides, thereby making it possible to efficiently monitor abnormalities in ATM cells. Can be done.

[0016]

As described above, according to the present invention, malfunction of a buffer control signal can be detected regardless of the operation of the opposite station, which greatly contributes to improving the reliability of communication. In addition, the more the transmission is relayed, the more the present invention becomes effective.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a time chart of the configuration according to the present invention.

FIG. 4 is a block diagram showing an example of transmission using the ATM method.

FIG. 5 is a diagram of a buffer configuration according to the prior art.

[Explanation of symbols]

1 Buffer 1a RAM 1b F/F 2 Read/Write control unit 2a, 2c
Counters 2b, 2d 53-decimal counter 2e Write data buffer 2f Selector 2g, 2h F/F 2i, 2j NAND 3 HEC check section 4, 5, 6 Transmission device 13-18 Cell conversion section 19-21 Demultiplexing section

Claims (3)

[Claims] [Claim 1] In an ATM transmission method in which cells are temporarily stored in a buffer provided in an ATM node and then sent out when the transmission path is empty, a CRC check is performed on the reading side of the buffer in the transmission device. A buffer malfunction monitoring method is characterized in that a signal is output when an error occurs, and the signal is used to detect a buffer malfunction. 2. The buffer malfunction monitoring method according to claim 1 uses a RAM in the buffer to perform address control, detect a malfunction, and return the address to an initial state in response to an output error signal, thereby controlling the buffer. A buffer malfunction monitoring method that includes restoring normal operating conditions. [Claim 3] The buffer malfunction monitoring method according to claim 1 uses a first-in, first-out memory for the buffer, performs clock control, detects a malfunction, and clears the inside of the first-in, first-out memory in response to an output error signal. A buffer malfunction monitoring method that includes restoring the buffer to a normal operating state.