JPH04330829A - Coding and decoding device - Google Patents

Abstract

PURPOSE:To provide an coding and decoding device by which a code can be decoded with a small error, even when an erroneous transmission is reduced, and the information of a code length can not be obtained. CONSTITUTION:An A/D converter 1 converts a television signal into an 8 bit digital signal, and a blocking circuit 2 divides the output into blocks formed of the prescribed number of picture elements. A DCT circuit 3 operates a discrete cosine transformation, an adaptive quantizer 4 encodes a conversion factor obtained as the result after adaptively changing the number of quantizing bits so that a coding amount can be constant, and outputs both a code length (b) and additional information (c) which decides the code length. A rearranging circuit 5 operates the rearrangement of the codes of each conversion factor at every above mentioned block, and outputs a code string (e) in which the complete code which is not divided appears at each 8 bit. A multiplexer 6 receives this code string (e) and the additional information (c) from the adaptive quantizer 4, and outputs them to an error correcting encoder 7. The error correcting encoder 7 operates an error correcting encoding by using 8 bits as one word.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal encoding device and decoding device.

0002

[Prior Art] As a technology for highly efficient encoding of digital video signals, there is a known encoding technology that adaptively changes the code length based on statistical properties such as dispersion, dynamic range, and probability of occurrence of the video signal. There is. One of them is
There is a method of requantizing a digital signal with a smaller number of bits than the original number of bits. According to it, for example, 8
The variance of the bit-quantized signal for each fixed interval is calculated, and the signal of the interval is adaptively divided into 0 to 8 according to the variance.
It is requantized in bits, and as a result of encoding the requantized quantization value and the variance determining the quantization bit length are given as additional information.

[0003] The code encoded by this method is further encoded for error correction, and then transmitted or recorded on a digital VTR or the like. An example of a highly efficient error correcting code is a Reed-Solomon product code that detects and corrects errors on a word-by-word basis. Then, the transmitted or recorded code is decoded after error correction, but in that case, it is decoded from a quantized value based on the code length determined by the above-mentioned additional information.

0004

[Problems to be Solved by the Invention] When decoding a code encoded and recorded using the above-described encoding method, additional information may not be obtained. For example, in a digital VTR,
When performing high-speed reproduction, the head scans across multiple helical tracks, so it may not be possible to read all the recorded information, and additional information may not be read out. Alternatively, in an image transmission device, if noise or the like is mixed in, errors will occur in the additional information due to the influence. In such a case, since information regarding the bit length during encoding cannot be obtained, it becomes impossible to determine from which part of the code string to be decoded a single code ends, and in the end all codes cannot be decoded. It becomes possible.

Furthermore, if an error occurs during reproduction in a digital VTR, it is possible to restore the code to some extent using an error correction code, but the unit of restoration is one word in the case of a Reed-Solomon product code, for example. and,
In the case of a code string consisting of codes with different code lengths, usually
Since one word is composed of a plurality of codes, even if a certain word is corrected, the code may not be able to be reproduced. For example, if error correction is performed on a total of 32 bits of code strings w1 to w6 encoded with different code lengths as shown in FIG. 15, using 8 bits as one word, the first
. . . each fourth word will be processed. For example, if an error occurs in the first to third words and error correction is possible only in the second word, then the codes w2 and w3
Although it belongs to the second word, it becomes impossible to decode it due to errors in the first and third words.

An object of the present invention is to solve such problems, to make it possible to decode codes with small errors even without additional information for determining the code length, and to make it possible to decode codes with small errors that occur in a certain part of the code string. An object of the present invention is to provide an encoding device and a decoding device configured so that errors do not affect decoding of other parts.

[0007]

[Means for Solving the Problems] The encoding device of the present invention includes:
In order to achieve the above purpose, means for quantizing and generating codes by adaptively changing the bit length of an input signal according to its statistical properties, and dividing the codes sequentially output from the means into a fixed number of bits. The present invention is characterized in that it includes means for rearranging the code string such that a complete code that is not included in the code appears.

In order to achieve the above object, the decoding device of the present invention calculates the length of each code when a code string rearranged so that a complete code that is not divided into every certain number of bits appears is input. If code length information exists, the input code string is divided into continuous codes of complete codes that are not divided, based on the code length information, or according to a pre-stored code length pattern if the code length information does not exist. The present invention is characterized by comprising means for rearranging the code strings, and means for sequentially decoding the codes constituting the rearranged code strings.

[0009]

[Operation] The encoding device of the present invention distributes the input signal,
Quantization is performed by changing the bit length according to statistical properties such as dynamic range and probability of occurrence. Then, each code is divided and rearranged as necessary, thereby forming a code string in which at least one complete code appears for each fixed bit length, and processing such as error correction is performed. Output.

The decoding device of the present invention rearranges the code string sent from the encoding device into the original code string according to the code length information sent with the code string, and sequentially decodes each code. If code length information cannot be obtained due to the influence of noise, etc., the code length is determined according to a typical code length pattern stored in advance. Convert to a continuous code string. Since the undivided complete code contained in the code string sent from the encoding device appears at a predetermined period, it is possible to know where in the code string it starts, and therefore even if code length information is not obtained, the above By using the code length pattern, the code can be decoded with less error.

[0011]

EXAMPLES Next, examples of the present invention will be described in detail. FIG. 1 shows an example of an encoding device according to the present invention. This device performs discrete cosine transform on an analog television signal, adaptively quantizes the transform coefficients with different numbers of bits, and rearranges the codes in the resulting code string, which is a feature of the present invention. be.

When an analog television signal is input, the A/D converter 1 converts it into an 8-bit digital signal and outputs it to the blocking circuit 2. The blocking circuit 2 rearranges the digital signals into digital signals for each block of 8 pixels x 8 pixels, for example, and sequentially outputs the digital signals to a DCT (discrete cosine transform) circuit 3. The DCT circuit 3 performs discrete cosine transform on this blocked digital signal, thereby obtaining 8×8 transform coefficients. Then, the transform coefficients are sequentially outputted to the adaptive quantizer 4 starting from the lowest spatial frequency by, for example, zigzag scanning.

The adaptive quantizer 4 is a quantizer that adaptively changes the number of quantization bits so that the code amount is constant.
The statistics of the transform coefficients from the DCT circuit 3 are taken, the number of quantization bits is determined according to the statistics, and each coefficient is quantized to 8 bits or less. As a result, the adaptive quantizer 4 outputs a code string composed of codes of different code lengths. As a specific control method for keeping the code amount constant, for example, the method described in Japanese Patent Application No. 102643 can be used in units of one field. In this case, the additional information that determines the code length can be, for example, the variance and average value of 8×8 transform coefficients for each field, and the average number of quantization bits for each block.

From the adaptive quantizer 4, the additional information c for determining the code length is sent to the multiplexer 6, and the quantization result of each transform coefficient, that is, the code a, and the number of quantized bits of each transform coefficient, that is, the code The length b is output to the rearrangement circuit 5, respectively. A rearrangement circuit 5, which is a feature of this encoding device, rearranges the codes of each transform coefficient for each block, and outputs a code string e in which a complete code appears from the most significant bit every 8 bits.

The multiplexer 6 receives this code string e and the additional information c from the adaptive quantizer 4, and outputs it to the error correction encoder 7 as one channel data. The error correction encoder 7 performs error correction encoding using 8 bits as one word, for example, using a Reed-Solomon product code.

The rearrangement circuit 5 has a configuration as shown in FIG. The counter 16 receives the quantization bit number b, counts the total code length for each block, and outputs the quotient d obtained by dividing the result by 8. That is, as shown in the flowchart of FIG. 3, the counter 16 first sets the code length addition result i to 0, and sets j corresponding to the code number to 1 (step 301). Then, it is determined whether j is 64 or less (step 302). Since j is 1 and is less than or equal to 64, the code length l1 of the first code (i.e. code length b)
is added to i and j is increased by 1 (step 3
03). After that, the process returns to step 302, and from then on, j
Repeat the above steps until the number exceeds 64. And j
When exceeds 64, divide i by 8 and output the quotient d (step 304).

The switch 18 outputs a control signal to FIFO (first in, first out) buffers 19 and 20 based on the quotient d output by the counter, and sends the first to dth codes a of each block to the buffer 19. The d+1th and subsequent codes are stored in the buffer 20, respectively. Here, the code stored in the buffer 19 becomes a code that appears in a complete form every 8 bits, and the code stored in the buffer 20 becomes a code that is divided and added to the code in the buffer 19. The operation of the switch 18 will be specifically explained using the flowchart of FIG. The switch 18 first sets j corresponding to the code number to 1 (step 401), and then determines whether j is less than or equal to the quotient d (step 402). In this case, since j is smaller than d, the process proceeds to step 403, where i corresponding to the bit number of each code is set to 1. Then, it is determined whether or not i is less than or equal to the code length lj (step 404), and if i is less than or equal to the code length lj, the code bit Xj,i is input to the buffer 19 and i is incremented by 1 (step 405).
). Note that the code bits Xj,i are each bit of the code a, and Xj,i represents the i-th bit from the MSB of the j-th code. The switch 18 repeats steps 404 and 405 until i exceeds the code length lj, and when i exceeds the code length lj, it means that the storage of the first code is completed, so it increments j by 1 (step 406)
, repeat the steps from step 402 onwards. and,
After storing up to the d-th code in the buffer 19, the process proceeds to step 407. Thereafter, the codes after the (d+1)th code are sequentially stored in the buffer 20 through the same procedure, that is, steps 408 to 411.

The code length b and the quotient d output by the counter 16 are also input to the FIFO buffer 17 and stored therein. The selector 21 selects these code lengths b output from the buffer 17.
and the quotient d. That is, selector 2
1 takes out bits from the buffer 19 by the number of code lengths b and outputs them, and if the bits are less than 8 bits, the number of bits short of 8 bits is taken out from the buffer 20 and output. The selector 21 repeats this operation d times. To explain using the flowchart shown in FIG. 5, the selector 21 first sets j corresponding to the code number to 1 (
Step 501), then it is determined whether j is less than or equal to d (
Step 502). In this case, since j is less than or equal to d, next, i corresponding to the bit number of each code is set to 1 (step 503), and it is determined whether or not i is less than or equal to the code length lj (step 504). And when i is less than lj,
Take out 1 bit (Xj, i) from the buffer 19 and output it, and also increment i by 1 (step 505)
. Thereafter, steps 504 and 505 are repeated until i exceeds the code length lj, and when i exceeds lj, it means that the output of one complete code has been completed, so the process proceeds to step 506. Then, it is determined whether or not i is 8 or less, and if it is 8 or less, 1 bit is taken out from the buffer 20 and output,
Also, i is increased by 1 (step 507). Thereafter, the process returns to step 506 and steps 506 and 507 are repeated until i exceeds 8. 1 if i exceeds 8
Since the output of bits for a word has been completed, j is incremented by 1 in order to output the bits for the next word (step 508), and the process returns to step 502. Thereafter, the above-described procedure is repeated until j exceeds d and transmission of one block's worth of codes is completed.

Next, a case in which the codes w1 to w6 shown in FIG. 6(B) are input to the rearrangement circuit 5 will be specifically explained. The actual number of codes per block is 64, but here, for simplicity, it is assumed that the number of codes per block is 6. The reordering circuit 5 is given the codes w1 to w6 as well as their code lengths b shown in FIG. 6(A). Then, the counter 16 calculates the total code length b, and outputs the quotient 4 obtained by dividing the result 32 by 8 as the quotient d. The switch 18 controls the buffers 19 and 20, and stores the first four codes of the code string a in the buffer 19 and the remaining codes in the buffer 20, respectively, according to the value of d. As a result, the contents of the buffer 19 become as shown in FIG. 6(C), and the contents of the buffer 20 become as shown in FIG. 6(D). On the other hand, the buffer 17 stores the code length b (FIG. 6(A)) and the quotient d (=
4) are stored, and the selector 21 operates based on these values. That is, the selector 21 first takes out 7 bits from the buffer 19, then takes out 1 bit, which is the shortfall of 8 bits, from the buffer 20 and outputs it. Next, the selector 21 takes out 6 bits from the buffer 19 and 2 bits from the buffer 20 and outputs them. By repeating this operation four times, the selector 21 becomes
Output the code string shown in E).

FIG. 7 shows an example of a decoding device according to the present invention. This decoding device decodes the signal encoded by the aforementioned encoding device of the present invention. The error correction decoder 8 decodes the decoded input, that is, the code to be decoded, word by word (8 bits), and outputs the result to the demultiplexer 9. The demultiplexer 9 separates the additional information f and the code string g for each block, and outputs the additional information f to the code length calculator 10 and the code string g to the inverse rearrangement circuit 11. The code length calculator 10 calculates the code length h of each transform coefficient from the additional information f, and sends it to the inverse rearrangement circuit 11 and the inverse quantizer 1.
Output to 2. The code length calculator 10 stores code length patterns of typical blocks, and if an accurate code length cannot be calculated, it outputs the stored code length and also outputs a control signal o. .

The inverse reordering circuit 11 performs an operation opposite to that of the reordering circuit 5 on the code string g according to the code length h, and outputs a restored code string r. When the control signal o is input here, the read code is output only for codes that can be decoded with a small error when decoded with an appropriate code length, and for other codes, for example, 0 is output.

The inverse quantizer 12 performs inverse quantization based on the code string r from the inverse rearrangement circuit 11 and the code length h and control signal o from the code length calculator 10. When the control signal o is input, the inverse quantization value of the p-th and subsequent transform coefficients is output as 0 for the output value p of a counter described later in the inverse rearrangement circuit 11.

The inverse DCT circuit 13 performs inverse discrete cosine transform on the output of the inverse quantizer 12 to restore pixel values for each block. The block decomposition circuit 14 rearranges the restored pixel values for each block and outputs the original scanning signal. The D/A converter 15 converts this scanning signal from a digital signal to an analog signal and outputs it as an analog television signal.

The inverse rearrangement circuit 11 has the configuration shown in FIG. The code length h and control signal o from the code length calculator 10 and the code string g separated by the demultiplexer 9 are input to this circuit. The code length h is input to the FIFO buffer 22 and switch 24, and the code string g is input to the FIFO buffer 22 and switch 24.
The signal is input to the O buffer 23 and the counter 28. The counter 28 calculates the length of the code string for each block and adds up to 8
The quotient p divided by is output. That is, as shown in the flowchart of FIG. 9, i, which corresponds to the number of bits constituting a code string, is first set to 0 (step 901), and it is determined whether there is data input (step 902). Since there is data input, i is increased by 1 (step 903). Then, steps 902 and 903 are repeated until there is no more data input, and then i is divided by 8 to obtain the quotient p, which is output (step 904).

The code string stored in the buffer 23 is distributed to a FIFO buffer 25 and a FIFO buffer 26 by a switch 24. That is, the switch 24 outputs a control signal to the buffers 25 and 26, so that the bits corresponding to the code length h are stored in the buffer 25, and the missing bits from that number to 8 bits are stored in the buffer 26. do. As a result, the buffer 25 stores the complete code appearing every 8 bits, while the buffer 26 stores the divided code.

To explain using the flowchart shown in FIG. 10, the switch 24 first selects the i corresponding to the code number.
is set to 1 (step 101), and it is determined whether or not i is less than or equal to the quotient p (step 102). In this case, since i is smaller than the quotient p, k corresponding to the bit number is set to 1 (step 103). ). and k is the code length l of the i-th code
It is determined whether it is less than or equal to i (that is, code length h) (step 104), and in this case, since k is smaller than code length li, 1 bit is input from buffer 23 to buffer 25, and k is increased by 1. (Step 105). From then on, k
Steps 104 and 105 are repeated until k exceeds li, and when k exceeds li, the process proceeds to step 106. Then, it is determined whether k is 8 or less (step 106),
In this case, k is smaller than 8, so 1 bit is input from buffer 23 to buffer 26, and k is increased by 1. From then on, steps 106 and 107 until k exceeds 8.
is repeated, and when k exceeds 8, the process returns to step 102.
Repeat the above operations until i exceeds p.

The selector 27 switches to take out p codes first from the buffer 25 and then take out codes from the buffer 26 according to the code length h stored in the buffer 22. However, if the control signal o is input, that is, if the correct code length cannot be obtained, the code cannot be restored from the data in the buffer 26 using the code length in the buffer 22. The data from the buffer 26 is not used and is output as all 0s. To explain using the flowchart shown in FIG. 11, the selector 27 first sets k corresponding to the code number to 1 (step 1101), determines whether k is less than or equal to the quotient p (step 1012), and in this case, Since k is smaller than the quotient p, m corresponding to the bit number is set to 1 (step 10
13). Then, it is determined whether m is less than or equal to the code length lk of the k-th code (step 1104), and in this case, m
is smaller than lk, so 1 bit (X
k, m) and outputs it, and also increments m by 1. Thereafter, step 1104 until m exceeds lk;
Step 1105 is repeated, and when m exceeds lk, k is incremented by 1 and the process returns to step 1102. Then, the above operations are repeated, and when k exceeds p, the process proceeds to step 1106.

Here, the selector 27 determines whether or not the control signal o is being sent (step 1106), and if the control signal o is not being sent, it is determined whether k is less than or equal to 64 (step 1106). Step 1107), when k is 64 or less, n corresponding to the bit number is set to 1 (Step 110
8), it is determined whether n is less than or equal to the code length lk (step 1109). Then, when n is less than lk, buffer 2
1 bit (Xk, n) is extracted from 6 and outputted, and n is incremented by 1 (step 1110). From then on, n
Steps 1109 and 1110 are repeated until n exceeds lk, and when n exceeds lk, k is incremented by 1 and the process returns to step 1107, where the same processing is performed until k exceeds 64.

If the control signal o has been sent in step 1106, the buffer 26 is cleared (step 1111), and then it is determined whether or not k is 64 or less (step 1112). In the following cases, n is set to 1 (step 1113). Then, it is determined whether n is less than or equal to the code length lk, and if n is less than or equal to lk, one bit of information with a value of 0 is output, and n is increased by 1 (step 1115). Then, steps 1114 and 1115 are repeated until n exceeds lk, and when n exceeds lk, k is increased by 1 and the process returns to step 1112, and k becomes 6.
The above process is performed until the number exceeds 4.

Next, a case in which the codes w1 to w6 shown in FIG. 6(E) are input to the inverse rearrangement circuit 11 will be specifically explained. The actual number of codes per block is 64, but here again for the sake of simplicity it is assumed that the number of codes per block is 6. First, when the code length is accurately obtained, data representing the code length shown in FIG. 6(A) is input as the code length h. The counter 28 calculates the length of the code string for each block, and outputs the quotient 4 obtained by dividing the total by 8. The switch 24 controls the buffers 25 and 26, and transfers 7 bits from the beginning of the input code string to the buffer 25 according to the value 7 of the code length h.
1 bit is stored in the buffer 26, and the 1 bit missing from the 8 bits is stored in the buffer 26. Next, the switch 24 causes the buffer 25 to store 6 bits based on the value 6 of the code length h, and causes the buffer 26 to store the missing 2 bits. switch 24
repeats this operation four times, and as a result, the contents of the buffer 25 become as shown in FIG. 6(C), and the contents of the buffer 26 become as shown in FIG. 6(D). And selector 2
7 is stored in the buffer 22 according to the data of the code length shown in FIG.
Read and output data for 4 codes in the order of 6 bits, 5 bits, 5 bits, then 5 bits from the buffer 26,
Data for 2 codes is read out in 4-bit order and output. As a result, the original code string shown in FIG. 6(B) is restored.

Next, a case where the code length of each code cannot be accurately determined will be explained. Since the control signal o is input at this time, a code length different from the actual code length as shown in FIG. 12A, which is stored in advance as a typical pattern, is given as the code length h. The switch 24 controls the buffers 25 and 26 according to the code length of FIG. 12(A) for the code string of FIG. The contents are as shown in FIG. 12(D). Then, the selector 27 is
According to the data shown in FIG. 12A accumulated in the buffer 22, data is first read from the buffer 25. Next, since the control signal o is input, the selector 27 does not use the contents of the buffer 26, but sets the contents of the buffer 26 to 0 and outputs bit data with a value of 0. As a result, the selector 27 converts the bits with a value of 0 to 1 in the code string of FIG. 12(C).
The code string shown in FIG. 12(B) with 0 added will be output. Although this code string has not been accurately restored, since the codes w1 to w4 are individually stored in each word, the codes w1 to w4 can be decoded with small errors even if they are decoded as is.

[0032] Here, the fact that the codes w1 to w4 are decoded with small errors will be explained in detail. First, if the dynamic range for quantization is constant regardless of the number of bits for quantization, then if the high-order bits of the code are preserved, even if decoding is done with a number of bits different from the actual code length, it will still be correct. It will be explained that the error in the decoded value is smaller than when decoding is performed using the number of bits.

FIGS. 13A to 13C show examples of codes output by the uniform quantizer. In Figure 13(A), the level is -1
The codes output when a signal in the range from 27 to +127 is quantized with 2 bits are shown. FIG. 13(B) shows the code output when quantizing with 3 bits, and FIG. 13(C) shows the code output when quantizing with 4 bits. The codes output in each case are shown. For example, if the value +40 is quantized with 3 bits, it becomes 10
1 is output.

FIGS. 13(D) to 13(F) show examples of decoding results of quantized codes. Figure 13(F) is Figure 13(A)
13(E) and (D) show the decoding results of the 2-bit quantized code shown in FIG. 13(B) and (C), respectively.
) shows the decoding results of codes quantized with 3 bits and 4 bits, respectively. For example, when the code 101 quantized with 3 bits in FIG. 13(B) is decoded, the result is +47.

By the way, code 1 quantized with 3 bits
If the upper 2 bits are saved for 01 and the lower bits are discarded and decoded as a 2-bit code 10, Figure 13
From (F), the result is +31. Furthermore, when code 101 is left as is and 4-bit codes 1010 and 1011 are decoded by adding 1 bit to the lower order, the results are +39 and +55, respectively, as shown in FIG. 13(D). In other words, whether it is decoded with 2 bits or 4 bits, 3
A value close to +47 is obtained when decoding with bits.

Expressing this generally, when the lower limit of the range for quantization is DL and the upper limit is DH, the dynamic range D can be expressed as D=DH-DL. If the code obtained by quantizing the input value with n bits is a1, a2, ..., an from the upper bit, and the decoded value obtained by decoding with m bits is Rm, then Rn+1=DL+D/2・a1+... +D/2^n
・an+D/2^n+1・an+1+D/2^n+2,
Rn=DL+D/2・a1+... +D/2^n・a
n+D/2^n+1, Rn-1=DL+D/2・a1+... +D/2^n
It can be seen that the lower bits do not have a large effect on the decoded value.

[0037] By preserving the high-order bits of the code in this way, even if the code is decoded with a number of bits different from the actual code length, the code can be decoded with a small error. Note that in the above description, the dynamic range is constant, but even if the number of bits for quantization changes and the dynamic range fluctuates, the same result can be obtained if the degree of the fluctuation is not very large.

As described above, in the encoding device of this embodiment, when the length of the code string is n bits for a code string adaptively encoded with 0 to 8 bits, n bits from the beginning are /8
For these codes, the code strings are rearranged so that the most significant bit of each code appears every 8 bits. Therefore,
For example, the code string in FIG. 15 is rearranged as shown in FIG. 14. In this example, since the length of the code string is 32 bits, the first four codes w1 to w4 are left as they are so that they appear every 8 bits, and codes w5 and w6 are divided and added to the codes w1 to w4. has been done. In the decoding device of this embodiment, when additional information for determining the code length is obtained, the codes w1 to w6 can be restored by an operation opposite to the rearrangement in the encoding device. On the other hand, if additional information cannot be obtained, there is a code starting point for every 8 bits of the given code string, and each 8 bits contains one complete code, so these codes can be interpreted as appropriate. If decoding is performed with a code length of 1, the above-mentioned effect will result in decoding with less error.

Next, it will be explained that the encoded sequence obtained by the encoding apparatus of this embodiment is suitable for error correction. In the Reed-Solomon product code, error correction encoding is performed using a fixed length of one word as the minimum unit. For example, for a code encoded with a fixed length of 8 bits, error correction encoding is performed using 8 bits as one word. For example, the code string shown in FIG. 15, which is adaptively encoded with a maximum of 8 bits, is
In the encoding apparatus of this embodiment, the data is rearranged as shown in FIG. 14, and error correction encoding is performed using 8 bits of the code string as one word. By the way, each word in FIG. 14 always includes one (or more than one) undivided code. That is, one error correction word includes at least one code that is not affected by other words. Therefore, if an error occurring in a certain word can be corrected, at least one code can be decoded. In other words, the decoding of at least one code is not completely impossible due to an uncorrectable error occurring in a certain word, as is the case in the past. becomes possible.

In this embodiment, the transform coefficients output from the DCT circuit 3 are outputted by zigzag scanning, starting with the transform coefficients having a low spatial frequency, that is, those having a large visual impact. Then, the rearrangement circuit 5 rearranges the codes so that they appear every 8 bits in order from the code corresponding to the transform coefficient with the lowest spatial frequency. When decoding a code string rearranged in this way, if the code length cannot be obtained, the code that appears every 8 bits is decoded with a small error as described above, but the conversion with a low spatial frequency Since the codes are arranged in order starting from the code corresponding to the coefficient, the code will be decoded with a small error, and the effect when the code length cannot be obtained will be even smaller.

Furthermore, in this embodiment, the codes of the encoded transform coefficients obtained by performing the discrete cosine transform are rearranged, but the present invention is not limited to this example. , it is widely applicable to code strings obtained by adaptive quantization.

[0042]

As explained above, in the encoding device of the present invention, a code string consisting of a plurality of codes with different bit lengths is rearranged so that a complete code that is not divided into every certain number of bits appears. will be held. Therefore, even if information indicating the code length is lost, it is possible to know where in the code string a complete code that is not divided begins. In the decoding device of the present invention, when decoding the code string obtained by the encoding device, if the code length is unknown, decoding is performed using the code length of a typical pattern stored in advance. . Therefore, even if information regarding the code length is lost, it is possible to decode with small error. Additionally, as mentioned above, the codes are rearranged so that a complete code that is not divided into bits appears, so there is at least one code in one word that is not affected by errors in other words. This reduces error propagation. Therefore, even if the information for determining the code length cannot be read out or an error occurs during high-speed reproduction on a digital VTR, there is little deterioration in image quality.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an encoding device of the present invention.

FIG. 2 is a block diagram showing in detail a rearrangement circuit of the encoding device of FIG. 1;

FIG. 3 is a flowchart showing the operation of a counter forming the rearrangement circuit of FIG. 2;

FIG. 4 is a flowchart showing the operation of switches forming the rearrangement circuit of FIG. 2;

FIG. 5 is a flowchart showing the operation of a selector forming the rearrangement circuit of FIG. 2;

FIG. 6 is an explanatory diagram of code rearrangement by the rearrangement circuit of FIG. 2;

FIG. 7 is a block diagram showing an example of a decoding device of the present invention.

FIG. 8 is a block diagram showing in detail the inverse reordering circuit of the decoding device of FIG. 7;

FIG. 9 is a flowchart showing the operation of a counter in the inverse reordering circuit of FIG. 8;

FIG. 10 is a flowchart showing the operation of the switches in the inverse reordering circuit of FIG. 8;

FIG. 11 is a flowchart showing the operation of a selector forming the inverse reordering circuit of FIG. 8;

FIG. 12 is an explanatory diagram of code rearrangement by the inverse rearrangement circuit of FIG. 8;

FIG. 13 is an explanatory diagram of quantization and inverse quantization with various numbers of bits.

FIG. 14 is sorted by the sorting circuit of FIG. 2;
FIG. 3 is a diagram showing a code divided into words.

FIG. 15 is a diagram showing codes encoded with different numbers of bits.

FIG. 16 is a diagram illustrating an example of word division of a code string during error correction in a conventional encoding device.

[Explanation of symbols]

1 A/D converter 2 Blocking circuit 3 DCT circuit 4 Adaptive quantizer 5 Reordering circuit 6 Multiplexer 7 Error correction encoder 8 Error correction decoder 9 Demultiplexer 10 Code length calculator 11 Inverse reordering circuit 12 Inverse Quantizer 13 Inverse DCT circuit 14 Block decomposition circuit 15 D/A converter 16, 28 Counter 17, 19, 20, 22, 23, 25, 26 FIF
O buffer 18, 24 switch 21, 27 selector

Claims (2)

[Claims] Claim 1: A means for quantizing an input signal by adaptively changing the bit length according to its statistical properties to generate a code, and a code sequentially output from the means that is not divided into a fixed number of bits. 1. An encoding device comprising means for rearranging a code string such that a complete code appears. Claim 2: When a code string rearranged so that a complete code that is not divided into every certain number of bits appears is input, if code length information indicating the length of each code exists, means for rearranging the input code string into a continuous code string of undivided complete codes based on the code length information or according to a pre-stored code length pattern if the code length information does not exist; A decoding device comprising means for sequentially decoding codes constituting a code string.