JPH04330804A - Semiconductor - Google Patents
SemiconductorInfo
- Publication number
- JPH04330804A JPH04330804A JP1781291A JP1781291A JPH04330804A JP H04330804 A JPH04330804 A JP H04330804A JP 1781291 A JP1781291 A JP 1781291A JP 1781291 A JP1781291 A JP 1781291A JP H04330804 A JPH04330804 A JP H04330804A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric substrate
- recessed part
- face
- package
- microstrip transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims abstract description 17
- 238000007747 plating Methods 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 239000010949 copper Substances 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 229920005989 resin Polymers 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 229910052718 tin Inorganic materials 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は半導体装置に関し、特に
超高周波帯域にて使用するGaAs電界効果トランジス
タ(以下GaAsFETと記す)を有する半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a GaAs field effect transistor (hereinafter referred to as GaAsFET) used in an ultra-high frequency band.
【0002】0002
【従来の技術】従来のGaAsFETを有する半導体装
置は、図3及び図4に示すように、パッケージ1内に搭
載したGaAsFETチップ7に対する50Ω内部整合
回路をチップコンデンサ8によるキャパシタンス及び金
属細線9のインダクタンスによる集中定数的整合回路と
、誘電体基板4に設けられたマイクロストリップ伝送線
路10及びオープンスタブパターン11による分布定数
回路とを設けて構成していた。ここで、誘電体基板4は
パッケージ1の平坦な底面上にマウントされていた。2. Description of the Related Art As shown in FIGS. 3 and 4, a conventional semiconductor device having a GaAsFET has a 50Ω internal matching circuit for a GaAsFET chip 7 mounted in a package 1 using capacitance of a chip capacitor 8 and inductance of a thin metal wire 9. It was constructed by providing a lumped constant matching circuit according to the above, and a distributed constant circuit consisting of a microstrip transmission line 10 and an open stub pattern 11 provided on a dielectric substrate 4. Here, the dielectric substrate 4 was mounted on the flat bottom surface of the package 1.
【0003】0003
【発明が解決しようとする課題】上述した従来の半導体
装置は、整合回路を構成する入力側及び出力側の夫々の
誘電体基板上に設けたマイクロストリップ伝送線路によ
り、伝搬する電磁波が誘電体と自由空間に跨って伝搬し
ている。特に周波数が高くなると、誘電体基板から放射
される自由空間への電磁波が増加し、必然的に入力側及
び出力側の夫々に設けた誘電体基板のマイクロストリッ
プ伝送線路から放射される電磁波も増加し、パッケージ
内の自由空間内で干渉し合ってしまう。[Problems to be Solved by the Invention] In the conventional semiconductor device described above, the microstrip transmission lines provided on the dielectric substrates on the input and output sides of the matching circuit prevent the propagating electromagnetic waves from interfering with the dielectric. It propagates across free space. In particular, as the frequency increases, the electromagnetic waves radiated from the dielectric substrate into free space increase, and the electromagnetic waves radiated from the microstrip transmission lines of the dielectric substrate provided on the input and output sides also increase. However, they interfere with each other in the free space inside the package.
【0004】従って、GaAsFETの入出力間のアイ
ソレーションが悪くなり、超高周波帯に於ける整合状態
が崩れ、特性を低下させるという問題点があった。[0004] Therefore, there has been a problem that the isolation between the input and output of the GaAsFET deteriorates, the matching state in the ultra-high frequency band collapses, and the characteristics deteriorate.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置は、
パッケージ内に搭載した半導体チップと、前記パッケー
ジ内に搭載して前記半導体チップの入力側及び出力側に
接続しインピーダンス整合を行うマイクロストリップ伝
送線路を有する半導体装置において、前記マイクロスト
リップ伝送線路を形成した誘電体基板を前記パッケージ
の底面に設けた凹部内に埋込んで構成される。[Means for Solving the Problems] A semiconductor device of the present invention includes:
In a semiconductor device having a semiconductor chip mounted in a package, and a microstrip transmission line mounted in the package and connected to an input side and an output side of the semiconductor chip for impedance matching, the microstrip transmission line is formed. A dielectric substrate is embedded in a recess provided on the bottom surface of the package.
【0006】[0006]
【実施例】次に、本発明について、図面を参照して説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【0007】図1及び図2は本発明の一実施例を示す切
欠斜視図及び部分断面図である。FIGS. 1 and 2 are a cutaway perspective view and a partially sectional view showing an embodiment of the present invention.
【0008】図1及び図2に示すように、銅等の金属か
らなるパッケージ1の内側底面に凹部を設け、凹部上段
の水平面に凹部を取囲んで酸化シリコン膜又は窒化シリ
コン膜あるいは絶縁性樹脂等の絶縁膜6を設け、絶縁膜
6以外のパッケージ1の表面にNiめっき層2及びAu
めっき層3を順次積層して設ける。次に、凹部の底面に
AuSnソルダー5を用い上面にマイクロストリップ伝
送線路10及びオープンスタブパターン11を形成した
誘電体基板4を接着して固定し、誘電体基板4の上面と
凹部上段の水平面を一致させると共に誘電体基板4の側
面を凹部の側壁である接地面に近付ける。As shown in FIGS. 1 and 2, a recess is provided on the inner bottom surface of a package 1 made of metal such as copper, and a silicon oxide film, a silicon nitride film, or an insulating resin is formed around the recess on the horizontal surface above the recess. An insulating film 6 such as Ni plating layer 2 and Au
Plating layers 3 are sequentially laminated. Next, the dielectric substrate 4 on which the microstrip transmission line 10 and open stub pattern 11 are formed on the top surface is bonded and fixed using AuSn solder 5 to the bottom surface of the recess, and the top surface of the dielectric substrate 4 and the horizontal surface of the upper stage of the recess are bonded. At the same time, the side surfaces of the dielectric substrate 4 are brought close to the ground plane, which is the side wall of the recess.
【0009】ここで、AuSnソルダー5の這い上りは
絶縁膜6により阻止することができる。Here, creeping up of the AuSn solder 5 can be prevented by the insulating film 6.
【0010】次に、パッケージ1の内側底部にGaAs
FETチップ7及びチップコンデンサ8を搭載し、金属
細線9によりGaAsFETチップ7,チップコンデン
サ8,マイクロストリップ伝送線路10の相互間を接続
してインピーダンス整合回路を形成し、半導体装置を構
成する。Next, GaAs is applied to the inner bottom of the package 1.
A semiconductor device is constructed by mounting a FET chip 7 and a chip capacitor 8, and connecting the GaAs FET chip 7, chip capacitor 8, and microstrip transmission line 10 with each other using a thin metal wire 9 to form an impedance matching circuit.
【0011】[0011]
【発明の効果】以上説明したように本発明は、パッケー
ジの内側底面に設けた凹部内にマイクロストリップ伝送
線路を形成した誘電体基板を設けることにより、誘電体
基板の側面に接地面を近づけ、放射する電磁波を凹部側
壁で遮断する構造を形成し、誘電体基板を固定する際の
位置精度を向上させると共に自由空間への電磁波を、凹
部側壁により遮断し、凹部の互に対向する両側の側壁の
間、即ち誘電体基板内を、導波管モードで伝送させ、伝
送特性を向上させる。As explained above, the present invention provides a dielectric substrate on which a microstrip transmission line is formed in the recess provided on the inner bottom surface of the package, thereby bringing the ground plane close to the side surface of the dielectric substrate. A structure is formed in which radiated electromagnetic waves are blocked by the side walls of the recess, improving positional accuracy when fixing the dielectric substrate, and electromagnetic waves entering free space are blocked by the side walls of the recess. In other words, within the dielectric substrate, transmission is performed in a waveguide mode to improve transmission characteristics.
【0012】従って、入力側及び出力側の夫々に設けた
誘電体基板のストリップ伝送線路上から自由空間へ飛び
出る電磁波は抑制され、入出力回路相互のアイソレーシ
ョンを保障出来、10GHz以上の超高周波帯において
も、損失の少ない安定した50Ω内部整合が得られると
いう効果を有する。[0012] Therefore, the electromagnetic waves that jump out into free space from the strip transmission line of the dielectric substrate provided on the input side and the output side are suppressed, and mutual isolation between input and output circuits can be guaranteed, and ultra-high frequency bands of 10 GHz or more can be suppressed. Also, it has the effect that stable 50Ω internal matching with little loss can be obtained.
【図1】本発明の一実施例を示す切欠斜視図である。FIG. 1 is a cutaway perspective view showing one embodiment of the present invention.
【図2】図1の部分拡大断面図である。FIG. 2 is a partially enlarged sectional view of FIG. 1;
【図3】従来の半導体装置の一例を示す切欠斜視図であ
る。FIG. 3 is a cutaway perspective view showing an example of a conventional semiconductor device.
【図4】図3の部分拡大断面図である。FIG. 4 is a partially enlarged sectional view of FIG. 3;
1 パッケージ
2 Niめっき層
3 Auめっき層
4 誘電体基板
5 ソルダー
6 絶縁膜
7 GaAsFETチップ
8 チップコンデンサ
9 金属細線
10 マイクロストリップ伝送線路11
オープンスタブパターン1 Package 2 Ni plating layer 3 Au plating layer 4 Dielectric substrate 5 Solder 6 Insulating film 7 GaAsFET chip 8 Chip capacitor 9 Fine metal wire 10 Microstrip transmission line 11
open stub pattern
Claims (1)
と、前記パッケージ内に搭載して前記半導体チップの入
力側及び出力側に接続しインピーダンス整合を行うマイ
クロストリップ伝送線路を有する半導体装置において、
前記マイクロストリップ伝送線路を形成した誘電体基板
を前記パッケージの底面に設けた凹部内に埋込んで設け
たことを特徴とする半導体装置。1. A semiconductor device having a semiconductor chip mounted in a package, and a microstrip transmission line mounted in the package and connected to an input side and an output side of the semiconductor chip for impedance matching,
A semiconductor device characterized in that the dielectric substrate on which the microstrip transmission line is formed is embedded in a recess provided on the bottom surface of the package.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1781291A JPH04330804A (en) | 1991-02-08 | 1991-02-08 | Semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1781291A JPH04330804A (en) | 1991-02-08 | 1991-02-08 | Semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04330804A true JPH04330804A (en) | 1992-11-18 |
Family
ID=11954148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1781291A Pending JPH04330804A (en) | 1991-02-08 | 1991-02-08 | Semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04330804A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01151804A (en) * | 1987-12-09 | 1989-06-14 | Fujitsu Ltd | Packing structure for semiconductor chip |
JPH02113702A (en) * | 1988-10-24 | 1990-04-25 | Mitsubishi Electric Corp | Microstrip line |
-
1991
- 1991-02-08 JP JP1781291A patent/JPH04330804A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01151804A (en) * | 1987-12-09 | 1989-06-14 | Fujitsu Ltd | Packing structure for semiconductor chip |
JPH02113702A (en) * | 1988-10-24 | 1990-04-25 | Mitsubishi Electric Corp | Microstrip line |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19980407 |