JPH01151804A - Packing structure for semiconductor chip - Google Patents
Packing structure for semiconductor chipInfo
- Publication number
- JPH01151804A JPH01151804A JP62311582A JP31158287A JPH01151804A JP H01151804 A JPH01151804 A JP H01151804A JP 62311582 A JP62311582 A JP 62311582A JP 31158287 A JP31158287 A JP 31158287A JP H01151804 A JPH01151804 A JP H01151804A
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- semiconductor chip
- output signal
- input
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000012856 packing Methods 0.000 title 1
- 239000002184 metal Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 26
- 239000007769 metal material Substances 0.000 claims description 4
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 230000006866 deterioration Effects 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 abstract description 2
- 230000010355 oscillation Effects 0.000 abstract description 2
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 101100460844 Mus musculus Nr2f6 gene Proteins 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体チップ、特に高速信号回路を有する半導体チップ
の実装構造に関し、
入出力信号線間に、漏話が発生する恐れの少ない、半導
体チップの実装構造を提供することを目的とし、
同一直線上に人力信号線と出力信号線とを有し、金属基
板に装着された回路基板と、電極を対応する入出力信号
線に接続して、該入力信号線と該出力信号線との間に実
装する半導体チップとを有する半導体装置において、該
半導体チップの両側面まで、切込みのある回路基板、或
いは該半導体チップ部分で２分割された一対の回路基板
と、金属材よりなり、下側縁の中央に下方が開いた開口
を有する門形垂直板、及び該門形垂直板の上部に設けた
天井板よりなる側面視がＴ形の遮断体とを具備し、該開
口が該半導体チップを跨いだ状態で、該門形垂直板の下
端面を該金属基板に密着して、該遮断体を該金属基板に
固着した構成とする。[Detailed Description of the Invention] [Summary] To provide a mounting structure for a semiconductor chip, in particular a mounting structure for a semiconductor chip having a high-speed signal circuit, in which crosstalk is less likely to occur between input and output signal lines. For the purpose of In a semiconductor device having a semiconductor chip mounted between the signal line and the semiconductor chip, a circuit board with a notch extending to both sides of the semiconductor chip, or a pair of circuit boards divided into two by the semiconductor chip portion, and a metal material. and a gate-shaped vertical plate having an opening opening downward at the center of the lower edge, and a blocking body having a T-shape in side view and consisting of a ceiling plate provided on the upper part of the gate-shaped vertical plate, and the opening The lower end surface of the gate-shaped vertical plate is brought into close contact with the metal substrate in a state where the gate-shaped vertical plate straddles the semiconductor chip, and the shield is fixed to the metal substrate.
本発明は、半導体チップ、特に高速信号回路を有する半
導体チップの実装構造に関する。The present invention relates to a semiconductor chip, and particularly to a mounting structure for a semiconductor chip having a high-speed signal circuit.
近年の通信機器、計算機器等は高速化が要求さ高速信号
が授受されている。これに伴い、これらの機器に使用す
る高速信号回路を有する半導体装置には、入出力信号間
に漏話が惹起される傾向にある。In recent years, communication devices, computing devices, etc. are required to be faster, and high-speed signals are exchanged. Accordingly, crosstalk tends to occur between input and output signals in semiconductor devices having high-speed signal circuits used in these devices.
第４図は従来の半導体チップの実装構造を示す断面図で
あって、金属基板ＩＯは、両側に側壁門番を有する鋼等
よりなる金属ケースの底板である。FIG. 4 is a sectional view showing a conventional semiconductor chip mounting structure, in which the metal substrate IO is the bottom plate of a metal case made of steel or the like and having side wall gates on both sides.
２は、セラミックス等のような誘電体よりなる回路基板
であって、表面には、半導体チップＩを挾んで対向する
ように、同一直線上に細幅の入力信号線３と出力信号線
４とを形成しである。Reference numeral 2 denotes a circuit board made of a dielectric material such as ceramics, and has narrow input signal lines 3 and output signal lines 4 on the same straight line, facing each other with the semiconductor chip I in between. It is formed.
回路基板２の裏面の全面を、金等をメタライズして接地
導体５を設け、接地導体５を金属基板１０の表面に、導
電性樹脂接着剤、或いは半田等を用いて密着させ、回路
基板２を金属基板１０に装着している。The entire back surface of the circuit board 2 is metalized with gold or the like to provide a ground conductor 5, and the ground conductor 5 is closely attached to the surface of the metal board 10 using a conductive resin adhesive or solder. is attached to the metal substrate 10.
半導体チップ１の表面には、所望の回路、及び入出力信
号線に接続する電極を設けである。The surface of the semiconductor chip 1 is provided with electrodes connected to desired circuits and input/output signal lines.
そして、半導体チップ１の裏面に金等をメタライズし、
導電性樹脂接着剤手段、或いは半田接着手段等により、
半導体チップ１を回路基板２の表面に密着して固定して
いる。そして、それぞれの電極と対応する入力信号線３
．及び出力信号線４の端末とを、金線等のボンデングワ
イヤ６を用いてワイヤボンディングしている。Then, metallize gold or the like on the back surface of the semiconductor chip 1,
By conductive resin adhesive means, solder bonding means, etc.
A semiconductor chip 1 is tightly fixed to the surface of a circuit board 2. Then, the input signal line 3 corresponding to each electrode
．． and the terminal of the output signal line 4 are wire-bonded using a bonding wire 6 such as a gold wire.
入力信号線３．及び出力信号線４を、上述のようにスト
リップ内導体とすることにより、信号の高速化に対処し
ている。Input signal line 3. By using the output signal line 4 as an intra-strip conductor as described above, the signal speed can be increased.
しかしながら上記従来の半導体チップの実装構造は、第
４図に示すように入力信号線３と出力信号線４とが、空
中、或いは回路基板を介して容量性結合をし、その結果
、入出力信号線間での漏話が生じる。However, in the conventional semiconductor chip mounting structure described above, the input signal line 3 and the output signal line 4 are capacitively coupled in the air or through the circuit board, as shown in FIG. Crosstalk occurs between lines.
信号が高速化するほど、この容量性結合による漏話が太
き（なり、入出力波形が劣化したり、或いはチップ回路
が発振する恐れがあった。As the signal speed increases, the crosstalk caused by this capacitive coupling becomes thicker, leading to the risk of deterioration of input/output waveforms or oscillation of the chip circuit.
本発明はこのような点に鑑みて創作されたもので、入出
力信号線間に漏話が発生する恐れの少ない、半導体チッ
プの実装構造を提供することを目的としている。The present invention was created in view of these points, and an object of the present invention is to provide a semiconductor chip mounting structure in which there is less risk of crosstalk occurring between input and output signal lines.
上記の問題点を解決するために本発明は、第１図、第２
図に例示したように、同一直線上にストリップ線路より
なる、入力信号線３と出力信号線４とを有し、金属基板
ｌＯに装着された回路基板２と、電極を対応するそれぞ
れの入力信号ｖｉ ３ 、及び出力信号線４に接続して
、入力信号線３と出力信号ｖＡ４の間に実装する半導体
チップとよりなる半導体装置において、回路基板は、角
板状で半導体チップ１の両側面まで、切込みを設けた回
路基板２、或いは半導体チップ１部分で２分割した一対
の回路基板２−１．２−２とする。In order to solve the above problems, the present invention has been developed as shown in FIGS.
As illustrated in the figure, the circuit board 2 has an input signal line 3 and an output signal line 4 made of strip lines on the same straight line, and is connected to a circuit board 2 mounted on a metal substrate 1O, and the electrodes are connected to the corresponding input signal lines. vi 3 and a semiconductor chip connected to the output signal line 4 and mounted between the input signal line 3 and the output signal vA4, the circuit board has a rectangular plate shape and extends to both sides of the semiconductor chip 1. , a circuit board 2 provided with a notch, or a pair of circuit boards 2-1, 2-2 divided into two by a semiconductor chip 1 portion.
金属材よりなり、下側縁の中央に下方が開いた開口２２
を有する門形垂直板２１と、門形垂直板２１の上部に設
けた天井板２３とよりなる、側面視がＴ形の遮断体２０
を用いて、開口２２が半導体チップｌを跨ぐように遮断
体２０をあてがい、門形垂直板２１の下端面を金属基板
１０に密着して、遮断体２０を金属基ＦｉｌＯに固着し
た構成とする。An opening 22 made of metal material and opened downward at the center of the lower edge
A blocking body 20 having a T-shape in side view and consisting of a gate-shaped vertical plate 21 having
The shielding body 20 is applied so that the opening 22 straddles the semiconductor chip l, the lower end surface of the gate-shaped vertical plate 21 is brought into close contact with the metal substrate 10, and the shielding body 20 is fixed to the metal base FILO. .
上記本発明の手段によれば、半導体装置の空間は、金属
基板１０に接地した遮断体２０により、入力信号線３側
と出力信号線４側に分離されている。According to the above means of the present invention, the space of the semiconductor device is separated into the input signal line 3 side and the output signal line 4 side by the interrupter 20 grounded to the metal substrate 10.
また、回路基板の下部には、入力信号線３側と出力信号
線４側に共通する接地された金属基板１０がある。Further, at the bottom of the circuit board, there is a grounded metal substrate 10 that is common to the input signal line 3 side and the output signal line 4 side.
したがって、高速信号が伝送することにより、入力信号
線３．及び出力信号線４のそれぞれに発生する電界は、
この遮断体２０に吸収され相手側に拡散しない。Therefore, by transmitting high-speed signals, the input signal line 3. The electric field generated in each of the output signal line 4 and the output signal line 4 is
It is absorbed by this blocking body 20 and does not spread to the other party.
即ち、入力信号線３と出力信号線４とが容量性結合する
恐れが少なくて、入出力信号線間での漏話がない。よっ
て、入出力波形が劣化したり、或いはチップ回路が発振
する恐れがない。That is, there is little risk of capacitive coupling between the input signal line 3 and the output signal line 4, and there is no crosstalk between the input and output signal lines. Therefore, there is no risk that input/output waveforms will deteriorate or that the chip circuit will oscillate.
以下図を参照しながら、本発明を具体的に説明する。な
お、全図を通じて同一符号は同一対象物を示す。The present invention will be specifically described below with reference to the drawings. Note that the same reference numerals indicate the same objects throughout the figures.
第１図は本発明の一実施例の構成図で、（ａｌは斜視図
、中）は断面図、第２図は本発明の他の実施例の断面図
、第３図は本発明のさらにその他の実施例の断面図であ
る。Fig. 1 is a block diagram of one embodiment of the present invention, (al is a perspective view, middle) is a sectional view, Fig. 2 is a sectional view of another embodiment of the present invention, and Fig. 3 is a further embodiment of the present invention. FIG. 7 is a sectional view of another embodiment.
第１図において、セラミックス等のような誘電体よりな
る矩形状の回路基板２の表面の中心部に、裏面のメタラ
イズ面を導電性樹脂接着剤手段、或いは半田接着手段等
により接着して、半導体チップ１をマウントしである。In FIG. 1, a metallized surface on the back side is bonded to the center of the front surface of a rectangular circuit board 2 made of a dielectric material such as ceramics using a conductive resin adhesive means or a solder bonding means to form a semiconductor. Mount chip 1.
回路基板２には、半導体チップ１を挟んで対向するよう
に、同一直線上に細幅の入力信号線３と出力信号線４と
を形成し、半導体チップ１のそれぞれの電極と、対応す
る入力信号線３．及び出力信号線４の端末のパッドとを
、金線等のボンデングワイヤ６を用いて、ワイヤボンデ
ィングしである。On the circuit board 2, narrow input signal lines 3 and output signal lines 4 are formed on the same straight line so as to face each other with the semiconductor chip 1 in between. Signal line 3. and the terminal pad of the output signal line 4 are wire-bonded using a bonding wire 6 such as a gold wire.
また、回路基板２には入力信号線３（出力信号線４にも
並行）に並行する両側縁から半導体チップ１の両側まで
、直角に切込みを設けである。この切込の幅には特別の
制限はないが、半導体チップｌの長さ（半導体チップの
入出力信号線方向の側総長）に近いことが望ましい。Furthermore, cuts are provided in the circuit board 2 at right angles from both side edges parallel to the input signal line 3 (also parallel to the output signal line 4) to both sides of the semiconductor chip 1. There is no particular limit to the width of this cut, but it is desirable that it be close to the length of the semiconductor chip l (the total side length of the semiconductor chip in the input/output signal line direction).
金属基板１０は、両側に側壁１０ａを有する鋼等よりな
る金属ケースの底板である。金属基板ＩＯの上面に、上
述の回路基板２の裏面の接地導体５を密着させて、回路
基板２を金属基板１０に固着しである。The metal substrate 10 is the bottom plate of a metal case made of steel or the like and has side walls 10a on both sides. The circuit board 2 is fixed to the metal substrate 10 by bringing the above-described ground conductor 5 on the back surface of the circuit board 2 into close contact with the upper surface of the metal substrate IO.
２０は、金属材（例えば鋼）よりなり、下側縁の中央に
下方が開いた開口２２を有する門形垂直板２１と、門形
垂直板２１の上部に設けた天井板２３とよりなる、側面
視がＴ形の遮断体である。20 is made of a metal material (for example, steel), and consists of a gate-shaped vertical plate 21 having an opening 22 opening downward at the center of the lower edge, and a ceiling plate 23 provided on the top of the gate-shaped vertical plate 21. The blocker is T-shaped when viewed from the side.
開口２２の高さは、金属基板１０の表面と半導体チップ
１の表面との距離より、所望に大きく、その幅は半導体
チップ１の幅よりもわずかに大きい。The height of the opening 22 is desirably greater than the distance between the surface of the metal substrate 10 and the surface of the semiconductor chip 1, and its width is slightly greater than the width of the semiconductor chip 1.
開口２２が半導体チップ１を跨ぐように、門形垂直板２
１を回路基板２の切込みに挿入し、門形垂直板２１の下
端面を金属基板１０に、導電性樹脂接着剤による接着、
或いは半田付は接着等して、遮断体２０を金属基板１０
に固着しである。The gate-shaped vertical plate 2 is arranged so that the opening 22 straddles the semiconductor chip 1.
1 into the notch of the circuit board 2, and bond the lower end surface of the gate-shaped vertical board 21 to the metal board 10 with a conductive resin adhesive.
Alternatively, the shield 20 can be attached to the metal substrate 10 by soldering or adhesion.
It sticks to.
上述のように半導体チップ１の上方から左右の両側にか
けて、金属基板１０に接地した遮断体２０を設けである
ので、半導体装置の空間は、入力信号線３側と出力信号
線４側とに、電磁気的に分離されている。したがって、
入出力信号線と出力信号線４とが、空間を介して容量性
結合する恐れが少ない。As described above, since the interrupter 20 grounded to the metal substrate 10 is provided from above the semiconductor chip 1 to both left and right sides, the space of the semiconductor device is divided into the input signal line 3 side and the output signal line 4 side. Electromagnetically separated. therefore,
There is little risk of capacitive coupling between the input/output signal line and the output signal line 4 via space.
なお、門形垂直板２１を両側を左右に延伸して、その端
面をそれぞれ側壁１０ａに密着させれば、空間を介して
の容量性結合を、はぼ完全に消滅させることができる。Incidentally, if both sides of the gate-shaped vertical plate 21 are extended to the left and right and the end faces thereof are brought into close contact with the side walls 10a, the capacitive coupling through the space can be almost completely eliminated.
第２図において、半導体チップｌは、金属基板１０の表
面に直接マウントしである。In FIG. 2, a semiconductor chip 1 is mounted directly on the surface of a metal substrate 10. In FIG.
そして第１図に示す回路基板２を、切込部分で入力信号
線３を有する回路基板２−１と、出力信号線４を有する
回路基板２−２とに分割して、それぞれの回路基板２−
１．２−２を、半導体チップ１を挟んで対向させた状態
で、金属基板１０の表面に固着し、半導体チップ１のそ
れぞれの電極を、対応する入力信号＆’７１３ 、出力
信号線４の端末のパッドに、ボンディングワイヤ６を介
して接続しである。Then, the circuit board 2 shown in FIG. −
1.2-2 are fixed to the surface of the metal substrate 10 while facing each other with the semiconductor chip 1 in between, and each electrode of the semiconductor chip 1 is connected to the corresponding input signal &'713 and output signal line 4. It is connected to the pad of the terminal via a bonding wire 6.
そして、開口２２が半導体チップ１を跨ぐように、門形
垂直板２１を回路基板２−１と２−２とが形成する間隙
に挿入し、門形垂直板２１の下端面を金属基板１０に、
導電性樹脂接着剤による接着、或いは半田付は接着等し
て、遮断体２０を金属基板１０に固着しである。Then, the gate-shaped vertical plate 21 is inserted into the gap formed between the circuit boards 2-1 and 2-2 so that the opening 22 straddles the semiconductor chip 1, and the lower end surface of the gate-shaped vertical plate 21 is attached to the metal substrate 10. ,
The blocking body 20 is fixed to the metal substrate 10 by adhesion using a conductive resin adhesive or by soldering.
第２図の実施例は上述のように、半導体チップ１の裏面
を、直接金属基板ＩＯに接地させ、容量性結合を惹起す
る誘電体を、半導体チップ１の下部から排除しである。As described above, in the embodiment shown in FIG. 2, the back surface of the semiconductor chip 1 is directly grounded to the metal substrate IO, and the dielectric material that causes capacitive coupling is eliminated from the bottom of the semiconductor chip 1.
したがって、入力信号線３と出力信号線４とが、容量性
結合をする恐れがまったくない。Therefore, there is no risk of capacitive coupling between the input signal line 3 and the output signal line 4.
第３図の実施例は、ワイヤボンディング実装法でなく、
半導体チップをフェイスダウンにし、フリップチップボ
ンディング実装したものである。The embodiment shown in FIG. 3 is not a wire bonding mounting method.
The semiconductor chip is placed face down and mounted using flip chip bonding.
即ち、半導体チップ１の電極に予め半田バンプ７を形成
しておき、一方では、回路基板２の入力信号線３及び出
力信号線４のそれぞれの端末に予備半田をしておく。そ
して半導体チップ１を逆さにして、それぞれの半田バン
プ７を入力信号線３゜及び出力信号線４の端末のパッド
に半田リフローして接着しである。That is, solder bumps 7 are formed in advance on the electrodes of the semiconductor chip 1, and on the other hand, preliminary solder is applied to the respective terminals of the input signal line 3 and the output signal line 4 of the circuit board 2. Then, the semiconductor chip 1 is turned upside down, and the respective solder bumps 7 are bonded to the terminal pads of the input signal line 3° and the output signal line 4 by reflow soldering.
回路基板２には入力信号線３ （出力信号線４にも並行
）に並行する両側縁から半導体チップ１の両側まで、直
角に切込みを設けである。Cuts are provided in the circuit board 2 at right angles from both side edges parallel to the input signal line 3 (also parallel to the output signal line 4) to both sides of the semiconductor chip 1.
そして、開口２２が半導体チップ１を跨ぐように、門形
垂直板２１を回路基板２の切込みに挿入し、門形垂直板
２１の下端面を金属基板１０に、導電性樹脂接着剤によ
る接着、或いは半田付は接着等して、遮断体２０を金属
基板１０に固着しである。Then, the gate-shaped vertical plate 21 is inserted into the notch of the circuit board 2 so that the opening 22 straddles the semiconductor chip 1, and the lower end surface of the gate-shaped vertical plate 21 is bonded to the metal substrate 10 using a conductive resin adhesive. Alternatively, the shielding body 20 may be fixed to the metal substrate 10 by soldering or the like by adhesion or the like.
第３図に示す実装構造は、容量性結合の排除の効果の点
においては、第１図に示したものとほぼ同じであるが、
第１図、第２図に示したものよりは、半導体チップのマ
ウントが容易で、且つ半導体装置の高周波特性が優れて
いるという利点がある。The mounting structure shown in FIG. 3 is almost the same as the one shown in FIG. 1 in terms of the effect of eliminating capacitive coupling.
Compared to the configurations shown in FIGS. 1 and 2, this configuration has the advantage that mounting of the semiconductor chip is easier and the high frequency characteristics of the semiconductor device are excellent.
以上説明したように本発明は、遮断体を設けて、入出力
信号線間が容量性結合するのを阻止した半導体チップの
実装構造であって、入出力信号線間実用りで優れた効果
がある。As explained above, the present invention is a semiconductor chip mounting structure in which a interrupter is provided to prevent capacitive coupling between input and output signal lines, and the present invention has excellent practical effects between input and output signal lines. be.
第１図は本発明の一実施例の構成図で、（ａｌは斜視図
、
（ｂｌは断面図、
第２図は本発明の他の実施例の断面図、第３図は本発明
のさらにその他の実施例の断面図、
第４図は従来例の断面図である。
図において、
１は半導体チップ、 ２．２−１．２−２は回路基板、
３は入力信号線、 ４は出力信号線、５は接地導体、
６はボンディングワイヤ、７は？Ｖ田ハンプ、
ＩＯは金属基板、２０は遮断体、 ２１は門
形垂直板、２２は開口、
２３は天井板をそれぞれ示す。
オＪご１耳／）Ｉ’ｅ／ｌｒｍイ列の断置目耳茅２ 阿FIG. 1 is a configuration diagram of one embodiment of the present invention, (al is a perspective view, (bl is a sectional view, FIG. 2 is a sectional view of another embodiment of the present invention, and FIG. 3 is a further embodiment of the present invention. 4 is a sectional view of a conventional example. In the figure, 1 is a semiconductor chip, 2.2-1.2-2 is a circuit board,
3 is the input signal line, 4 is the output signal line, 5 is the ground conductor,
6 is bonding wire, 7 is? Vta hump,
IO is a metal substrate, 20 is a barrier, 21 is a gate-shaped vertical plate, 22 is an opening, and 23 is a ceiling plate. O J Go 1 ear/) I'e/lrm A row's incision eye ear 2 A
Claims (1)
板に装着された回路基板と、電極を対応する入出力信号
線に接続して、該入力信号線と該出力信号線との間に実
装した半導体チップとを有する半導体装置において、 該半導体チップ（１）の両側面まで切込みのある回路基
板（２）、或いは該半導体チップ（１）部分で２分割さ
れた一対の回路基板（２−１，２−２）と、金属材より
なり、下側縁の中央に下方が開いた開口（２２）を有す
る門形垂直板（２１）、及び該門形垂直板（２１）の上
部に設けた天井板（２３）よりなる側面視がＴ形の遮断
体（２０）とを具備し、 該開口（２２）が該半導体チップ（１）を跨いだ状態で
、該門形垂直板（２１）の下端面が該金属基板（１０）
に密着して、該遮断体（２０）が該金属基板（１０）に
固着されたことを特徴とする半導体チップの実装構造。[Claims] A circuit board having an input signal line and an output signal line on the same straight line and mounted on a metal substrate, and an electrode connected to the corresponding input/output signal line, In a semiconductor device having a semiconductor chip mounted between the output signal line and the semiconductor chip (1), the circuit board (2) has a notch extending to both sides of the semiconductor chip (1), or the circuit board is divided into two by the semiconductor chip (1). a pair of circuit boards (2-1, 2-2), a gate-shaped vertical plate (21) made of a metal material and having an opening (22) opened downward at the center of the lower edge; A ceiling plate (23) provided on the top of the plate (21) is provided with a blocker (20) that is T-shaped in side view, and the opening (22) straddles the semiconductor chip (1). The lower end surface of the gate-shaped vertical plate (21) is connected to the metal substrate (10).
A semiconductor chip mounting structure characterized in that the shield (20) is fixed to the metal substrate (10) in close contact with the metal substrate (10).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62311582A JPH01151804A (en) | 1987-12-09 | 1987-12-09 | Packing structure for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62311582A JPH01151804A (en) | 1987-12-09 | 1987-12-09 | Packing structure for semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01151804A true JPH01151804A (en) | 1989-06-14 |
Family
ID=18018973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62311582A Pending JPH01151804A (en) | 1987-12-09 | 1987-12-09 | Packing structure for semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01151804A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04274633A (en) * | 1990-12-03 | 1992-09-30 | American Teleph & Telegr Co <Att> | Synchronization apparatus |
| JPH04330804A (en) * | 1991-02-08 | 1992-11-18 | Nec Yamagata Ltd | Semiconductor |
-
1987
- 1987-12-09 JP JP62311582A patent/JPH01151804A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04274633A (en) * | 1990-12-03 | 1992-09-30 | American Teleph & Telegr Co <Att> | Synchronization apparatus |
| JPH04330804A (en) * | 1991-02-08 | 1992-11-18 | Nec Yamagata Ltd | Semiconductor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6114635A (en) | Chip-scale electronic component package | |
| US4259684A (en) | Packages for microwave integrated circuits | |
| KR900001273B1 (en) | Semiconductor integrated circuit device | |
| JPH0321089B2 (en) | ||
| US6204448B1 (en) | High frequency microwave packaging having a dielectric gap | |
| JPH07114323B2 (en) | Microwave integrated circuit package | |
| JPH0425036A (en) | Microwave semiconductor device | |
| US6046501A (en) | RF-driven semiconductor device | |
| JPH03255657A (en) | Hybrid integrated circuit device | |
| JPH01151804A (en) | Packing structure for semiconductor chip | |
| JPH10224175A (en) | Elastic surface wave device | |
| EP0001890B1 (en) | Improvements in or relating to microwave integrated circuit packages | |
| JPH11330298A (en) | Package provided with signal terminal and electronic device using the package | |
| JP2511136Y2 (en) | Metal package for electronic parts | |
| KR100420792B1 (en) | Power Microwave Hybrid Integrated Circuits | |
| RU2183367C2 (en) | Microwave hybrid integrated circuit | |
| JP2894616B2 (en) | Surface acoustic wave device and equipment using the same | |
| JPH0623032Y2 (en) | Circuit board mounting structure | |
| JPH0719148Y2 (en) | Microwave circuit package | |
| JP2541336B2 (en) | Method of connecting integrated circuit device | |
| JPH07105463B2 (en) | Package for ultra high frequency devices | |
| JP2001118981A (en) | Multi chip module | |
| JPH0342859A (en) | Package for high-speed device | |
| JPS5844732A (en) | Semiconductor device | |
| JPH02107001A (en) | High frequency circuit device |