JPH04328911A - Adaptive digital filter - Google Patents

Abstract

PURPOSE:To attain the simplified hardware by devising the digital filter such that required and minimum number of product sum arithmetic operation circuits is enough when a partial tap within a limited range is used for product sum arithmetic operation even when the digital filter for ghost canceller has lots of taps. CONSTITUTION:A multi-port memory 1 outputs plural data blocks (e.g. each comprising 8 sample data) simultaneously within one sample period of an input television signal. The data block is fed respectively to product sum arithmetic operation circuits MA-1-MA-8 of a product sum arithmetic section 3 through shift registers SR-R1-SR-R8. Coefficients to 640 taps in total are grouped for 8-taps each and 8 groups at maximum whose coefficients are not zero are set. Data read from the multi-port memory 1 and the group having coefficients of non-zero are calculated respectively by the product sum arithmetic operation circuits MA-1-MA-8 and an output data is formed by adding outputs of all the product sum arithmetic operation circuits.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive digital filter used, for example, in a ghost canceller.

0002

2. Description of the Related Art A ghost canceller to which the present invention can be applied will first be described. Radio waves transmitted from a broadcasting station are broadcast as images to a television set in a home or the like via a receiver, for example, an external antenna. If there is an obstacle between the broadcasting station and the receiver, such as a tall building or mountain, the radio waves emitted from the broadcasting station will be directly received by the external antenna (hereinafter referred to as direct waves), and the radio waves emitted from the broadcasting station will be directly received by the external antenna (hereinafter referred to as direct waves) and are received after being reflected by obstacles (hereinafter referred to as indirect waves). In such a case, an original image is projected on the screen by the direct wave, and a ghost (post-ghost) is generated by the indirect wave after the original image (on the right side on the screen). Also,
If the distance between the broadcasting station and the receiver is close, the transmitted radio waves will be received by the antenna terminal of the television main body before being received by the external antenna. For this reason, the radio waves received by the external antenna broadcast an original image on the screen, and the radio waves received by the antenna terminal appear as a ghost in front of this original image (on the left side on the screen) (front ghost). .

A ghost canceller has been proposed as a device for removing ghosts as described above. In this ghost canceller, a tuner selects a desired radio wave from among radio waves input from an antenna, and supplies the selected radio wave to an A/D converter. The output signal of the A/D converter is supplied to a digital filter and a ghost analysis section. The ghost analysis section determines filter coefficients necessary to realize characteristics that reduce ghosts, and provides these filter coefficients to the digital filter. The received signal passes through this digital filter to reduce ghost components, and is further output via the D/A converter.

By the way, in general, ghost cancellers are
A digital filter with a very long impulse response is required, and its construction, in principle, requires an IIR type digital filter, ie, a digital filter with feedback. However, in reality, an FIR type digital filter must be used for close-in ghosts due to practical constraints. In addition, FI with a long impulse response can be used even for ghosts that are not close to each other.
An IIR type digital filter is constructed using an R type digital filter (transversal filter). For this reason, the arithmetic circuit is practically composed of an FIR type digital filter with a long impulse response.

A digital filter, for example, an FIR type digital filter (transversal filter) is shown in FIG.
As shown in the block diagram of FIG.
0A to 100E, multipliers 101A to 101E, adder 1
02 and a filter coefficient storage section 103. Filter coefficient storage section 103 stores filter coefficients supplied to each multiplier 101A to 101E. In the case of a ghost canceller, by using a reference waveform (referred to as a GCR waveform) in the received signal, a coefficient calculation unit (not shown) calculates appropriate coefficients according to temporal changes in ghosts. , this coefficient is stored in the storage unit 103.

Furthermore, the registers 100A to 100E and the filter coefficient storage section 103 have the same function as a memory in principle. A digital filter that handles acoustic signals uses a configuration that includes a set of multipliers and adders and performs time-sharing processing using a program. However, the data rate of digitized television video signals is fast, and one data period is almost the same as the calculation speed of a multiplier or adder, so such time-sharing processing is not possible, and digital filters that handle television video signals cannot perform such time-sharing processing. , registers 100A to 100E are used as shown in FIG. register 1
With 00A to 100E, delay data and coefficients are simultaneously applied to each multiplier for each input pixel (sample). Furthermore, ordinary memories use registers because they can only handle one piece of data at a time.

By the way, when using the direct wave as a reference, -1
Radio waves received in the range of about 40 μs appear on the screen as ghosts. This time is equivalent to approximately 600 pixels of a digitized television video signal. In order to realize such a long impulse response, as shown in FIG.
00 taps (600=40000ns/70ns:70
ns is a typical sampling period of a digital television signal) A connected digital filter 110 is used as a ghost canceller.

FIG. 10 is a block diagram showing an example of a unit product-sum operation circuit. In FIG. 10, a is the video data from the product-sum calculation circuit in the previous stage, b is the product-sum calculation result in the previous stage, and c is a coefficient. Data a is outputted as output data d via a register 104 indicated by RA and a register 106 indicated by RB. The output of the register 104 and the coefficient c via the register 107 indicated by C are supplied to the multiplier 108, the multiplication result is added to data b in the adder 105, and the addition result is output data via the register 104 indicated by RC. It is assumed that e. Register 104 is a pipeline register when adders 105 are connected in cascade. A register 106 indicated by RB is a register for compensating for the delay of the register 104 between the input terminal a and the output terminal d. Further, FIG. 11 is a block diagram of a unit product-sum calculation circuit constituting a transposed type digital filter having the same function as the circuit shown in FIG.

[0009]

Incidentally, ghosts that actually appear on the screen occur in a range of about 40 microseconds, but they occur not in all of that time, but in part. Therefore, although the ghost canceller is equipped with a 600-tap digital filter 110, only some of the taps are multiplied by a non-zero coefficient, as exemplarily shown in the shaded area in FIG. There are many product-sum calculation circuits playing around with just that. Of course, if the ghost is constant, then Figure 1
Although it is sufficient to prepare a computing unit only for the shaded area in 2, the ghost does not occur at a specific position on the screen due to the influence of the position of the receiving antenna, surrounding buildings, etc. For this reason, 6
A digital filter with as many as 00 taps is required. A high-speed multiplier for video signals included in a digital filter has a large number of gates and occupies a large area on an LSI chip, leading to an increase in cost in the future.

[0010] As a solution to this problem, for example, the following can be considered. Assuming that the input data rate is sufficiently slower than the processing speed of the digital filter, one memory 111 is provided to store the input data, as shown in FIG.
Replaces 0H. In FIG. 13, W1 is a terminal into which input data is written, R1 to Rn are terminals from which read data is taken out, the write address is controlled by address Aw, and the read address is controlled by addresses A1 to An. By doing this, for each data input, necessary addresses are randomly accessed in order from A1 to An, and the readout output from the memory 111 is given to the product-sum calculation unit to obtain one output. Can be done.

However, as described above, the high data rate of digitized television video signals requires a memory 111 with a wide bandwidth as shown in FIG. That is, a large number of data accesses must be performed simultaneously during one cycle. Although it is possible to realize a certain number of ports (number of simultaneous accesses) as such a multi-port memory, it is not possible to achieve the random access required for the digital filter for the ghost canceller mentioned above. , is impossible.

[0012] Therefore, an object of the present invention is to provide an adaptive digital filter that can perform only necessary tap calculations and that can be simplified to the minimum necessary hardware configuration.

[0013]

[Means for Solving the Problems] The present invention has one serial access write port SR-W and a plurality of serial access read ports SR-R1 to SR-R8. A multi-port memory (1) in which an input data string is written in blocks each consisting of n pieces of data, and a plurality of arbitrary blocks are read out from read ports SR-R1 to SR-R8 for each write, and a read Port SR-R1 to SR-R
Product-sum calculation circuits MA-1 to MA- connected to 8, respectively.
8, and means (2) for generating a read block address of the multiport memory (1) and coefficients to be applied to the product-sum calculation circuits MA-1 to MA-8.

[0014]

[Operation] In the multiport memory 1, while one data block is written, a plurality of data blocks can be read from a designated block address. Therefore, for example, it is sufficient to be able to access the data blocks necessary for multiplication with non-zero coefficients required for ghost cancellation, and to have this limited number of product-sum calculation circuits, which further reduces the hardware scale. Can be made smaller.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. This embodiment is a configuration that can be applied to a ghost canceller. It is assumed that the digital filter for the ghost canceller has 640 taps. In addition, the input data is 14.4MHz (approximately 70MHz).
With a sampling frequency of ns period), one sample is 8
This is a television video signal digitized into bits.

In FIG. 1, 1 surrounded by a broken line indicates a multiport memory. The multi-port memory 1 includes a memory element array MEM, a shift register SR-W forming a serial input port, and eight shift registers SR-R1 to SR-R8 forming a serial output port. The multi-port memory is configured as follows. In other words, eight serial access ports are provided to handle data in data blocks of a certain size, and serial access is performed within each data block, but random access is performed for each data block, creating a pseudo multi-port system as a whole. has been realized. Figure 1
Although the width L2 of the shift registers SR-R1 to SR-R8 is written to be longer than the width L1 of the memory element array MEM, in reality, L1>L2. Also, in Figure 1,
Coefficient determination and a coefficient storage unit for canceling ghosts are the same as those in the prior art except for grouping, which will be described later, and therefore illustration thereof is omitted.

Shift register SR-W, SR-R1 to S
Both R-R8 shift data from left to right. Shift registers SR-R1 to SR-R8 have a function of shifting data from top to bottom. In this embodiment, eight shift registers SR-R1 to S
Since R-R8 is provided, data corresponding to (8×8=64) taps can be obtained from the multiport memory 1. This means that out of the assumed 640 taps, if the maximum value of taps with non-zero coefficients is 64 taps, which is 1/10 of the maximum value, ghosts can be sufficiently suppressed. This setting of 1/10 is an explanatory value and is not an actual value. In other words, the tap portion to be calculated is 4
Approximately what fraction of 0 microseconds should be set is set, and corresponding product-sum calculation circuits are provided, but the settings are made empirically through experiments. However, the setting is not simply determined based on the probability that the coefficient is non-zero, but is considered to be the minimum number of taps necessary to sufficiently suppress noticeable ghosts.

Further, reference numeral 2 denotes an address generator that generates an address for the memory element array MEM. This address is assigned to each horizontal column of the memory element array MEM, and this horizontal column is defined as a data block. In other words, one address represents the data block number. In this example, the data block size is 8 samples. Since the input data supplied to the shift register SR-W is a television video signal in which one sample is digitized into 8 bits, this word length (8
The multi-port memories 1 are arranged for the number of bits). That is, 8 multi-port memories are provided, each forming a bit plane, and the memory element array MEM of each bit plane has 8 elements horizontally and 80 elements vertically (640
/8) are lined up.

Reference numeral 3 surrounded by a broken line indicates a product-sum operation section that performs an FIR filter operation. The sum-of-products calculation unit 3 inputs the shift register SR- of the multi-port memory 1 to each
It includes product-sum arithmetic circuits MA-1 to MA-8 to which serial output data of R1 to SR-R8 are supplied, and an adder SUM that adds the outputs of these product-sum arithmetic circuits MA-1 to MA-8. I'm here. The product-sum calculation circuits MA-1 to MA-8 have a relatively small number of taps equal to the data block size (8 samples). In other words, each of the product-sum calculation circuits MA-1 to MA-8 constitutes an 8-tap FIR filter.

As the product-sum calculation circuits MA-1 to MA-8, those known in the prior art shown in FIG. 10 or 11 may be used. As an alternative, a parallel arithmetic circuit disclosed in Japanese Patent Application No. 1-337319 previously proposed by the present applicant or a filter arithmetic circuit described in Japanese Patent Application No. 2-122654 may be used. Good too. Serial data is output from this adder SUM. As the adder SUM, a tree adder as shown in FIG. 2, a column adder as shown in FIG. 3, etc. can be used. Note that, for example, a pipeline register for high-speed operation may be provided at this position as indicated by the triangular mark in FIGS. 2 and 3.

As described above, bit planes corresponding to each bit of one sample of the input television video signal may be configured, but instead of configuring each bit plane, 8 bit planes may be configured.
Bit-parallel processing can also be performed. That is, the memory element array MEM has 64 elements arranged horizontally and 80 elements arranged vertically. FIG. 4 shows eight elements of such a configuration cut out vertically.

As shown in FIG. 4, shift register SR-W constituting the write port and shift registers SR-R1 to SR-R8 constituting the read port shift 8-bit parallel data and also shift 8-stage data. have The input 8-bit data is transferred to shift register SR.
-W, and bit-parallelly leads to 6 of 8 samples.
Four bits are simultaneously written to the memory element array MEM. The destination of this write depends on the write address from the address generator 2, that is, the designation of which stage of the memory element array MEM.

Shift register SR-R8 shown in FIG.
In SR-R7 and SR-R7, the square blocks represent latches, and the round blocks are horizontally extending bus switches as shown in FIG. Shift register SR-R1
~ Shifting data from top to bottom in the vertical direction of SR-R8 is made possible by connecting latches indicated by squares. On the other hand, shifting from left to right in the lateral direction is achieved by turning on the switches indicated by circles one by one from the right end to the left end.

In this embodiment, one data block is made up of eight samples, so the coefficients of the digital filter must be grouped every eight taps. In this embodiment, filter coefficients for ghost cancellation need to be determined as follows.

First, a non-zero portion of the coefficients of the FIR filter that cancels the ghost to be suppressed is found. Next, it is determined how many of the 8-tap divisions among the 640 taps these non-zero taps exist. If it is 8 groups or less, it is fine.
Otherwise, eight groups are selected preferentially according to a certain rule. For example, an isolated non-zero tap whose surrounding taps are zero may be removed, eight groups may be selected from those with the greatest ghost removal effect, or eight groups may be selected from those that are earlier in time. Such grouping of coefficients is performed by a coefficient calculation unit that determines coefficients.

FIG. 6 shows a series of filter coefficients grouped every 8 taps, and the shaded portions represent non-zero coefficients determined as described above. The numbers preceded by * in FIG. 6 are group numbers of non-zero coefficients grouped every 8 taps from the temporally earlier part of the impulse response. Note that the side indicated by *0 is the earliest in terms of time, but since there is also a front ghost, the end in FIG. 6 is not the time of the actual signal.

FIG. 7 represents the addressing of the memory element array MEM. Memory element array ME as shown in FIG.
In M, an address is determined for each horizontal row, as shown by the # symbol in FIG. One of these addresses corresponds to one data block (8 samples) of the input signal.

Next, the operation of this embodiment will be explained. The input signal passes through the shift register SR-W and is written to the memory element array MEM. This writing cycle is
This is 560 ns, which is 1/8 of the input data rate (about 70 ns). Further, the write address is sequentially incremented in ascending order, returns to #0 after #79, and repeats this process. Here, the address of the input data block just written into the memory element array MEM is assumed to be #P.

In order to obtain the output of the FIR type filter with non-zero taps shown as the shaded area in FIG. 6, the following [Equation 1] is used.
filter operations are required.

The first term in [Equation 1] is (#P)×(*
0) means the newest data (
rightmost data) and the product of the first coefficient of coefficient *0 and #P
The product of the second newest data (second data from the right) of the data block and the second coefficient of coefficient *0 and #P
The product of the third newest data (third data from the right) of the data block and the third coefficient of coefficient *0 and...
... ... It means the sum of the oldest data (leftmost data) of the data block of #P and the product of the last coefficient of coefficient *0. The same applies to other terms such as (#P-1)×(*1).

This calculation is performed by applying data from the memory element array MEM to the product-sum calculation circuits MA-1 to MA-8 of the product-sum calculation unit 3 through shift registers SR-R1 to SR-R8. First, the block address #P is given to the memory element array MEM from the address generator 2, and the block data #P is transferred from the memory element array MEM to the shift register SR-R8. Next, the block address of #P-1 is given to the memory element array MEM from the address generator 2, the block data of #P that was in SR-R8 is shifted to SR-R7, and the block address of #P-1 is given from the memory element array MEM. Block data of P-1 is moved to SR-R8. Next, memory element array M
The block address of #P-2 is sent to EM by address generator 2.
, the block data of #P in SR-R7 is shifted to SR-R6, and the block data of #P in SR-R8 is shifted to SR-R6.
The block data of P-1 is shifted to SR-R7, and the block data of #P-2 is moved from the memory element array MEM to SR-R8. Next, the memory element array MEM
, the block address of #P-10 is given from the address generator 2, the block data of #P that was in SR-R6 is shifted to SR-R5, and the block data of #P that was in SR-R7 is shifted to
-1 block data is shifted to SR-R6, and SR
-The block data of #P-2 that was in R8 is now SR-R7
#P-10 from the memory element array MEM
block data is moved to SR-R8. Next, the block address of #P-20 is given to the memory element array MEM from the address generator 2, the block data of #P that was in SR-R5 is shifted to SR-R4, and the block address of #P-20 is given to the memory element array MEM.
-The block data of #P-1 that was in R6 is now SR-R5
The block data of #P-2 which was in SR-R7 is shifted to SR-R6, the block data of #P-10 which was in SR-R8 is shifted to SR-R7, and the block data of #P-2 which was in SR-R7 is shifted to SR-R7. The block data of #P-20 is transferred to SR-R8.

Thereafter, similar operations are repeated, and after 8 cycles counting from the beginning, SR-R1 has #P data block SR-R2, #P-1 data block SR-R3 has #P- 2 data block SR-R4 has #P-10
The data block SR-R5 of #P-20 has the data block SR-R6 of #P-21.
-R7 has the data block #P-30, and SR-R8 has the data block #P-50. Therefore,
In the product-sum calculation circuits MA-1 to MA-8, a 64-tap filter calculation expressed by [Equation 1] is performed.

That is, the first term of [Formula 1] is calculated by the product-sum calculation circuit MA-1 via SR-R1, and the second term of [Formula 1] is calculated by SR-R2.
The third term of [Equation 1], which is calculated by the product-sum calculation circuit MA-2, is calculated by the product-sum calculation circuit MA-3 via SR-R3.
The eighth term of [Formula 1] is calculated by the product-sum calculation circuit MA-1 via the SR-R8. Each product-sum calculation circuit MA-1 to M
The above operations in A-8 are performed in parallel and simultaneously.

Product-sum calculation circuits MA-1 to M of product-sum calculation section 3
The coefficients for each product-sum operation in A-8 are: *0 coefficient set is used in MA-1, and *1 coefficient set is used in MA-2.
For MA-3, a coefficient set of *2 is used; for MA-4, a coefficient set of *10 is used; for MA-5, a coefficient set of *20 is used; −6, a coefficient set of *21 is used and M
In A-7, a coefficient set of *30 is used, and in MA-8
In , a set of *50 coefficients is used, and these coefficients change in response to changing ghost conditions.

The operation of transferring data from SR-W to memory element array MEM and the operation of transferring data from memory element array MEM to SR-W
The 9 cycles of operation to transfer data from R1 to SR-R8 are as follows:
The input data is serially input to the SR-W and the operation is performed simultaneously in parallel with the operation until the next data block is determined. Therefore, these nine cycles are required to be performed in about 560 ns, but the operation of the multiport memory 1 is about 62 ns per cycle, which is almost the same operating speed as the input cycle, and a special high-speed There is no problem as no action is required.

(a) If the above input data is SR-W
and (b) an operation of 9 cycles to shift data from SR-W to memory element array MEM and from memory element array MEM to SR-R1 to SR-R8. Two operations (a) and (b) are performed simultaneously in parallel. That is, the calculations of the 8-tap FIR filters in each of the product-sum calculation circuits MA-1 to MA-8 need to be performed in 560 ns, but since each tap takes 70 ns, this is also not a problem.

To summarize the above operations, (a) 8-cycle operation in which input data is shifted to SR-W; (b) S
Operation of transferring data from R-W to memory element array MEM and from memory element array MEM to SR-R1 to SR-R
(c) The product-sum calculations of the 8-tap FIR filters in the product-sum calculation circuits MA-1 to MA-8 are all performed simultaneously in parallel. For this reason,
The operation (a) handles data of a block one block before the operation (b). Also, the operation in (b) is (
The data of the block one block before the operation in c) is handled. The above description explains the operation of the calculation when the block of input data of #P is written to the memory element array MEM.

Next, the input data block #P+1 is written to the memory element array MEM. In this case, an operation using #P+1 as the base point is performed instead of #P in the above explanation. The same applies to the following data of #P+1. Note that since the memory element array MEM is as shown in FIG. 7, the address of the input data marked with # is mod. 80 (modulo addition modulo 80).

In the above description, the input data block is
Groups of non-zero coefficients are also selected from among the groups divided in order of 8 taps, which are divided into 8 samples in the order of arrival. This constraint can be weakened by devising the configuration of the memory element array MEM.

Although a standard television is used in this embodiment, the present invention is not limited to this. Also,
Not limited to digital filters for ghost cancellers,
It is also possible to apply the present invention to cases where it is necessary to change the taps on which the filter calculation is performed adaptively.

[0041]

According to the present invention, unnecessary tap operations can be avoided and the number of arithmetic units can be reduced to the minimum necessary. In other words, it is easy to reduce the product-sum calculator having 600 taps to a fraction of its size. Instead, multi-port memory is required, but multi-port memory originally had the same purpose as the register for holding data for 600 taps, and because it has a higher degree of integration than logic such as registers, it can be made smaller. Become. Since the scale of the hardware can be reduced to a fraction of that in this way, it becomes possible to reduce power consumption and to keep costs low. Furthermore, even if the antenna position is changed or the surrounding buildings that cause ghosting are changed, unnecessary tap calculations can be adaptively avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing the configuration of an example of an adder circuit that can be used in the present invention.

FIG. 3 is a diagram showing the configuration of another example of an adder circuit that can be used in the present invention.

FIG. 4 is a block diagram showing a partial configuration of an embodiment of the present invention.

FIG. 5 is a connection diagram showing switches used to connect a shift register and a bus.

FIG. 6 is a schematic diagram showing an example of a filter coefficient sequence.

FIG. 7 is a schematic diagram showing addressing of the memory element array MEM.

FIG. 8 is a block diagram of a conventional digital filter.

FIG. 9 is a schematic diagram showing a digital filter used in a ghost canceller.

FIG. 10 is a block diagram of an example of a unit product-sum calculation circuit.

FIG. 11 is a block diagram of another example of the unit product-sum calculation circuit.

FIG. 12 is a schematic diagram showing a digital filter used in a ghost canceller.

FIG. 13 is a schematic diagram of an illustrative wide-bandwidth memory of the prior art.

[Explanation of symbols]

1 Multi-port memory 2 Address generation circuit 3 Product-sum calculation unit MEM Memory element array SR-W Shift registers SR-R1 to SR-R8 forming write ports Shift registers forming read ports

Claims (1)

[Claims] 1. A serial access write port and a plurality of serial access read ports, wherein an input data string is written to the write port in blocks each consisting of n pieces of data; a multi-port memory from which any plurality of blocks are read from the read port each time; a sum-of-products calculation circuit connected to each of the read-out ports; a read block address of the multi-port memory and the sum-of-product calculation circuit; an adaptive digital filter comprising: coefficients given to the filter; and means for generating the coefficient.