JPH04326626A - Soft discrimination circuit - Google Patents

Abstract

PURPOSE:To avoid the adjustment for a reference voltage or the like of an A/D converter and to convert a signal with high accuracy even in the case of a change in a signal level in the soft discrimination circuit in which digital modulation wave such as an MSK modulation wave is demodulated and Viterbi decoding or the like is implemented via the A/D converter. CONSTITUTION:An output of a detector 8 detecting a maximum value of an input signal level of an A/D converter 2 and a detector 9 detecting a minimum value is inputted to a maximum reference voltage terminal 11 and a minimum reference voltage terminal 14 of the A/D converter and a reference voltage is changed in matching with a change in a signal level. A midpoint reference voltage 13 of the A/D converter 2 is used for a bias voltage of the input signal coupled in terms of capacitance to ensure the accuracy of the MSB of A/D conversion with respect to the change in the signal level. Thus, four adjustment positions of the reference voltage of A/D converter are not required and even when the signal amplitude is changed thrice, the A/D conversion is attained while keeping the accuracy. The accuracy of the MSB is secured against a change in the signal level.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a circuit that is used for digital transmission signals and performs soft decisions in order to perform error correction using analog weights such as Viterbi decoding on digitally modulated signals such as MSK modulation and QPSK modulation. It is something.

0002

2. Description of the Related Art Conventionally, demodulation and soft decisions of digitally modulated signals such as MSK modulated signals and QPSK modulated signals have been performed using a configuration as shown in FIG. The signal demodulated by the digital demodulation circuit 1, for example, becomes an analog signal called the well-known eye pattern in the MSK demodulation circuit, and two types of analog signals, an in-phase component signal (I) and a quadrature component signal (Q), are generated. Output from the digital demodulation circuit. Only one of them is illustrated here. In order to match the amplitude level of this signal with the input level of the A/D converter, first cut the DC component with capacitor 4, divide it with resistor 17 and variable resistor 18 to match the level, and add an offset voltage with power supply 19 to this signal. The signal is input to the input terminal 12 of the A/D converter 2 via the buffer amplifier 5 in order to lower the output impedance. The A/D converter used for such applications is of a high-speed type, and is of a type usually called a flash type, which has 2 -1 comparators depending on the number of bits N. In such an A/D converter, in order to obtain a comparison voltage, a maximum reference voltage VRT and a minimum reference voltage VR are used as reference voltages.
Generally, B is given from outside. In the case of FIG. 2, VRT and VRB are applied to input terminals 11 and 14 by power supplies 15 and 16, respectively. VRM is VRT, VRB
This is the midpoint voltage terminal of the A/D converter, and is normally grounded through a capacitor 10 as shown in the figure, and is used to reduce noise in the comparison voltage inside the A/D converter. Further, 101 is an input terminal for a clock signal supplied from the digital demodulation circuit 1. Soft decisions are made by connecting in this way. Such soft decisions are disclosed in detail in Japanese Unexamined Patent Publication No. 60-218953. The A/D converted digital data is output from the output terminal 3 and input to a subsequent Viterbi decoding circuit or the like.

0003

[Problem to be Solved by the Invention] As an example of how to provide a reference voltage for an A/D converter, as shown in Figure 3, there is an example in the Hitachi High Speed A/D/D/A Converter Handbook (published in March 1990). The ones shown are common. In other words, the reference voltage is obtained using a semi-fixed resistor and an operational amplifier. This is to lower the output impedance. In this way, in the circuits shown in FIGS. 2 and 3, in order to match the output signal level of the digital demodulation circuit 1 with the input level of the A/D converter 2, adjustment is required at four points: the signal level, the offset voltage, and the reference voltage. , there was a problem that there were many adjustment points. Furthermore, the output signal level of the digital demodulation circuit 1 is normally subjected to AGC (automatic gain control) at the previous stage, but in the range where AGC stops operating or when the amplitude changes due to temperature characteristics, There was a problem that /D conversion was no longer possible. SUMMARY OF THE INVENTION An object of the present invention is to provide a soft decision circuit that eliminates the drawbacks of conventional circuits, such as having many adjustment points and generating errors due to changes in output amplitude level. Also, Fig. 4 shows the A/D
Another way of using the reference midpoint voltage terminal 13 of the converter is shown. A
In order to improve the accuracy of /D conversion, a correction voltage is inputted from the outside as shown in FIG. 4, and this is also disclosed in the aforementioned handbook. In this case, there will be more adjustments to make.

0004

[Means for Solving the Problems] In order to achieve the above object, a level detector is provided for the input signal of the A/D converter, and the reference voltage of the A/D converter is detected according to the output of the level detector. ) can now be controlled. maximum and minimum 2
For an A/D converter having two reference voltage terminals, a peak level detector for detecting the maximum level of the input signal and a bottom level detector for detecting the minimum level are provided, and the outputs of these two detectors are It is now input to the reference voltage terminal.

[0005] Also, as a bias for a capacitively coupled input signal, a voltage is taken out from a terminal from which a midpoint voltage between two reference levels is output and used.

[0006]

[Operation] The peak level detector that detects the maximum level of the signal and the bottom level detector that detects the minimum level can accurately detect the maximum and minimum levels by having a sufficiently large time constant relative to the signal transmission frequency. And so. As a result, the reference voltage of the A/D converter can keep up with AGC drift or a signal at a level where AGC cannot function, and it is possible to always perform accurate A/D conversion with few errors.

Furthermore, by using the midpoint potential of the reference voltage as a bias for the capacitively coupled input signal,
The most important MSB of the A/D conversion result without adjustment
It is possible to always maintain the best conversion accuracy. By combining this midpoint bias and supplying the maximum and minimum reference voltages from the level detector, the A/D converter ideally follows changes in signal level.
Conversion accuracy can be further improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the drawings. Figure 1
1 is a block diagram showing an embodiment of the present invention. FIG. Components in FIG. 1 having the same numbers as those in FIG. 2 described in the conventional example have the same functions as those in FIG. 2. In Figure 1, 6 is a bias resistor for biasing the input signal whose DC component has been cut by capacitor 4, 7 is a power supply for bias voltage supply, and 5 is a buffer amplifier for lowering the output impedance. . 8 is a peak level detector for detecting the maximum level of the output signal of the buffer amplifier 5, and 9 is a bottom level detector for detecting the minimum level. These outputs are supplied to a maximum reference voltage terminal 11 and a minimum reference voltage terminal 14 of the A/D converter 2, respectively. Normally, the voltage VRT of 11 is 3.5V, and the voltage of 14 is 1.5V.
It is about 5V, and even if it changes about ±0.5V, A
/D converter works normally. This reduces the signal amplitude to 1
Even if the voltage changes three times from Vpp to 3Vpp, A/D conversion can be performed correctly, eliminating the need for adjustment and making it possible to track AGC drift. FIG. 5 shows another embodiment of the present invention, in which the reference voltage of the A/D converter is only one, and the signal is input between 0V and 2.5V. It is possible to change the maximum level by approximately ±0.5V using the peak level detector 8.

FIG. 6 shows another embodiment of the present invention, with a capacity of 4
A bias is applied to the signal from which the DC component has been cut by the midpoint reference voltage of the A/D converter. In A/D conversion, the conversion accuracy of the MSB is most important, and this depends on the accuracy of the midpoint potential. Therefore, by providing VRM, which is the exact midpoint between VRT and VRB, as the midpoint offset voltage of the signal, conversion accuracy can be improved without adjustment. In the case of FIG. 6, even if the signal amplitude changes, only the midpoint accuracy can be ensured. FIG. 7 shows another embodiment in which the midpoint bias is provided from the VRM. Since the connection to the positive input terminal of the buffer amplifier 5 has high impedance, the midpoint potential hardly changes. However, care must be taken because the input signal is inverted. FIG. 8 is an example in which a buffer 27 is added to the example of FIG. 6 in order to reduce the influence on the midpoint potential. By doing so, it is possible to reduce the resistance value of the resistor 6. Figure 9 shows a combination of the example in Figure 1 and the example in Figure 8. This configuration eliminates adjustment and ideally maintains the midpoint, maximum, and minimum voltages even when the signal level changes. The conversion accuracy can be improved by changing the value.

FIGS. 10(a) and 10(b) show examples of a peak level detector 8 and a bottom level detector 9, which can be easily realized using known circuits.

[0011]

As described above, in a system in which a digital demodulated signal subjected to MSK demodulation or QPSK demodulation is subjected to a soft decision via an A/D converter, the digital demodulated signal and the A/D demodulated signal are
Even if the reference voltage adjustment of the D converter is not adjusted and the signal level changes due to changes in AGC due to temperature characteristics, etc., the A
Since the reference voltage of the A/D converter changes in accordance with the signal level, A/D conversion accuracy can be ensured correctly. In addition, by supplying the midpoint reference voltage of the A/D converter as a bias for the capacitively coupled signal, correct midpoint accuracy can always be maintained even when the signal level changes.
The conversion accuracy can be improved. Furthermore, by combining the above two terms, there is no need for any adjustment, and even when the signal level changes, both the amplitude and midpoint are ideally adjusted.
The D converter keeps track of the changes, making it possible to always maintain conversion accuracy. In an example in which the maximum reference voltage and minimum reference voltage are provided from a level detector, ideal A/D conversion is performed for a three-fold change from 1Vpp to 3Vpp.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a conventional configuration diagram.

FIG. 3 is a conventional reference voltage circuit diagram.

FIG. 4 is a diagram showing an example of the use of a conventional midpoint voltage terminal.

FIG. 5 is a configuration diagram showing another embodiment of the present invention.

FIG. 6 is a configuration diagram showing the midpoint bias of the present invention.

FIG. 7 is a configuration diagram showing another embodiment showing the midpoint bias of the present invention.

FIG. 8 is a configuration diagram showing another embodiment of the midpoint bias of the present invention.

FIG. 9 is a configuration diagram showing another embodiment of the present invention.

FIG. 10 is a configuration diagram showing an example of a peak level detector and a bottom level detector.

[Explanation of symbols]

8...Peak level detector, 9...Bottom level detector, 11...Maximum reference voltage terminal of A/D converter, 12...Input terminal, 13...Middle point voltage terminal, 14...Minimum reference voltage terminal, 5...Buffer amplifier , 27...buffer amplifier.

Claims (4)

[Claims] 1. A soft-decision demodulation circuit that makes a soft decision on a digital modulation signal, which includes a level detector that detects the level of the digital modulation signal that is subjected to a soft decision, and converts the output of the level detector into a reference voltage of an A/D converter. A soft decision circuit characterized by supplying power to a terminal. 2. According to claim 1, the level detector is a peak level detector having a sufficiently large time constant compared to the transmission rate of the digital modulation signal, and comprises two peak level detectors, and a A first peak level detector detects the maximum level of the digital modulation signal, a second peak level detector detects the minimum level, and the output of the first peak level detector is sent to an A/D converter. a maximum level reference voltage terminal of the A/D converter, and an output of the second peak level detector is supplied to a minimum level reference voltage terminal of the A/D converter. 3. A soft-decision demodulation circuit that soft-decisions a digital modulation signal, which capacitively couples and inputs the digital modulation signal, and outputs a voltage at the midpoint between the maximum reference voltage and the minimum reference voltage of the A/D converter. A soft decision circuit characterized in that a midpoint reference voltage is used as a bias voltage for a digital modulation signal. 4. In claim 2, the digital modulation signal is capacitively coupled and input, and a midpoint reference voltage for outputting a voltage is set at a midpoint between the maximum reference voltage and the minimum reference voltage of the A/D converter. A soft decision circuit characterized in that the bias voltage is a digital modulation signal.