JPH0432367A - Hierarchy picture generating device - Google Patents

Abstract

PURPOSE:To generate a hierarchy picture at a high speed by providing a storage means storing a picture data and plural generating means generating a hierarchy picture with respect to a picture data stored by the storage means to the generating device. CONSTITUTION:When an original picture data is inputted through a data line 15, the data is stored in an original picture memory and latched in a latch 16 as a data for 225 picture elements. Then the data is given to an LUT(Lookup Table) 20, in which 1st hierarchy data for 49 picture elements (7 picture elements in main scanning direction and 7 picture elements in subscanning direction) is formed. Then the data by 49 picture elements is latched by a latch 19 and stored in a picture memory 12 and given to an LUT 21, in which a block data being a 2nd hierarchy picture (3 picture elements in main scanning direction and 3 picture elements in subscanning direction) is formed, the 1st hierarchy picture is stored in the picture memory 12, the 2nd hierarchy picture is stored in the picture memory 13 and a 3rd hierarchy picture is stored in the picture memory 14 respectively simultaneously. Thus, the hierarchy picture is generated at a high speed with simple constitution.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a hierarchical image generation device, and more particularly to a hierarchical image generation device capable of generating a plurality of hierarchical images by recursively performing reduction processing on image data. It is something.

[Prior Art] In recent years, a hierarchical encoding method has been proposed as an encoding method for image communication for soft copies such as displays.

This hierarchical encoding method first performs subsampling using spatial filtering on the input image to be encoded (hereinafter referred to as the original image), and then recursively processes reduced images with lower resolution. We will create it according to the purpose. The image created here is a hierarchical image. Next, during transmission, the images are encoded from the lowest resolution to the highest resolution, and the encoded image data is transmitted (.

On the other hand, on the receiving side, by converting these hierarchical images into single numbers and displaying them, the image content can be grasped at an early stage of transmission.

As described above, an apparatus for generating a hierarchical image using an encoding method that facilitates early understanding of the image content is conventionally configured as shown in FIG.

In the figure, 71 is an original image memory, which is a memory that stores an original image. 72 is a reduction unit, which reduces the original image stored in the original image memory 71; 73 and 74 are image memories A and B, which store the reduced images generated by the reduction unit 72; It is. 7
Reference numeral 5 denotes an encoding unit, which encodes the image data stored in each memory 71, 73, and 74. Reference numeral 76 denotes a controller, which performs overall control.

The operation of the hierarchical image generation device having the above configuration will be explained below.

In the following explanation, the reduction ratio between each hierarchical image is set to 1/2 in the main scanning direction and the sub-scanning direction of the image, and the resolution of the image with the lowest resolution is set to 1/1 in each of the main scanning and sub-scanning directions.
Set it to 6. In addition, each memory 71, 73, 74 and the reduction unit 7
The controller 76 controls input/output to and from the encoder 2 or the encoder 75.

First, the operation of generating a 1/16 image in the main scanning and sub-scanning directions will be explained.

The image data is read from the original image memory 71 and the reduction unit 7
Transfer to 2. Then, the reduction unit 72 generates a 1/2 size image (hereinafter referred to as a first layer image) and stores it in the image memory A73. Next, the first layer image is read from the image memory A73, and the reduction unit 72 again
Transfer to.

Here, a 1/4 size image (hereinafter referred to as a second layer image) is generated and stored in the image memory B74.

Similarly, image data is exchanged between the image memory A73 and the image memory B74 via the reduction unit 72, and finally a 1/8 size image (hereinafter referred to as
An image of 1/16 size (hereinafter referred to as a fourth layer image) is stored in the image memory B74.

Thereafter, the fourth layer image is transferred from the image memory B74 to the encoding unit 75, encoded, and transmitted from the transmission path 77. The third layer image in the image memory A73 is similarly encoded and transmitted from the transmission path 77. Next, when encoding the second layer image and the first layer image,
The original image is read out from the original image memory 71 again, and after each hierarchical image is generated, encoding is performed.

Note that techniques such as a thinning method and a projection method are often used to reduce an image, but in order to facilitate the explanation of the embodiments to be described later, image reduction by a projection method will be described.

This projection method performs calculations using a filter that weights the degree of influence from each original image pixel on a pixel that has been reduced according to the reduction magnification, in accordance with the position of the pixel of interest. Hereinafter, a case will be described taking as an example a case where both the main scanning and sub-scanning are reduced to 1/2.

The 3×3 pixel group shown in FIG. 8 is the target pixel of the filter, and here, the value of each pixel is expressed as
”” Let it be X m *. FIG. 9 shows the weight of the filter, and the value y of the generated reduced pixel is obtained by the following formula.

y = 1/6 X (xao+xoa+xxo+x*
i) + 2/16 X (X o++ X +o+
X 12+ X *+)+ 4/16 X X + +
...(1) Also, the original image is 2
If the image is expressed by a value, the value yT of the reduced pixel is
Compare y obtained by formula (1) with threshold T and calculate the following (2
) is determined as follows.

(L=♂)+(-12) By repeating this filter calculation by overlapping the pixel of interest and the center of the filter as shown in Figure 10, an image reduced to 1/2 size can be obtained. It will be done.

[Problems to be Solved by the Invention] However, in the conventional example described above, the hierarchical image to be encoded is generated by reducing the size of the original image as necessary, so there is a drawback that high speed is lacking.

The present invention was made to solve the above problems, and
Hierarchical image generation unit that can generate hierarchical images at high speed! The purpose is to provide

"Means and operations for solving the problem" In order to achieve the above object, the hierarchical image generation device of the present invention has the following configuration. That is, the hierarchical image generation device of the present invention recursively performs reduction processing on image data to generate multiple A hierarchical image generation device capable of generating hierarchical images includes a storage means for storing image data, and a plurality of generation means for generating hierarchical images from the image data stored in the storage means.

Further, a hierarchical image generation device of another invention is a hierarchical image generation device capable of generating a plurality of hierarchical images by recursively performing reduction processing on image data, and includes a storage means for storing image data, and a storage means for storing image data; For image data stored by means,
It includes a plurality of generation means that generate hierarchical images, and an encoding means that encodes the plurality of hierarchical images generated by each generation means.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing a system configuration of a hierarchical image generation device in an embodiment.

In the figure, 1 is a CPU, which controls the entire system, and 2 is a magnetic disk, which stores original image data and the like. 3 is a bus, which carries image data and CPU
Control commands issued by.

Exchange the status of various devices. Reference numeral 4 denotes a hierarchical image generation unit, the details of which will be described later, which generates a plurality of hierarchical images. Reference numeral 5 denotes a transmission path through which encoded data is transmitted.

Note that although the hierarchical image generation unit 4 in the embodiment will be described as having a configuration including an encoding unit that encodes the generated hierarchical image, it may have a configuration that does not include the encoding unit. Also,
The epui includes a ROM that stores the processing procedures of the CPU 1, and an RA such as a work area used by the CPU when executing processing.
Contains M.

In the above configuration, the hierarchical image generation unit 4 in the embodiment is
When an original image is input from the magnetic disk 2 via the bus 3 under the control of the CPU, a layered image is generated from the original image, encoded from a low-resolution image, and transmitted to the outside via the transmission line 5.

<First Example> Next, the hierarchical image generation unit 4 in the first example will be described below with reference to FIG. 2.

FIG. 2 is a schematic block diagram showing the configuration of the hierarchical image generation section 4. As shown in FIG. In this embodiment, a case will be described in which a hierarchical image is generated using a binary image as an original image.

In the figure, 11 to 14 are image memories, respectively.
IJ is a memory for storing the original image, and 12 to 1
4 is a memory for storing a first layer image, a second layer image, and a third layer image, respectively. A data line 15 is connected to the outside, for example, the bus 3 in FIG. 1, and is used to read original image data. Numerals 16 to 19 are latches, respectively, which keep the data delay constant. 20 to 22 are L U T (Look U
23 is an address counter that generates an address for reading data from the original image memory.

24 to 26 are address counters, respectively, which generate addresses for writing data into each of the image memories 11 to 14. 27 is an encoding unit that encodes each hierarchical image. A data line 28 is used to send encoded data to the transmission line 5 in FIG.

Note that the reduction ratio between each hierarchical image is set to 172 in both the main scanning and sub-scanning directions, and the projection method described above is used as the reduction method. In the case of the projection method, the number of pixels required to generate one reduced pixel is 9, and if the target is a binary image, it is composed of a ROM etc. with 9 bits of input and 1 bit of output. This can be realized by LUT. Then, in advance (1
), reduced pixel data determined by 9-bit input according to equation (2) is stored.

In addition, in the projection method, pixels other than the pixel of interest are 0, which is used multiple times.
For example, adjacent reduced pixels share three pixels. Therefore, when obtaining two reduced pixels with one ROM, the input to the ROM 31 is 15 bits and the output is 2 bits, as shown in FIG. 3(b).
etc. can also be sufficient. The input is a pixel value a~0,
The output is the reduced pixel value A, B 0 For example, 32768w
An ordX 8-bit mask ROM may be used, and this ROM 31 is used to configure each of the reduced LUTs 20 to 22.

The scale of LUT 20 is 225 bits for input and 49 bits for output, the scale of LUT 21 is 49 bits for input and 9 bits for output, and the scale of LUT 22 is 9 bits for input and 1 output.
It's bit. In other words, LUT20 is 32768wo
rdX 24 8-bit ROMs, the smallest ROM is 8
Assuming that it is 192 words x 8 bits, this can be configured with one piece.

Similarly, LUT21 is 32768 wordX 8 bi
4 t ROMs and 8192 wordX 8 bit
, there is one ROM, and L U T 22 is 8192
It can be configured with one wordX 8-bit ROM.

Next, the operation of hierarchical image generation in this embodiment will be described below with reference to FIG.

Note that address counters 23 to 26 and latches 16 to 1
9 is supplied with the same clock by a clock supply line (not shown). In addition, each address counter 23 to 2
6 is the pixel address (0,
O) are respectively on the upper left.

First, when original image data is input via the data line 15, the data is stored in the original image memory 11. Next, as pixel block data (data for 225 pixels) of 155 pixels in the main scanning direction and 155 pixels in the sub-scanning direction, the latch 16
latched to.

Then, the above-mentioned 225-pixel data is stored in the LUT 20 for 7 pixels in the main scanning direction and 7 pixels in the sub-scanning direction of the first layer image.
This is pixel block data (499 pixel data).

Next, this 499 pixel data is latched in the latch 17, and at the same time, the latch 16 is latched in the original image memory 11.
15×15 data is input from pixel address (15, O). Then, the address counter 24 starts from the pixel address (0, O) on the image memory 12 in the main scanning direction 7.
An absolute address for writing pixel block data of 7 pixels in the sub-scanning direction is generated. As a result, the 499-pixel data read from the latch 17 is stored in the image memory 12, and at the same time becomes block data of 3 pixels in the main scanning direction and 3 pixels in the sub-scanning direction of the second layer image by the LUT 21.

The data for these nine pixels is latched by the latch 18 and similarly stored in the image memory 13 by the address counter 25. Then, similarly, the next LUT2
2, a third layer image is generated.

By performing the above operations, the image memory 14 stores the first
A hierarchical image, a second hierarchical image is generated in the image memory 13, and a third hierarchical image is generated in the image memory 14 at the same time.

Next, based on these results, the encoding unit 27 encodes each hierarchical image alone or by referring to the lower resolution image one level higher.
For example, when encoding an image alone, since the input image is a binary image, encoding is performed using MH encoding or MMR encoding using a run length that is generally used in facsimile etc. .

Many methods have been proposed for performing encoding with reference to the next higher resolution image, but arithmetic encoding will be used here for explanation. Arithmetic coding divides a probability number line into intervals according to the probability of appearance of a symbol sequence, and uses a binary decimal value that indicates the position within the divided interval as the code for the sequence. J Vol, 43
．． No. 12 (1989) pp. 1361-1369)
.

In other words, when encoding a symbol, this encoding improves the encoding efficiency if the probability of occurrence of that symbol is close to the probability of occurrence predicted from the surrounding or previous situation (high accuracy). .

On the other hand, except for the uppermost low-resolution screen, when decoding an image, the low-resolution screen one level above has already been decoded and can be referenced. Furthermore, since the lower resolution screen one level higher is defined by reduction processing, there is a strong pixel correlation between layers. Based on these facts, by referring to the pixels of the next lower resolution screen, it is possible to improve the accuracy of the predicted appearance probability and to improve the encoding efficiency.

FIG. 11 shows the reference pixel group. FIG. 11(8) shows the hierarchical screen on which encoding is performed, and FIG. 11(b) shows the same position on the lower resolution screen one level above.

In the figure, 110 a ~ x, l 11 A ~
F represents a pixel, and it is assumed that the pixel 110u is equivalent to the position of the pixel 111E. Here, the pixels to be referred to when encoding the pixel 110u are 1101. m, n, and pixel 1
11A, B, C, D, E.

Further, FIG. 12 is a schematic block diagram showing the configuration of the encoding section. Data lines 137 to 140 are respectively connected to image memories that store images in each layer shown in FIG. Then, a data line 140 sequentially reads out image data from the image memory 11 in the scanning line direction, and a selector 136 switches and inputs screen data to be encoded.

When encoding the third layer screen, connect the data line 137 to the data line 126, and when encoding the second layer screen, connect the data line 137 to the data line 125 and the data line 138 to the data line 126. .

Similarly, the data line of the screen to be encoded is connected to the data line 12.
6, connect the data line of the lower resolution screen one above to be referenced to the data line 125. 121 to 124 are FIFOs, the output of FIFO 124 is the input of PIF0123, and the output of FIFO 125 is the input of FIFO126. 127 to 132 are latches that delay data by one cycle. These FIFOs and latches allow pixel 1 * m + n + and pixel 11
1A.

B, C, D, and E are input to the predictor 133. This predictor 133 is a circuit that predicts the appearance probability of the pixel 110u from these reference pixel data.

Then, the prediction result and the data of the pixel 110u are input to the encoder 134, and encoded data is output from the data line 135. The encoded data thus obtained is sent to the transmission line 28 via the data line 28.

Note that the above-mentioned arithmetic encoding is a known technique;
Detailed explanation will be omitted.

<Second Embodiment> Next, the hierarchical image generation unit 4 in the second embodiment will be described below with reference to FIG. 4.

FIG. 4 is a schematic block diagram showing the configuration of the hierarchical image generation section 4. As shown in FIG. As shown in the figure, in this embodiment, since the circuit scale increases as the number of layers increases, the image reduction processing section that performs image reduction processing is configured with two or more stages. In the figure, 10a and 10b are image reduction processing units, excluding the encoding unit 27 shown in FIG.

40 is a data line for reading original image data; 41 to 40;
48 is a data line for reading image data of each layer;
Reference numeral 9 denotes an encoding unit that performs encoding, and 5° denotes a data line that sends encoded data to the transmission path 51.

In the above configuration, when original image data is input via the data line 40, the data is stored in the original image memory 11 shown in FIG. Then, similar to the operating procedure described in the first embodiment, images up to the third layer are created.

Next, the third layer image is sent to the image reduction processing section 10b,
The image is stored in the original image memory 11. Here, it goes without saying that the original image memory 11 of the image reduction processing section 10b may have the same size as the image memory 14 of the image reduction processing section 10a.

Then, the image reduction processing unit 10b similarly performs the fourth to sixth
Generate a hierarchical image. Here, the data line from the original image memory of the image reduction processing section 10b to the encoding section 49 is unnecessary.

Therefore, the encoding unit 49 reads the original image data from the data line 41 and the first to sixth layer image data from the data lines 42 to 47, encodes them, and sends them out from the data line 50.

Third Embodiment> In the above-mentioned embodiments, the case where a binary image is processed was explained as an example, but the case where the present invention is applied to a multi-valued image will be explained below as a third embodiment.

First, as an image reduction means, in the embodiment described above, each LU 720 to 22 was used as shown in FIG. is difficult.

For example, considering an image with a data amount of 8 bits per pixel, one projection method requires an input of 8×9=72 bits, which cannot be constructed using a ROM or the like. Therefore, the fifth
The reduction unit shown in the figure is used.

In the figure, 100a to 100d, 101a.

101b, 102, 104 are adders, 103a to 103
1 is a data line for inputting nine pixel data necessary for the projection method, and 105 is a data line for outputting a reduced pixel value.

In the above configuration, the data lines 103a and 103b.

From C and d, the pixel values X oo and X ox+X say X *m at the position of filter weight 1/16 are input, respectively. In addition, data lines 103e, f, g and h
, the pixel value at the position of filter weight 2/16 is X0. .

Input Xlo and Xli+X*□, respectively. Then, from the data line 1031, the x-th pixel value of interest is input.

Further, adders 100a-d input two pieces of 8-bit data and output 9-bit data, and adders 101a, b input two pieces of 9-bit data and output 10-bit data. The output of the adder 101a has a filter weight of 1.
The adder 101b outputs the sum of pixel values whose filter weight is 2/16.

Next, the adder 102 shifts the output of the adder 101b by 1 bit and multiplies it by a weight of "2", and adds the output of the adder 101b.
Add the output of a. Also, by adding and shifting 2 bits of “0” to the lower side of the data line 1031,
An adder 104 adds the pixel value of interest multiplied by a weight of "4" and the output from the adder 102 . Then, the lower 4 bits are discarded and the value of the reduced pixel is obtained from the data line 105 by dividing by 1/16.

That is, the input is 72 bits, the output is 8 bits,
This level of scale is easy in recent years when customizing ICs.

FIG. 6 is a schematic block diagram showing the configuration of a hierarchical image generation section using the above-mentioned reduction section.

In the figure, 511 to 514 are image memories, respectively, 511 is an original image memory that stores the original image, and 512 to 514 are image memories.
514 is an image memory that stores first to third hierarchical images. 515 is a data line for reading original image data from outside, and 516 to 519 are latches for making data delay constant * 520a to z, A to W, 521a
~i.

522 is an image reduction unit having the configuration shown in FIG.

523 is an address counter that generates an address for reading data from the original image memory 511;
26 is an address counter that generates an address for writing data into each image memory 512-514. 527
is an encoding unit that performs encoding, and 528 is a data line that transmits encoded data.

First, original image data is stored in the original image memory 511 from the data line 515. Each address counter 523 to 526
, latches 516 to 519 are supplied with the same clock by a clock supply line (not shown). Also, similar to the first embodiment, the latch 516 initially operates at the pixel address (0,
Latch the 15×15 pixel data with O) at the upper left. This 15x15 pixel data is divided into 49 7x7 pixel block data, each of which is sent to the image reduction unit 520.
a-z, A=W is input. Then, a filter operation is performed, and 7×7 pixel data is latched into the latch 517.

Next, at the same time as writing the above-mentioned pixel data into the image memory 512, each of the image reduction units 520a to 520Z, A%W
The next 15×15 pixel data is input to perform a reduction operation. Further, the input 7×7 pixel data is divided into nine 3×3 pixel block data, and each is input to the image reduction units 512a to 512i. Then, a filter operation is performed, and 3×3 pixel data is latched into the latch 518.

Thereafter, in the same way, 3x3 pixel data is written to the image memory, and at the same time, 3x3 pixels are input to the image reduction unit 522 to perform reduction operation, and the data is transferred to the memory
14.

That is, a first layer image is generated in the image memory 512, a second layer image is generated in the image memory 513, and a third layer image is generated in the image memory 514 at the same time.

Next, based on these results, the encoding unit 527 encodes each hierarchical image alone or by referring to the lower resolution image one level higher. Note that the encoding is not particularly limited, but any orthogonal transform encoding or the like that encodes a multivalued image may be used.

The encoded data thus obtained is sent out via data line 528.

Further, the image reduction method and reduction rate are not limited to these, and may be other spatial filters, an average value based on calculation, or a majority voting method, and the reduction rate may be different for each layer.

[Effects of the Invention] As explained above, according to the present invention, a hierarchical image can be generated at high speed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the system configuration of the hierarchical image generation device in the embodiment. FIG. 2 is a schematic block diagram showing the configuration of the hierarchical image generation device in the first embodiment. ) is a diagram showing the configuration of the LUT shown in FIG. 2, FIG. 4 is a schematic block diagram showing the configuration of the hierarchical image generation device in the second embodiment, and FIG. 5 is an image reduction diagram in the third embodiment. FIG. 6 is a schematic block diagram showing the configuration of the hierarchical image generation device in the third embodiment; FIG. 7 is a schematic block diagram showing the configuration of the hierarchical image generation device in the conventional example; FIG. 8 is a diagram showing the image matrix of the projection method, FIG. 9 is a diagram showing the weight of the filter of the projection method, FIG. 1O is a diagram showing the pixel position of interest in the projection method, and FIGS. ) is a diagram showing a pixel group referred to during encoding, and FIG. 12 is a schematic block diagram showing the configuration of the encoding section. In the figure, 1...CPU, 2...Magnetic disk, 3...
・Bus, 4... Encoding unit, 5... Transmission line, 10...
- Hierarchical image generation device, 11 to 14... image memory, 1
5...Data line, 16-19...Latch, 20-2
2...LUT, 23-26...address counter,
27... Encoding unit, 28... Data line. Figure 1 (b) Figure 3 Figure 4 Figure 7F! lJ Figure 9 o: 3 on day shift, red Figure 10 Figure 8

Claims (2)

[Claims] (1) In a hierarchical image generation device capable of generating a plurality of hierarchical images by recursively applying reduction processing to image data, a storage means for storing image data, and for the image data stored in the storage means, A hierarchical image generation device comprising: a plurality of generation means for generating hierarchical images; (2) A hierarchical image generation device capable of generating a plurality of hierarchical images by recursively applying reduction processing to image data, comprising: a storage means for storing image data; and a storage means for storing image data in the storage means; A hierarchical image generation device comprising: a plurality of generation means for generating hierarchical images; and an encoding means for encoding the plurality of hierarchical images generated by each generation means.