JPH04322340A - Cache memory - Google Patents

Abstract

PURPOSE:To present a cache memory capable of increasing the speed of access from the external and parity error recovery by performing the parity check at a high speed. CONSTITUTION:The parity check is performed as the retrieval processing using the parity generated from a virtual address by a parity generating circuit 12, and the retrieval processing is performed by the physical address in the case of a mis-retrieval. In the case of success in retrieval, the virtual address tag of the pertinent entry is updated, and the physical address tag read out from the entry is used to perform the parity check of the physical address; and if parity error occurs, the entry where the parity error occurs is updated by the physical address obtained by conversion of the virtual address generated from the virtual address tag of the entry.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory that includes a virtual address tag and a physical address tag in one entry, and has improved parity checking methods and parity error recovery.

0003

2. Description of the Related Art Conventionally, there are two methods for performing a parity check on a tag storing an address in a cache memory. The first method, as shown in FIG.
In this method, the logic gate 3 compares the parities read from the entries of the TP. On the other hand, in the second method, as shown in FIG.
The output of comparator 6 which inputs TAG) and the valid flag (V
) is a method of multiplying the hit check with AND gate 7.

[0004] The first method of generating parity from a tag can check whether the contents of the cache memory have changed due to a soft error or the like. However, since tag reading and parity generation are executed sequentially, parity checking takes time. Therefore, this method is not suitable for cache memories that require high access speed.

On the other hand, the second method of generating parity from an address executes reading of the tag and generation of parity in parallel, thereby realizing high-speed access. For this reason, this method is often used in cache memories. However, since this method treats parity errors as cache errors, even if the contents of the tag change due to a sort error or the like, it cannot be detected.

On the other hand, a double tag cache as shown in FIG. 6 has been proposed as a new method of cache memory. This method has two tags, a virtual address tag and a physical address tag, in one entry, and can be accessed using a virtual address from the CPU and a physical address from the system bus.

[0007] A parity check method in such a double tag cache memory uses a method of generating parity from a read tag. This is because, with the method of generating parity from a physical address when the contents of the physical address change, accesses from the system bus cannot be parity checked, and a hit check will result in a cache miss.

[0008] Therefore, invalidating a cache entry during direct memory access, or invalidating or updating a cache entry to maintain data consistency in the cache memory in a multiprocessor system, results in a cache miss. , incorrect data remains in cache memory. In such a state, if the CPU accesses the virtual address, incorrect data will be given to the CPU, causing malfunction.

[0009] In this way, since the double tag cache generates parity from the read tag, the CPU
Access from was slow. Additionally, in order to recover parity, a trap must be placed and a parity error recovery routine executed, which takes a considerable amount of time.

0010

[Problem to be solved by the invention] As explained above,
In conventional double tag cache memory,
Since parity was generated from the tag read from the entry and the parity check was performed, the parity check took time and external access took time.

[0011] Furthermore, in the parity check, if a parity error occurs, a special sequence must be executed to recover from the parity error, and a lot of time is consumed in executing this sequence. was.

The present invention has been made in view of the above, and its purpose is to speed up external access and recovery from parity errors by performing parity checks at high speed. The objective is to provide a cache memory that can be achieved.

[Configuration of the invention]

[0014]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an entry consisting of a virtual address tag, a parity of the virtual address tag, a physical address tag, a parity of the physical address tag, a valid flag, and data; Generate the parity of the virtual address given from the outside, compare the generated parity with the parity of the virtual address tag read from the entry according to the virtual address, and compare the parity of the virtual address and the parity of the virtual address tag read from the entry according to the virtual address. a first parity check means for outputting a search result for the virtual address and performing a parity check based on a comparison result with a read virtual address tag and a valid flag read from the entry according to the virtual address; Generate a parity of a physical address tag read from the entry according to a physical address given from the outside, and based on a comparison result between the generated parity and the parity of a physical address tag read from the entry according to the physical address. and second parity check means for performing a parity check on the physical address.

[0015]

[Operation] In the above configuration, the present invention performs a parity check as a search process using parity generated from a virtual address, and when a search error occurs, performs a search process using a physical address, and when a match is found. The virtual address tag for that entry is updated.

[0016] Furthermore, the physical address tag read from the entry is used to check the parity of the physical address, and if a parity error occurs, the virtual address generated from the virtual address tag of the entry is converted and the obtained Update the entry where a parity error occurred at the physical address that is specified.

[0017]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a cache memory according to the present invention. In FIG. 1, the cache memory entries of the present invention include a virtual address tag (VTAG), virtual address tag parity (VP), physical address tag (PTAG), physical address tag parity (PP),
It consists of data (DATA), data parity (DP), and valid flag (V).

Parity check on the virtual address side is as follows:
The logic gate 13 compares the parity obtained by inputting the virtual address to the parity generation circuit (PGEN) 12 and the parity (VP) of the virtual address read from the entry, and the comparison result is converted into a virtual address by the comparator 14. AND with tag comparison result and valid flag (V)
This is done by performing a logical AND operation using the gate 15 to generate a virtual address hit signal.

[0020] Parity check on the physical address side is as follows:
By inputting the read physical address tag (PTAG) into the parity generation circuit (PGEN) 16 and comparing the parity obtained with the parity (PP) of the physical address tag and outputting the result as a parity error signal. I am doing it. The physical address hit check is performed by generating a physical address hit signal from the comparison result of the physical address tag by the comparator 18, a valid flag, and a parity error signal.

The virtual address parity generation circuit 12 is as follows:
Since the parity is generated from a virtual address, it is sufficient to provide one parity generation circuit even in the case of a set-associative type cache memory. Furthermore, since parity generation for virtual addresses can be performed in parallel with reading virtual address tags, parity checks can be performed at high speed without reducing cache access speed.

Next, the access operation from the CPU to the cache memory shown in FIG. 1 will be explained with reference to the flowchart shown in FIG.

First, a hit check is performed on the virtual address tag (step 100). If the hit check results in a hit (step 110), the data is accessed (step 120).

On the other hand, if there is a miss, a hit check is performed at the physical address corresponding to the missed virtual address (step 130). If the check results in a hit, this means that data with the same physical address but a different virtual address is registered in the cache, so the virtual address tag of the hit entry is rewritten (step 140).

On the other hand, if the physical address check also fails, it means that the cache does not hold the data requested by the CPU, so select an entry to replace (in the case of direct mapping, the available entries are (there is only one), the CPU refills the selected entry with the requested data (step 150
).

Now, consider the case where a parity error occurs in the virtual address tag. In the cache memory of the present invention, a virtual address parity error results in a cache miss. Therefore, when a hit check is performed using the physical address next, since the physical address is hit, the virtual address tag and the parity of the virtual address tag are written.

Next, when the hit check using the virtual address is performed again, there is a hit, so the data is accessed. Therefore, a special operation is performed to detect and recover from a parity error by treating a parity error in a virtual address tag as a cache miss and performing a hit check on the physical address just like a normal cache miss. parity without
Errors can be recovered.

Next, the operation of accessing the cache memory from the system bus will be explained with reference to the flowchart shown in FIG.

When accessing from the system bus, a hit check is performed using the physical address (step 200), and if there is no parity error and there is a hit (step 2
10, 220), access data or invalidate entries in response to requests from the system bus (
Step 230). On the other hand, if there is no parity error and there is a miss, the cache memory does not respond (step 240).

On the other hand, if a parity error occurs, the virtual address tag is accessed to generate a virtual address (step 250). The virtual address is then translated back to a physical address and a physical address tag is written (step 260) to recover from the parity error.

[0031] In this way, the parity check of the virtual address of the double tag cache memory generates parity from the address and treats the parity error as a cache error, and when a cache error occurs at the virtual address, the physical address Performs a hit check with , and if a hit is found in the physical address, the virtual address tag of the hit entry is rewritten.

[0032] In addition, the parity check of the physical address is performed by generating parity from the read tag.
For an entry in which an error has been detected and a parity error has occurred, the virtual address tag is accessed to generate a virtual address, and a physical address is generated from the virtual address and written to the physical address tag.

[0033] As a result, a parity error of a virtual address tag in an access from the CPU has the same operation as a normal cache miss, and no special operation is required.
Can recover from errors. Furthermore, cache access associated with parity checking can be performed at high speed. Additionally, since parity errors can be handled in the same way as cache errors, hardware can be simplified.

Furthermore, even if a parity error occurs in the physical address tag during access from the system bus, the parity error can be easily recovered by reading the virtual tag address.

[0035]

As explained above, according to the present invention, the parity check of a virtual address is treated as a search process using parity generated from a virtual address,
If a parity error occurs and a match is found in the physical address search, the virtual address tag of the matching entry is updated, and the parity check of the physical address is performed using the physical address tag read from the entry, and the parity error is detected. If this occurs, the virtual address obtained from the virtual address tag of the entry is updated with the converted physical address, making it possible to quickly check the parity of the virtual address. Error recovery can be performed quickly.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a cache memory according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the cache memory shown in FIG. 1;

FIG. 3 is a flowchart showing the operation of the cache memory shown in FIG. 1;

FIG. 4 is a diagram showing a configuration example of a conventional cache memory.

FIG. 5 is a diagram showing an example of a configuration of a conventional cache memory.

FIG. 6 is a diagram showing a configuration example of a conventional double tag type cache memory.

[Explanation of symbols]

1, 8, 11 Cache memory entries 2, 4
, 16 Parity generation circuit 3, 5, 6, 7, 13, 14, 15, 17, 18, 19
logic gate

Claims (3)

[Claims] Claim 1: Generates an entry consisting of a virtual address tag, a parity of a virtual address tag, a physical address tag, a parity of a physical address tag, a valid flag, and data, and a parity of a virtual address given from the outside, and a comparison result of a parity of a virtual address tag read from the entry according to the virtual address, a comparison result of the virtual address and a virtual address tag read from the entry according to the virtual address, and a comparison result of the virtual address tag read from the entry according to the virtual address; Therefore, a first parity check means performs a parity check while outputting a search result of the virtual address based on a valid flag read from the entry, and a physical address read from the entry in accordance with a physical address given from the outside. a second parity check means that generates parity of a tag and performs a parity check of the physical address based on a comparison result between the generated parity and the parity of the physical address tag read from the entry according to the physical address; A cache memory comprising: 2. A mismatch is detected by the first parity check means in a search using an externally given virtual address, and a match is detected in a search performed using a physical address translated corresponding to the virtual address. 2. The cache according to claim 1, wherein the virtual address tag and the parity of the virtual address tag of the entry for which a match has been detected are respectively updated to the virtual address and the parity generated from the virtual address. memory. 3. If a parity error is detected by the second parity check means in a search using an externally given physical address, the physical address of the entry in which the parity error has occurred and the parity of this physical address are verified as valid. Claim 1, wherein the virtual address generated by the virtual address tag read from the entry in which the error has occurred is updated to a physical address obtained by converting the virtual address and a parity generated from this physical address. Or the cache memory described in 2.