JPH04318711A - Majority decision device - Google Patents

Abstract

PURPOSE:To reduce a debug time, a fault ratio and power consumption by forming the device only with a shift register of flip-flop structure and a shift control means. CONSTITUTION:A reception message in 40-bit is given to a shift register 10, '1' is set to its first stage, and the level is packed till the end stage sequentially depending on the state of a shift control means 20 and the result of 3/5 majority decision is outputted from the final stage. The means 20 gives a shift clock to the register 10 when the bit of the reception message selected by a message extraction signal is '1'. Before the operation of the register 10, it is in the reset state and an optional bit of the reception message selected by a reception message extract signal is inputted five times continuously in time series and when '1' is included three times or over, each stage is filled by '1' entirely and the result '1' of decision is outputted. Thus, hazard free state without any transient state is obtained in the result of decision.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention is a method for determining the reliability of data transmission information exchanged between a base station and a mobile station, particularly serial received messages, by majority logic in a cellular mobile telephone system. Regarding equipment.

0002

2. Description of the Related Art In order to improve the reliability of messages received by a mobile station via a downlink from a base station to a mobile station in a cellular mobile phone, the Electronics Industries Association of America has decided to transmit the same data to each other by 5 times. The bit information for each same bit position is determined to be accurate information based on 3/5 majority logic, but in this case, serial data of several bits is input sequentially five times as one data block. The data block is input by a presettable counter with a counting capacity corresponding to the maximum data block length and the number of inputs, and a storage device with a memory capacity corresponding to the assumed maximum data block length. Each time, the number of times the bit information at the same bit position is in a predetermined bit state is cumulatively added and then stored.

0003

[Problems with the prior art] As shown in FIG.
The received messages are sent through 40 sets of 5-stage flip-flops F.
F. During the repetition of 5 times for the downlink control channel and 11 times for the downlink communication channel, a shift clock is inputted and stored by the message extraction signal only when it corresponds to a predetermined bit position. When the downlink control and communication channels are repeated five times, the shift register becomes full and the result is statically output from the 3/5 majority decision section 50 based on random logic. Therefore, a majority decision is made based on the final cumulative addition value obtained for each bit position, which requires a large number of memories and counters with at least a larger capacity than expected, and a control system consisting of gates, counters, etc. in the periphery. Including circuits inevitably results in a large-scale circuit configuration, which becomes enormous and complicated.

0004

[Means for Solving the Problem] Therefore, the present invention receives received messages by a shift register consisting of a three-stage flip-flop and a shift control section, and performs a 3/5 majority decision in time series without storing the messages. It is characterized by
In particular, if one word is 40 bits, 40 sets of lines would be required, but this configuration allows the line scale to be significantly reduced.

[0005]

[Embodiment] An embodiment of the present invention will be explained in detail below with reference to FIGS. 1 and 2. First, in FIG. 1, 10 is a flip-flop F. F. are connected in three stages in cascade, and the received message "1" is input to one of the first stages, a shift register, 2.
0 is a shift control means which inputs the received message, message extraction signal and shift clock, and adds this output as the other input of the shift register in the first stage.

[0006] For a 40-bit received message, "1" is always set in the first stage of the shift register, and depending on the state of the shift control means, "1" is sequentially packed up to the last stage, and the result of the 3/5 majority decision is is output from the third and final stage. Here, the shift control means supplies a shift clock to the final stage shift register only when the bit of the received message selected by the message extraction signal is "1".

Next, the concept of operation for one bit of a received message will be explained with reference to FIG. 2. The shift register is in a reset state before operation, and any bit of the received message selected by the received message extraction signal is
When the bit is received 5 times in a row and the bit is 1, the shift register is filled with 1's and becomes full, and out of 5 received message bits, 1 is received 3 times. If the above is included, each stage of the shift register will be filled with "1", and as a result, the final stage will have "1" as the majority decision result.
” appears, otherwise it is judged as “0” and becomes “0”
Output.

[0008]

Effects of the Invention As described above, since the present invention consists of only a shift register constituted by a simple flip-flop and a shift control means, the judgment result can be hazard-free without any transient state, and the judgment bit length can be reduced. There is no need to reorganize the logic when changing the , just adding or subtracting the number of stages of the shift register is sufficient. In addition, the number of gates used in the basic circuit for majority decision is 41 compared to the conventional circuit.
In contrast, in the present invention, the number of lines is reduced to 24, which reduces the chip area during integration, which in turn reduces debugging time, failure rate, and power consumption. It also contributes to reduction.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a majority decision device of the present invention.

FIG. 2 is a conceptual diagram of the operation in FIG. 1;

FIG. 3 is a circuit configuration diagram of a conventional 3/5 majority decision device.

[Explanation of symbols]

10 Shift register 20 Shift control means

Claims (1)

[Claims] Claim 1: A device for determining the correctness or incorrectness of a serially received message in a cellular mobile phone system by majority logic, wherein the serial data of the received message is always supplied with n bits of "1" in the first stage. n
A shift register with a stage configuration of flip-flops and a shift clock signal is supplied to the first stage shift register only when the bit of the received message selected by the message extraction signal is "1". and a shift control means for taking in only the corresponding bits, and a shift control means for taking in only the corresponding bits.
A majority decision determination device that determines that a majority decision has been made when `` is included n-2 times or more.