JPH04318651A - Microcomputer system - Google Patents

Abstract

PURPOSE:To protect the internal processing of a CPU from being left stopped indefinitely due to lack of the I/O board. CONSTITUTION:The present microcomputer system is equipped with a connection signal generating section 22 that is installed in the I/O board 20 and that grounds the CPU board 10 when connecting the CPU board 10, a signal holding circuit 15 that is installed in the CPU board 10, that holds the rise of an earth signal supplied from the I/O board 20, that sends the earth signal as a connection holding signal, and that sends an input/output prohibit signal to a gate circuit 16, a selector circuit 13 that selects a connecting channel for access destination I/O board 20 in accordance with an I/O request signal and I/O address to I/O board 20, and that transfers and outputs the connection holding signal received from this connecting channel as an operation prohibit signal, and a timer circuit 14 that starts time limit measurement when a connection request is issued to the I/O board 20, that outputs a time limit over signal, after a prescribed time limit passes, to both the interrupt prohibit signal input terminal and operation permission signal input terminal of CPU11, and that prohibits time limit measurement during receiving the operation prohibit signal from the selector circuit 13.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system having data communication or interface control functions for peripheral devices and the like.

0002

[Prior Art] In a conventional microcomputer system, a CPU board equipped with a CPU and memory is
When exchanging data with an I/O board equipped with an I/O circuit for coupling between the U board and peripheral devices, it is necessary to measure the timing because the coupling time with the I/O board differs each time. be.

First, the CPU board outputs an I/O request signal and stops internal processing in order to activate the necessary I/O boards. When the I/O board receives this I/O request signal, it starts access processing to the external interface of the I/O circuit. Next, when data transfer becomes possible, the I/O board outputs a connection confirmation signal to the CPU board. When the CPU board receives this connection confirmation signal, it restarts internal processing and transfers data between the CPU board and I/O board.

0004

[Problems to be Solved by the Invention] In the conventional microcomputer system described above, after the CPU board outputs an I/O request signal, internal processing is not restarted unless a connection confirmation signal is received from the I/O board. If the connection confirmation signal line with the connected I/O board is disconnected, the connection confirmation signal from the I/O board will be output after the CPU board outputs the I/O request signal. C
Since the CPU board cannot receive the signal, there is a problem that the internal processing of the CPU board will not be restarted forever.

[0005]

[Means for Solving the Problems] The system of the present invention includes a CPU board equipped with a central processing unit (CPU) and memory, and an input/output (I/O) circuit having an interface unit that connects the CPU and peripheral devices. and an I/O board mounted with the CPU, the memory, and the I/O circuit are connected to each other by an address bus, a data bus, and a control bus via a gate circuit in the CPU board. In the system, a connection signal generation unit is mounted on the I/O board and provides a ground signal when connecting to a connection path with the CPU board; and a connection signal generator is mounted on the CPU board and provides a ground signal from the I/O board. a signal holding circuit that holds the rising edge of the signal and sends it as a connection holding signal and sends an input/output prohibition signal to the gate circuit; a selector circuit that selects the connection path of the I/O board to be accessed according to the /O address and transfers and outputs the connection holding signal received from the connection path as an operation prohibition signal; , starts time measurement when a connection request is made to the I/O board, and outputs a time limit exceeded signal to an interrupt signal input terminal and an operation permission signal input terminal of the CPU after a predetermined time period has elapsed;
Further, a timer circuit is provided that prohibits the time-limited measurement while receiving the operation prohibition signal from the selector circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, a CPU board 10 equipped with a CPU 11 and an I/O board 20 equipped with an I/O circuit 21 having an interface with peripheral devices and a connection signal generator 22 are mounted on the CPU board 10. They are connected via an address bus 31, a data bus 32, a control bus 33, and a connection path 34 via a gate circuit 16. Note that the CPU board 10 includes a memory 12, a selector circuit 13, a signal holding circuit 15, and a timer circuit 14 in addition to the CPU 11. The I/O circuit 21 mounted on the I/O board 20 connects the CPU 11 and memory 12 with an address bus 31, a data bus 32, and a control bus 3.
3, and the connection signal generating section 22 is connected to the selector circuit 13 via the signal holding circuit 15 through a connection path 34. The signal holding circuit 15 sets the connection holding signal 43 to a high level when the connection path 34 changes from earth (low level) to power supply +Vcc (high level), and sets it to a low level in response to a reset request 46 from the CPU 11. .

When the selector circuit 13 receives both the I/O request signal 41 from the control bus 33 and the I/O address from the address bus 31, the selector circuit 13 maintains the connection from the connection path 34 corresponding to the I/O address. A signal 43 is output to the timer circuit 14. The output terminal of the timer circuit 14 is connected to the operation permission signal input terminal (READY) and the interrupt request signal input terminal (INT) of the CPU 11.

The connection path 34 is connected to the power supply +Vcc within the CPU board 10 via a resistor, and is also connected to the ground at the connection signal generating section 22 within the I/O board 20. Therefore, when the I/O board 20 is connected, the selector circuit 13 receives the air (low level) of the I/O board 20 from the connection path 34 via the signal holding circuit 15, so it is sent to the timer circuit 14. An operation prohibition signal 44 is sent to prohibit the timer circuit 14 from measuring time. On the other hand, I
When the /O board 20 is not connected, the selector circuit 13 is connected to the power supply +Vcc (high level).
There is no prohibition on the operation of the timer circuit 14.

When the timer circuit 14 receives the I/O request signal 41 from the control bus 33, it normally starts counting time for a time limit, and when a predetermined time limit has elapsed, sends a time limit exceeded signal 45 to the C bus.
It is output to the operation permission signal input terminal (READY) and interrupt signal input terminal (INT) of the PU11. Further, when the timer circuit 14 receives the connection confirmation signal 42 from the control bus 33, it stops counting time and restores the time value to zero. On the other hand, while receiving the operation prohibition signal 44 from the selector circuit 13, the timer circuit 14 does not perform a timing operation even if it receives the I/O request signal 41.

Next, the operational procedure during I/O access in this embodiment will be explained.

[0012] CPU board 10 and one I/O board 2
In order to transfer data between
Outputs the I/O address assigned to the corresponding I/O board 20 to the address bus 31, and outputs the I/O address to the control bus 33.
It outputs the O request signal 41 and stops the internal processing.

[0013] The I/O circuit 21 of the I/O board 20
When the /O request signal 41 is received, the I/O is sent from the address bus 31.
The O address is read, and if the address corresponds to the address given to the own board, access processing to the external interface of the I/O circuit 21 is started. After this, I/O circuit 2
1 outputs a connection confirmation signal 42 when data transfer with the CPU 11 becomes possible.

When the CPU 11 of the CPU board 10 detects this connection confirmation signal 42 from the control bus 33, the CPU 11
11 is restarted, and data transfer with the I/O circuit 21 is performed.

First, the CPU board 10 and the I
When the I/O board 20 is connected to the I/O board 20 by a bus, the connection path 34 to the selector circuit 13 is connected to the ground at the access destination I/O board 20, and is therefore at a low level. The CPU 11 outputs an I/O address to the address bus 31 and an I/O request signal 41 to the control bus 33 for the I/O circuit 21 to be accessed. The connection path 34 connected to the I/O board 20 is selected according to the address and the I/O request signal 41. The selected connection path 34 is directly connected to the timer circuit 14 by the selector circuit 13 via the signal holding circuit 15. Therefore, timer circuit 1
4 is ground air (low level) from the connected I/O board 20
Upon receiving the operation prohibition signal 44, the timekeeping operation is prohibited.

Next, the CPU board 10 and the I/O
When the O-board 20 is off the bus, the connection 34 to the selector circuit 13 is at a high level. C.P.
U11 provides I/O to the I/O circuit 21 to be accessed.
Outputs the address to address bus 31 and controls bus 3
At the same time, the selector circuit 13 outputs the I/O request signal 41 to the I/O board 20 in response to the I/O address and the I/O request signal 41.
Select. The selected connection path 34 is connected to the selector circuit 1
3, it is directly connected to the timer circuit 14 as it is. Therefore, the timer circuit 14 receives the high level on the connection path 34 and the timekeeping operation is enabled. The timer circuit 14 is
When the operation is enabled, the I/O request signal 4 of the control bus 33 is activated.
1 is detected, and after a certain period of time has elapsed since time measurement started, the time limit exceeded signal 45 is sent to the operation permission signal input terminal (RE) of the CPU 11.
ADY) and an interrupt signal input terminal (INT). The CPU 11 receives a connection confirmation signal 42 from the control bus 33.
Instead of the timeout signal 45 from the timer circuit 14
is received, the internal processing is restarted, and the CPU board 10
and data transfer between the I/O boards 20. Also, C
The PU 11 transmits the time limit exceeded signal 45 to an interrupt signal input terminal (
INT) and recognizes that the I/O board 20 to be accessed is disconnected from the bus.

Note that when the I/O board 20 that has been disconnected from the bus is reconnected, a malfunction may occur unless initial control is performed from the CPU 11. Therefore, if the connection hold signal 43 becomes high level, The gate circuit 16 is closed (input/output prohibition signal 47), and the I/O request signal 41 is not sent. When the connection holding signal 43 becomes high level, after performing initial control of the I/O board 20, the CPU 11 issues a reset request 46 and sets it to low level.

FIG. 2 is a block diagram of a second embodiment of the invention. The only difference from the first embodiment (see FIG. 1) is the operation of the signal holding circuit 25.

The signal holding circuit 25 has a connecting path 34 connected to the ground (
When the connection holding signal 43 changes from (low level) to power supply +Vcc (high level), the connection holding signal 43 is set to a high level, and is set to a low level in response to a reset request 4b from the CPU 11. Further, the signal holding circuit 25 has an address bus 31, a data bus 32,
The connection state of the I/O board 20 to be accessed can be referenced via the control bus 33.

When an interrupt request is generated by the time limit exceeded signal 45, the CPU 11 connects the signal holding circuit 25 to the I/O board 20 to be accessed via the address bus 31, data bus 32, and control bus 33. When it is detected that the I/O board 20 is present, the I/O board 20 is initially controlled, and then a reset request 46 is issued and the connection holding signal 43 is set to a low level.

[0021]

[Effects of the Invention] As explained above, according to the present invention, I
Even if the /O board is disconnected and the connection confirmation signal is not sent back to the CPU board, the timer circuit in the CPU board can output a time over signal instead of the connection confirmation signal to prevent the I/O board from being disconnected. It is possible to prevent the internal processing of the CPU from being stopped forever.

[0022] Furthermore, when a disconnected I/O board is reconnected, it is recognized that the I/O board has been connected, and the I/O board is reconnected.
It is also possible to initialize the O board and restart the input/output processing of the accessed I/O board without stopping the CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention.

FIG. 2 is a block diagram of an embodiment of the invention.

[Explanation of symbols]

10 CPU board 11 CPU 12 Memory 13 Selector circuit 14 Timer circuit 15, 25 Signal holding circuit 16 Gate circuit 20 I/O board 21 I/O circuit 22 Connection signal generation section 31 Address bus 32 Data bus 33 Control bus 34 Connection path 41 I/O request signal 42 Connection confirmation signal 43 Connection hold signal 44 Operation prohibition signal 45 Time limit exceeded signal 46 Reset request 47 Input/output prohibition signal

Claims (2)

[Claims] Claim 1: A CPU board equipped with a central processing unit (CPU) and a memory, and an I/O board equipped with an input/output (I/O) circuit having an interface section for coupling the CPU and peripheral devices. and in a microcomputer system in which the CPU, the memory, and the I/O circuit are connected by an address bus, a data bus, and a control bus via a gate circuit in the CPU board, the CPU is mounted on the I/O board. and a connection signal generating unit that provides a ground signal when connecting to the connection path with the CPU board, and a connection signal generation unit that is mounted on the CPU board and holds the rising edge of the ground signal given from the I/O board and sends it out as a connection holding signal. and a signal holding circuit that sends an input/output prohibition signal to the gate circuit; a selector circuit that selects the connection path of the I/O board and transfers and outputs the connection holding signal received from the connection path as an operation prohibition signal; and a selector circuit that is mounted on the CPU board and requests connection to the I/O board. When the time limit measurement is started, and after a predetermined time limit has elapsed, a time limit exceeded signal is output to the interrupt signal input terminal and the operation permission signal input terminal of the CPU, and while the operation prohibition signal is being received from the selector circuit, the time limit measurement is started. A microcomputer system characterized by comprising a timer circuit for inhibiting. 2. The signal holding circuit is connected to the address bus, the data bus, and the control bus, and when each bus is connected to the I/O board to be accessed, the signal holding circuit transmits the signal to the CPU. Applicable I when the time limit exceeded signal is input
2. The microcomputer system according to claim 1, wherein the microcomputer system performs initial control of the /O board.