JPH04316310A - Manufacture of semiconductor device concerned with lithography processing - Google Patents

Abstract

PURPOSE:To see that the tendency of the thickening/thinning depending upon the circumstances where its pattern is arranged does not appear in formation, etc., of a pattern by exposing the photosensitive film being applied in the substrate face region in and around a chip arranged region and then, developing it. CONSTITUTION:A photosensitive film is applied on the surface of a semiconductor substrate 1, and exposure treatment for transcribing the specified pattern, wherein a semiconductor device formation chip is a unit, on the photosensitive film is performed. In such a case, to the surplus region where one part of the pattern 2 lacks in case that it is the substrate face region in and around the chip arrangement region and that the same pattern as the chip is arranged under the situation that the chip where a semiconductor device is made is arranged at the surface of the substrate 1, the photosensitive film applied in the surplus region is exposed partially, and then the development concerned with the exposure for transcription of the said pattern 2 is performed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to lithography processing using a photosensitive resist, and particularly to lithography processing that involves pattern deformation during development processing during resist pattern formation.

Photolithography is used to form integrated circuits on semiconductor substrates such as Si wafers, and ultraviolet g-line and i-line are used as light sources especially when forming fine patterns. Soft X-rays and electron beams are also used.

Dimensional changes in resist patterns formed by such lithography have been a problem when there is a common tendency across the entire substrate to thicken or thin. In the case of non-uniform occurrence within the substrate surface, the extent of the occurrence is relatively small, and so it has rarely been taken up in the past.

However, in recent years, as integrated circuits have become more highly integrated and patterns have become finer, the 1μ rule in pattern design is shifting to the 0.5μ rule, and even more so in the near future.
In a situation where a transition to the 5μ rule is considered inevitable, variations in pattern dimension changes within the substrate have become impossible to ignore.

[0005] Variations in pattern dimension changes within this substrate have the following tendency. First, if there is a sparse/dense bias in the pattern distribution within a chip, the patterns in the sparse portions become larger than those in the dense portions. Here, the term "pattern distribution is dense" refers to a state in which the ratio of the pattern area to the substrate area is large, and when patterns with the same line width are arranged, the portion where the patterns are densely distributed is dense. On the contrary, the distance between the patterns is relatively large,
Parts that exist in isolation are sparse.

Second, when comparing corresponding patterns of different chips, the pattern of the chip at the periphery of the substrate tends to be larger than that of the chip at the center. In either case, the degree of enlargement is about 1 to 2% based on the thinner pattern, and although it is not a particular problem with fine patterns of about 1 μm rule, it increases as patterns become finer. Since the leverage ratio increases, it is thought that this will become a problem in the formation of integrated circuits with ultra-fine patterns.

[0007] The above-mentioned tendency is typically seen in the developing devices and processing methods that are currently widely used, and although other devices and processing methods may show the opposite tendency, the present invention is capable of solving either tendency. It is also effective in compensating for The following explanation is related to the above-mentioned tendency, and when the tendency is opposite, it can be similarly understood by reading sparse/dense interchangeably.

[0008]

[Prior Art and Problems to be Solved by the Invention] The tendency and extent of dimensional changes in patterns distributed within a chip are determined by the sparseness/density of the patterns, and are predictable. This can be compensated for by applying a preliminary deformation to the pattern on the mask side that cancels out the amount.

On the other hand, differences in the center/periphery of the wafer are often difficult to compensate for in a similar manner. This is because when forming highly integrated circuits using ultraviolet lithography, a step-and-repeat method using a reticle mask is normally used, which forces all chips placed on the substrate to have the same pattern. That's because you don't get it.

The above is a pattern deformation that occurs when forming a resist pattern, but similar problems also occur when a poly-Si layer or a SiO2 layer is selectively etched using a resist pattern as a mask. For example, when dry etching is performed on poly-Si using a resist pattern as a mask, the poly-Si patterns created under isolated resist patterns or resist patterns around the substrate tend to enlarge compared to patterns under other conditions. It has been found that it has Similar to resist pattern enlargement, opposite trends may be observed due to differences in processing methods and conditions, but since these are all problems that can be solved by the present invention, only typical examples will be discussed below.

[0011] An object of the present invention is to prevent thickening/thickening depending on the environment in which the pattern is placed in forming a resist pattern or patterning a layer to be processed using the resist pattern as a mask.
It is an object of the present invention to provide a processing method that does not cause the tendency of thinning and thinning, and another object of the present invention is to provide a method for manufacturing a semiconductor device composed of ultra-fine patterns by adopting this processing method. That's true.

0012

[Means for Solving the Problems] In order to achieve the above object, in the exposure process included in the present invention, a photosensitive film is applied to the surface of a semiconductor substrate, and a semiconductor device forming chip is coated on the photosensitive film. In a process for transferring a predetermined pattern in units of units, in a situation where a chip on which a semiconductor device is formed is placed on the surface of the substrate, a substrate surface area around the chip placement area, If a pattern identical to the chip is placed, a part of the area of the pattern will be missing, and after exposing the photosensitive film applied to the surplus area, the pattern transfer is performed. Development processing related to exposure processing is performed.

[0013] Further, as an embodiment of the exposure processing for this surplus area, (1) the pattern of the chip is transferred by repeated exposure using a reticle mask, and the transfer exposure using the reticle mask is also performed for the surplus area.
The following processing methods are provided: (1) exposing the substrate surface by masking the chip placement area; and (2) scanningly irradiating ultraviolet light guided by an optical fiber.

[0014]

[Operation] In order to understand the operation and effect of the above-mentioned means adopted in the present invention, it is necessary to understand the cause of the variation in the dimensional change width of the pattern within the substrate. Regarding dimensional changes, next, deformation of a pattern formed by a resist pattern will be explained. Although the present invention is also effective for negative type resists, in the following explanation, unless otherwise specified, the photosensitive characteristics of the resists are positive type.

[0015] Usually, the development of a photosensitive resist is carried out in the steps shown in FIG. First, as shown in FIG. 4A, a developer 14 is adhered to the side of the substrate 11 on which the resist 13 is adhered. The developer is supplied from a nozzle (not shown) above the substrate;
Surface tension holds a significant amount of developer on the substrate. During the elapse of a predetermined period of time, the exposed portion of the resist changes to the same figure (b).
) When the resist is dissolved in a developer and the developer is removed and washed, unexposed portions of the resist remain as shown in (c) of the same figure, forming a resist pattern.

[0016] When the amount of the developer is limited in this way and the developer is not stirred, the chemical properties of the developer change to a significant degree as development progresses, and the extent of the change is limited by the degree of dissolution. The difference will depend on the amount of resist applied. In other words, in areas where the ratio of photosensitive areas is large, a large amount of resist will be dissolved, resulting in a significant change, and if the ratio of photosensitive areas is small, the amount of resist dissolved will be small, resulting in changes in the chemical properties of the developer. It is also small.

[0017] Although some aspects of the actual nature of this change in chemical properties remain unexplained, from a macroscopic perspective, it is a deterioration in the developing ability and a decrease in the dissolution rate of the photosensitive resist. It is. Therefore, in areas where the ratio of photosensitive areas is large (areas where the pattern is dense), the pattern thinning is slower than in areas where the ratio of photosensitive areas is small (areas where the pattern is sparse), and relatively speaking, An enlarged pattern will appear.

Next, a situation will be described in which, even when patterning a poly-Si layer or the like using a resist pattern as a mask, enlargement occurs in areas where the pattern is sparse. When performing this patterning process by dry etching such as RIE, in order to clearly realize etching anisotropy, a film of deposits adheres to the side walls of the recesses created by removing the material to be etched, and Although it is necessary to create a situation that suppresses etching, deposits often adhere to the sidewalls in areas where the pattern is sparse. As a result, the pattern becomes larger in sparse areas than in dense areas.

[0019] As described above, when focusing on one resist pattern, whether pattern enlargement occurs or not depends on whether or not other patterns exist in close proximity. In order to make the dimensional changes uniform, it is sufficient to prevent extreme spacing and density in the pattern arrangement.

When considering the situation of patterns actually placed on Si wafers etc. from this point of view, chips with the same pattern are adjacent to each other in the center of the wafer, so the density and density within the chips is All other conditions can be said to be the same. However, for chips placed in the outermost row, if the resist is positive, there is an area outside where the resist remains on the entire surface, and from the perspective of pattern density, it is extremely dense. It will be placed. On the other hand, in the case of a negative resist, all of the outer resist is removed, resulting in an extremely sparse state.

[0021] The present invention allows chips at the center of the wafer and chips at the outer periphery to be placed in the same environment by eliminating external factors that cause such a situation. Now, let us consider the area of unexposed resist left on the wafer periphery during normal processing. As shown in FIG. 4, when a plurality of chip regions 12 are arranged on a substrate 11, an unused surplus region is generated around the chip region, and the unexposed resist left in this region creates a pattern-dense environment for adjacent chips. will be created.

[0022] When we divide these surplus areas and examine the strength of their effects, it is clear that the areas adjacent to the chip area in two directions have a strong influence on increasing the pattern density. It is. If you place the chip in this part, as shown by position A in the figure, a part of it will be chipped, but 1/2
Two or more parts will rest on the substrate.

Next, regarding the area adjacent to the chip in only one direction, as shown in position B in the figure, even the area where a considerable part of the chip is missing is a unified area by being continuous in the horizontal direction. It can be said that those occupying a large area have a large influence in terms of increasing pattern density. Furthermore, a region like position C, which is equivalent to position B when the pattern is rotated, is also a part that has a similar influence.

According to the present invention, during the exposure process for pattern transfer to the resist, this type of surplus area is also selectively exposed, and while a part of the resist is removed by the development process, an appropriate amount of the resist is removed. If the resist is left behind, the resist left on the periphery of the wafer will place the chips on the periphery in the same environment as the chips in the center, suppressing pattern enlargement. . In particular, if selective removal of the resist is carried out with emphasis on the portions that are most affected as described above, a greater effect can be achieved with fewer steps.

[0025]

Embodiment FIG. 1 is a diagram schematically showing a first embodiment corresponding to claim 2. In the figure, 1 is a semiconductor substrate, and 2 is a chip pattern.

In this embodiment, the same pattern is transferred outside the regular chip area, and pseudo chips 3a to 3d are arranged. 3a corresponds to position A in FIG. 4, and 3b corresponds to position B. 3c and 3d are those in which a plurality of chips are arranged instead of rotating the pattern as in position C in FIG. Pattern transfer in the chip area is performed by step-and-repeat, but placement of pseudo chips is performed by increasing the number of pattern transfer repeat points.

If a pattern including a pseudo chip is transferred in this way, the pattern density environment of the outermost regular chip will be similar to that of the center chip, and the change in pattern dimension between the chips will be The differences will be resolved.

FIG. 2 is a diagram schematically showing a second embodiment corresponding to claim 3. In the figure, 1 is a semiconductor substrate, the surface of which is coated with a photosensitive resist, and a chip pattern is transferred thereto. As shown in the figure, a mask is prepared which has a light shielding pattern 4a covering the chip area of this substrate and a pattern 4b for selectively exposing the peripheral area. pattern 4
The symbol a is filled, and the pattern 4b is, for example, a striped pattern at predetermined intervals.

When this mask is placed on the substrate as shown in the figure and the entire surface is exposed to ultraviolet light, the resist around the chip area is partially exposed and removed by development. Therefore, in this case as well, the pattern density environment of the outermost regular chip is similar to that of the central chip.

FIG. 3 is a diagram schematically showing a third embodiment corresponding to claim 4. Here, the exposure process for the surplus area is performed by exposing the surplus area to ultraviolet light guided by the optical fiber 5 in a scanning manner. In this case, it will be explained that the same effects as in each of the above embodiments can be achieved by appropriately selecting the scanning pitch so that the density of the remaining resist is similar to that in the chip area. It's obvious. In this figure as well, 1 is the semiconductor substrate, 2
is the chip pattern.

When carrying out the present invention, it is not possible to visually distinguish between the chip area to which the regular pattern has been transferred and the surplus area at the periphery, so in the second and third embodiments, the surplus area Positioning for exposure depends on the mechanical precision of the exposure device. In step-and-repeat type exposure apparatuses in practical use today, position control is performed with an accuracy of about ±30 μm, and this level of alignment accuracy is sufficient for the present invention.

[0032]

[Effects of the Invention] As explained above, in the present invention, since the excess area surrounding the area where the chip is placed is exposed to light, the resist in this area is removed during development in the same way as in the case of negative resist. This avoids spurious pattern overcrowding. As a result, during development processing or dry etching using the resist pattern as a mask, pattern enlargement does not occur within the chip disposed around the chip area.

[Brief explanation of drawings]

[Figure 1] Diagram schematically showing the first embodiment

[Figure 2]
A diagram schematically showing the second embodiment

[Figure 3] Diagram schematically showing the third embodiment

[Figure 4] Diagram explaining surplus area

[Figure 5] Schematic cross-sectional diagram showing the resist development process

[Explanation of symbols]

1 Semiconductor substrate 2 Chip patterns 3a, 3b, 3c, 3d Pseudo chips 4a, 4b
Light-shielding pattern 5 Optical fiber 11 Substrate 12 Chip area 13 Resist film 13' Resist pattern 14 Developer

Claims (4)

[Claims] 1. In an exposure process for applying a photosensitive film to the surface of a semiconductor substrate and transferring a predetermined pattern in units of semiconductor device forming chips to the photosensitive film, a semiconductor device is formed on the surface of the substrate. Under the condition where the chip to be formed is placed, the area on the substrate surface around the chip placement area, where if the same pattern as the chip is placed, a part of the pattern will be missing. In contrast, a method for manufacturing a semiconductor device, which comprises partially exposing the photosensitive film applied to the surplus area, and then performing a development process related to the exposure process for pattern transfer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the pattern of the chip is transferred by repeated exposure using a reticle mask, and the transfer exposure using the reticle mask is also performed on the surplus area. A method for manufacturing a semiconductor device, characterized by: 3. The method of manufacturing a semiconductor device according to claim 1, wherein the exposure process for the surplus area includes completely blocking light to the chip placement area and selectively blocking light to the surplus area. A method for manufacturing a semiconductor device, characterized in that the substrate surface is exposed to light using a mask. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the exposure process for the surplus area is performed by scanningly irradiating the excess area with ultraviolet light guided by an optical fiber. A method for manufacturing a semiconductor device.