JPH04314261A - Gradation control circuit and printer - Google Patents

Abstract

PURPOSE:To decrease the time required for gradation print. CONSTITUTION:A gradation memory 53 to store a gradation data corresponding to N-sets of drive elements is provided and each of gradation data outputted from the gradation memory 53 is sequentially latched to plural 1st latch circuits 54-57. After the data is latched to all of the 1st latch circuits 54-57, each data in the 1st latch circuits 54-57 is inputted transmission to relevant 2nd latch circuits 63-66. Furthermore, a decrement circuit 68 decrementing sequentially each data in the 2nd latch circuits 63-66 in each setting timing is provided and only when each data in the 2nd latch circuits 63-66 is larger than the setting value, a drive element is driven.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation control circuit and a printer.

0002

Conventionally, in an electrophotographic printer, a charged photoreceptor drum is irradiated with a light source to form an electrostatic latent image on its surface, and toner is attached to the electrostatic latent image for development. After that, the toner image is transferred to a recording medium. FIG. 2 is a schematic diagram of a conventional electrophotographic printer.

[0003] In the figure, an electrophotographic printer 1 is composed of a control section 3 that receives print data from a terminal 2, and a printing section 4 that performs printing. The control unit 3 includes an external connection interface unit 5 such as a Centronics interface.
, a reception buffer 6, a microprocessor 7, a font memory 8, an image memory 9, and a printer interface section 10. Print data sent from the terminal 2 is supplied to a reception buffer 6 via an external connection interface section 5.

The printing section 4 is also provided with a printing paper supply section 11 on the right side for automatically supplying standard printing paper. Also, inside the printing unit 4, there are registration rollers 12 that start driving the printing paper from the printing paper supply unit 11, a clutch-driven hopping roller 13 that transports the printing paper to the registration roller 12, and a photosensitive roller on the outer periphery. A photoreceptor drum 14 having a body surface formed thereon, a charger 15 that uniformly charges the surface of the photoreceptor, and an LE that forms an electrostatic latent image corresponding to image data for printing on the surface of the photoreceptor.
A D head 16, a developing device 17, a transfer device 18, a fixing device 19, and a cleaner 24 are provided. A discharge section 20 is provided on the left side of the printing section 4 to discharge the printing paper after printing.

The printing section 4 is also provided with a microprocessor 21 that communicates with the control section 3 and controls the printing section 4 as a whole. Further, between the control section 3 and the printing section 4, there is a bidirectional serial interface 22 for communication between the two, and a bidirectional serial interface 22 for transferring and controlling print data formed of dot image data. They are connected by a video interface 23 having a signal line.

[0006] Here, the serial interface 22
connects the microprocessor 7 and the microprocessor 21 of the printing section 4 via the printer interface section 10 of the control section 3; It is connected to the LED head 16 of section 4.

When print data from a host computer (not shown) is input to the electrophotographic printer 1 having the above configuration via the terminal 2 and the external connection interface section 5, the electrophotographic printer 1 receives the print data into the reception buffer 6. 1 to the receiving buffer 6
When a page's worth of print data is captured, the photoreceptor drum 14 rotates, the surface of the photoreceptor is uniformly charged by the charger 15, and the developer in the developing device 17 is stirred. will be held.

When the preliminary operation is completed, the clutch of the hopping roller 13 is turned on, and the printing paper is taken out from the printing paper supply section 11 and conveyed to the registration rollers 12. On the other hand, the microprocessor 7 reads the character code included in the print data taken into the reception buffer 6, refers to the font memory 8, creates image data for printing, and writes it into the image memory 9. In the image memory 9, image data for printing, for example, one page of printing paper is edited and stored.

Furthermore, when image data is directly sent as print data from a host computer (not shown) and transmitted to the reception buffer 6 via the terminal 2 and the external connection interface section 5, the microprocessor 7 stores it as it is in the image memory. Write to the predetermined address of 9. Further, in the case of business graphic printing, print data is sent from the host computer in the form of graphic commands, so the print data is edited and calculated by the microprocessor 7 and written directly to the image memory 9 as image data.

[0010] When the analysis and editing of the image data for printing is completed in this manner, the printing paper that has reached the registration rollers 12 is conveyed toward the transfer device 18. In parallel with this, image data for printing is supplied by the microprocessor 7 to the LED head 16 via the video interface 23, the LED head 16 is driven, and an electrostatic latent image is formed on the outer periphery of the photoreceptor drum 14. Ru. When the photoreceptor drum 14 rotates in the direction of arrow a in the figure, the electrostatic latent image is developed by the developing device 17 and transferred to the transfer device 1.
At step 8, the image is transferred to printing paper. Thereafter, the printing paper is fixed in the fixing device 19 and is discharged to the discharge section 20. Further, toner remaining on the photosensitive drum 14 after the transfer is removed by a cleaner 24.

[0011] In this way, information based on print data received from the host computer is printed on printing paper. FIG. 3 is a circuit diagram of an LED head of an electrophotographic printer. In the figure, 20 is a shift register circuit (SR
), and stores print data for each line, which is serially input as a DATA signal, in synchronization with a clock pulse input as a CLOCK signal. 21 is a latch circuit (LT) for one line of print data;
Data in the shift register circuit 20 is taken in by a pulse applied as a LOAD signal. 22 is a driver, which is composed of a NAND circuit 23 and a resistor 24;
The output of the latch circuit 21 and STB are connected to the NAND circuit 23.
(strobe) signal is input. Then, when a high level signal is input to the STB signal, the latch circuit 2
The output of the NAND circuit 23 to which the high-level output of 1 is input becomes low level, and current flows to the LED array 25 through the resistor 24, causing the LEDs to emit light.

By the way, the print result obtained by the electrophotographic printer 1 has two values, ie, the color of the printing paper and the color of the toner.
The exposure time is adjusted by the gradation information. That is, in areas where light printing is to be performed, the exposure time by the LED head 16 is shortened to reduce the amount of charge removed from the photoreceptor drum 14, and in areas where dark printing is to be performed, the exposure time is lengthened to reduce the amount of charge removed from the photoreceptor drum 14. Increase the amount of charge removed. Since the amount of toner adhesion during development varies depending on the amount of charge removed from the photoreceptor drum 14, gradation can be expressed based on the density difference in dot units.

FIG. 4 is a block diagram of a gradation control circuit in a conventional electrophotographic printer. In the figure, 16 is L
It is an ED head, and the number of dots in one line in the main scanning direction of printing is N. The shift register circuit 20 is LE
Gradation data corresponding to whether or not the D array 25 is driven is input, and one line's worth of tone data in the main scanning direction is sequentially transferred. Therefore, N flip-flop circuits are provided corresponding to the number N of dots in the main scanning direction. and,
The gradation data transferred to the shift register circuit 20 is latched by the latch circuit 21, and the driver 22
Based on the gradation data latched by the latch circuit 21, the LED array 25 is driven to emit light for only the time the STB signal is turned on.

Further, 31 is a gradation memory (corresponding to the image memory 9 in FIG. 2), which stores N pieces of M-bit gradation data for one line when the maximum number of gradations for printing is 2M. Stored. Reference numeral 32 denotes an N-ary counter, which is provided to know when reading of one line of gray scale data in the gray scale memory 31 is completed. 33 is an M-bit binary counter (hereinafter referred to as "M-bit counter"), which receives the output of the N-ary counter 32 and is decremented every time N dots have been read from the gradation memory 31. Ru. 34 is a comparator for comparing the gradation data read from the gradation memory 31 and the output of the M-bit counter 33; when the gradation data read from the gradation memory 31 is larger than the output of the M-bit counter 33; The output is turned on, and this output is the LED head 1
The signal is input to the shift register circuit 20 in 6.

FIG. 5 is a time chart of signals of a tone control circuit in a conventional electrophotographic printer. As shown in the figure, when the electrophotographic printer 1 prints one line, the light emitting time of the LED array 25 changes depending on the number of gradations, so the driving of the LED array 25, that is, the light emitting operation, is divided by the number of gradations. Ru. Prior to the timing of driving each divided LED, one line of gradation data of the shift register circuit 20 is transferred to the LED head 16. and,
During the time for printing one line, gradation data for N dots are continuously read from the gradation memory 31, and this operation is repeated 2M gradation times. Here, the data string of gradation data read from the gradation memory 31 is the same from the time of the first data transfer/LED drive to the 2Mth data transfer/LED drive.

[0016] Now, when a data string of gradation data consisting of a, b, c, d, . Output '0' of counter 33 (M bit)
The comparison result (1 bit) is compared with the LED head 16.
will be forwarded to. That is, M-bit data strings a, b,
If each value of c, d, ... is '0', LE
Data of '0' is transferred to the D head 16, and if the data is other than '0', data of '1' is transferred to the LED head 16. When the first data transfer to the LED head 16 is completed, the transferred data is latched by the latch circuit 21, and the LED is turned off for a time TS during which the STB signal is output.
Each drive element of array 25 is driven.

During the second data transfer, the M-bit counter 33 is incremented and its output is '
It becomes 1'. Then, the gradation data is read out for the second time, and the data strings a, b, c, d,... are sequentially compared with the output '1' of the M-bit counter 33, and if it is larger than '1', the data string a, b, c, d,... Only the corresponding element of the LED head 16 receives the STB signal and emits light. Similarly, data transfer and L
The ED drive is repeated up to the 2Mth time, and the output of the M bit counter 33 is sequentially incremented to 2, 3, . . . , 2M -1.

As a result, when data 'j' is stored in the gradation memory 31 in the data strings a, b, c, d, . . . of gradation data, the M bit counter 33 is incremented and the output is The output of the comparator 34 corresponding to data 'j' is maintained at '1' until it reaches 'j'. and,
During that time, the driving element of the corresponding dot in the LED head 16 is driven j times for each time TS, and the cumulative driving time is j×
TS (seconds).

FIG. 6 is a diagram showing the relationship between the strobe time of the LED head and the print density. If the accumulation of light emitting time per driving element for one line of printing is defined as strobe time, the print density also increases monotonically in accordance with the strobe time. Since the strobe time and print density do not have a linear relationship, a correction table is provided to correct this, and the gradation data in the gradation memory 31 is corrected in advance.

[0020]

However, in the gradation control circuit and printer having the above configuration, the access time to the gradation memory 31, that is, the cycle of the CLOCK signal is TCLK, the number of dots in the main scanning direction is N, and the number of gradations is If is 2M, the time required to perform gradation printing for one line is theoretically N x TCLK x 2M (seconds) (
In reality, it will be even longer if the time for latching is taken into account. ), and the normal value of the number of dots N is on the order of several thousand, so it takes a long time to perform one line of gradation printing, making it impossible to perform high-speed printing.

The present invention solves the problems of the conventional gradation control circuit and printer described above, and provides a gradation control circuit and printer that can shorten the time required to print one line of gradation. The purpose is to provide.

[0022]

[Means for Solving the Problems] To this end, the gradation control circuit and printer of the present invention include a gradation memory that stores gradation data consisting of N pieces of data corresponding to N driving elements. A plurality of first latch circuits are provided to sequentially latch each piece of grayscale data output from the grayscale memory.

The same number of second latch circuits are provided corresponding to each of the first latch circuits, and after data is latched in all of the first latch circuits, each of the first latch circuits is Data is input into respective second latch circuits. Further, a decrement circuit is provided that sequentially decrements each data in the second latch circuit at each set timing, and the drive element is driven only when each data in the second latch circuit is larger than a set value. It is now possible to do so.

The print head formed by the N driving elements is disposed facing the photosensitive drum and exposes the surface thereof. A charging means for charging the surface of the photosensitive drum, a developing means for developing the exposed surface, a transfer means for transferring the developed toner image onto paper, and a fixing means for fixing the transferred toner image are the photosensitive drums. They are provided opposite to the body drums, respectively.

[0025]

[Operation] According to the present invention, as described above, there is provided a gradation memory that stores gradation data consisting of N pieces of data corresponding to N driving elements, and the gradation data outputted from the gradation memory is Each piece of gradation data is sequentially latched by a plurality of first latch circuits. When all N pieces of data are latched, each piece of data is input into second latch circuits provided corresponding to the first latch circuits.

Each data in the second latch circuit is circulated through a decrement circuit and is sequentially decremented at each set timing. When each of the decremented data decreases to a predetermined value, the driving of the driving element is stopped, and until then, the driving element is driven. The surface of the photoreceptor drum is charged by a charging means, and when the driving element exposes the surface of the photoreceptor drum to light, the surface charge disappears corresponding to the length of the exposure time. Therefore, the surface after exposure is developed, the developed toner image is transferred to paper,
Once fixed, printing corresponding to the gradation data in the gradation memory is performed.

[0027]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an LED driver IC chip in the gradation control circuit of the present invention, FIG. 7 is a diagram showing a truth table of the decrement circuit of the LED driver IC chip, and FIG. 8 is a block diagram of the gradation control circuit of the present invention. It is. In this case, the description will be made assuming that four driving elements are driven by one LED driver IC chip.

In FIG. 8, 51 is an LED driver IC.
K LED driver IC chips 51 are connected to form an LED head 52. A gradation memory 53 is connected to the LED head 52 and stores gradation data. The gradation data has a number of dots N
The gradation data of each data string has an M-bit configuration.

Next, the LED driver IC chip 51 will be explained based on FIG. In the figure, 54 to 57 are latch circuits for holding M-bit gradation data and shifting it in parallel, 58 to 61 are selector circuits, and 63 to 66 are outputs from the selector circuits 58 to 61. The receiving latch circuit 68 is a decrement circuit connected between the latch circuit 66 and the selector circuit 58. Further, 69 is a timing control circuit for controlling the timing of each of the latch circuits 54 to 57, 63 to 66 and selector circuits 58 to 61, and 71 to 74 are OR circuits for calculating the logical sum of M-bit gradation data. 75 is the OR circuit 71~
74 is a latch circuit that receives the output, 76 to 79 are AND circuits, and 81 is an LED array.

LED driver IC chip 51 having the above configuration
At this time, the M-bit grayscale data read from the grayscale memory 53 (see FIG. 8) is input to the latch circuit 54. The latch circuit 54 is composed of M flip-flop circuits, and holds gray scale data input from the outside. The output of the latch circuit 54 is input to a latch circuit 55, the output of the latch circuit 55 is input to a latch circuit 56, and the output of the latch circuit 56 is input to a latch circuit 57. In response to the CLOCK signal from the timing control circuit 69, the latch circuits 54 to 57 receive the M signal input from the outside.
Bit gradation data is shifted in parallel. Then, N CLOCK signals are sent from the timing control circuit 69.
When the signal is output, all the gradation data constituting the data string of N dots are sent to each LED.
It is held in latch circuits 54 to 57 within the driver IC chip 51.

58 is a selector circuit having two sets of M-bit inputs and one set of M-bit outputs. Also, 59-61
is a similar selector circuit. 63 is a latch circuit for temporarily holding the M-bit output of the selector circuit 58. Similarly, latch circuits 64 to 66 temporarily hold the outputs of selector circuits 59 to 61, respectively. The M-bit output of the final stage latch circuit 66 is
The M-bit output of the decrement circuit 68 is input to the selector circuit 58. The other M-bit inputs of the selector circuits 58-61 are the outputs of the latch circuits 54-57, respectively.

Further, OR circuits 71 to 74 receive M-bit outputs from latch circuits 63 to 66, respectively, take the logical sum of the M-bit gradation data, and output the result to latch circuit 75. In this case, an LED with a width of 4 dots per chip
Since the driver IC chip 51 is taken as an example, the number of bits M of the latch circuit 75 is four. The above latch circuit 7
The four output signals of No. 5 are output to AND circuits 76 to 79, respectively, and the STB signal is input to the other input terminals of the AND circuits 76 to 79. And AND circuit 7
Outputs 6 to 79 drive each drive element of the LED array 81 to light up.

In FIG. 7, the gradation data is 2 bits, and the number of gradations is 22=4. In this case, when '0', '1', '2', and '3' are input to the decrement circuit 68, the outputs are '0', '0', '1', and '2', respectively.
becomes. The numbers in the figure are expressed in hexadecimal. Figure 9
is a circuit diagram of an LED driver IC chip with 22 gradations and 2 dot width.

In the figure, D1 and D0 are signals constituting a data string of gradation data input from the outside,
Signal D1 is MSB (most significant bit), signal D0 is L
SB (least significant bit). On the other hand, the signals D1', D
2' is an output signal to the LED driver IC chip 51 in the next stage, and becomes the signals D1 and D0 in the LED driver IC chip 51 in the next stage.

[0035] d1 and d0 are output from the right end of the diagram,
This is a decrement signal which is circulated and re-inputted to the input part of the left decrement circuit 82, and is the decrement signal d1.
is the MSB, and the decrement signal d0 is the LSB. Q11, Q10, Q21, Q20, q11, q
10, q21, and q20 are flip-flop circuits. Flip-flop circuits Q11 and Q10 constitute a 2-bit latch circuit 83, and flip-flop circuits Q21 and Q20 similarly constitute a latch circuit 84. The latch circuits 83 and 84 constitute a two-bit, two-stage parallel shift register. Also,
The flip-flop circuits q11 and q10 and the flip-flop circuits q21 and q20 similarly constitute 2-bit latch circuits 85 and 86, respectively. Selector circuits 87 and 88 are connected upstream of the input data terminals of the latch circuits 85 and 86, respectively, and one input terminal of the selector circuits 87 and 88 is connected to the output terminals of the latch circuits 83 and 84, respectively. The outputs of the latch circuits 85 and 86 are respectively O.
It passes through R circuits 91 and 92 and is input to latch elements L1 and L2. The outputs of the latch elements L1 and L2 are ANDed with the STB signal and then drive the drive elements 93 and 94 to emit light.

FIG. 10 is a time chart showing the operation when two LED driver IC chips of FIG. 9 are connected. The gradation data Dn is 2-bit data read from the gradation memory 53 (see FIG. 8). The gradation data D
The numbers in n are each data in the data string indicating the gradation, and show how the gradation data Dn changes as the LED head 52 operates. Also, CLK1, CLK2
are each flip-flop circuit q11, q10, q21
, q20, Q11, Q10, Q21, and Q20.

Here, if the data string of the tone data Dn for 4 dots is, for example, 1, 2, 3, 2, then the above CL
When four pulses of the OCK signal CLK2 are generated, each data of the gradation data Dn is input to a parallel shift register constituted by latch circuits 83 and 84 and sequentially transferred at each clock timing. That is, data d0+1 held by flip-flop circuits Q11 and Q10 changes sequentially to 1, 2, 3, 2, and data d0 held by flip-flop circuits Q21 and Q20.
+2, flip-flop circuits Q31 and Q30 (not shown)
The data d0+3 held by the flip-flop circuits Q41 and Q40 (not shown) are also delayed by one clock and are sequentially changed to 1, 2, 3, 2.
and changes. When data transfer for 4 dots is completed, L
A D-P signal is generated and input to selector circuits 87 and 88, thereby flip-flop circuits Q11 and Q1
The data held in 0, Q21, and Q20 are respectively stored in flip-flop circuits q11, q10, q21,
Moved to q20.

That is, the flip-flop circuit q11,
Data d0+1 held by q10, data d held by flip-flop circuits q21 and q20
0+2, flip-flop circuits q31, q3 (not shown)
At this point, data d0+3 held by 0 and data d0+4 held by flip-flop circuits q41 and q40 (not shown) become 2, 3, 2, and 1, respectively.

Next, when the ET signal is turned on and input to the decrement circuit 82, the data held by the flip-flop circuits q21 and q20 at the next clock timing is changed as shown in the truth table of FIG. The converted data becomes data input to flip-flop circuits q11 and q10. The data held in the flip-flop circuits q11 and q10 is transferred to the flip-flop circuit q2 as is.
1, input to q20.

At this time, the flip-flop circuits q11, q
Data d0+1 held by 10, data d0 held by flip-flop circuits q21, q20
+2, data held by flip-flop circuits q31 and q30 d0+3, flip-flop circuit q41
, q40 are now 2, 2, 0, and 2, respectively.

As a result, after two clocks, data d0+
1, d0+2, d0+3, and d0+4 are all updated from the values before the ET signal was turned on, and become decremented values as shown in the truth table of FIG. 7, and the data d0+1, held by flip-flop circuits q11 and q10,
Data d0+2 held by flip-flop circuits q21 and q20, flip-flop circuits q31 and q3
data d0+3 held by 0, data d0+ held by flip-flop circuits q41, q40
4 becomes 1, 2, 1, and 0, respectively.

In this way, the flip-flop circuit q11
, q10, data d0+2 held by flip-flop circuits q21 and q20, data d0+3 held by flip-flop circuits q31 and q30, and flip-flop circuit q.
The data d0+4 held by 41, q40 is 2
Each clock timing is decremented to a value as shown in the truth table of FIG.

[0043]The above flip-flop circuit q11
, q10 and the outputs of flip-flop circuits q21, q20 are passed through OR circuits 91, 92, respectively, and then latched by latch circuits L1, L2, resulting in an output signal d.
0+3 (L3) and d0+4 (L4) are obtained. These output signals d0+1 (L1) to d0+4 (L4) are the data d0+1 held by the flip-flop circuits q11 and q10, and the data d0+1 held by the flip-flop circuits q21 and q20.
data d0+2 held by flip-flop circuits q31, q30, data d0+3 held by flip-flop circuits q31, q30
, the on-time varies depending on the value of data d0+4 held by flip-flop circuits q41 and q40, and becomes shorter as each of the data d0+1 to d0+4 is decremented.

That is, the output signals d0+1(L1) to d
0+4 (L4) has a pulse width corresponding to the data strings 1, 2, 3, 2 of the input gradation data Dn, and this output signal d0+1 (L1) to d0+4
By driving the LED elements 93 and 94 using (L4), gradation printing becomes possible. In the above example,
While the output signals d0+1 (L1) to d0+4 (L4) are turned on and the drive elements 93 and 94 emit light to execute gradation printing, the data strings 2, 2, and 2 for the next print line are
Gradation data Dn consisting of 3, 2, 1 is input,
Each data is sequentially transferred to the flip-flop circuit Q11.
, Q10, Q21, Q20, Q31, Q30, Q41
, Q40. These data are LD-
Until the P signal is input, the flip-flop circuit q11
, q10, q21, q20, q31, q30, q41
, q40, it does not move and waits.

In this way, during the execution of gradation printing by the light emission of the drive elements 93 and 94, the gradation data D of the next printing line is
n inputs can be made in parallel. Assuming that the number of dots in the main scanning direction of the LED head 52 is N, the time required for gradation printing for one line in the example of FIG. 10 is CLOC.
When the period of the K signal is TCLK, the time required to latch the gradation data for N dots into the latch circuits 83 and 84 in all the LED driver IC chips 51 is N×T.
It is given by CLK. Considering that the number of gradations is 22 and 2 clocks are required to decrement one gradation number, if N×TCLK > 22 × 2× TCLK, then if N×TCLK (seconds) This is a good thing, and gradation printing can be completed in a shorter time than when using conventional gradation control circuits and printers.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0047]

According to the present invention, as described above, there is provided a gradation memory that stores gradation data consisting of N data corresponding to N drive elements, and the output from the gradation memory is Each piece of gray scale data is sequentially latched by a plurality of first latch circuits. When all N data are latched, each data is input into second latch circuits provided corresponding to the first latch circuits.

Each data in the second latch circuit is circulated through a decrement circuit and is sequentially decremented at each set timing. When each of the decremented data decreases to a predetermined value, the driving of the driving element is stopped, and until then, the driving element is driven. The surface of the photoreceptor drum is charged by a charging means, and when the driving element exposes the surface of the photoreceptor drum to light, the surface charge disappears corresponding to the length of the exposure time. Therefore, the surface after exposure is developed, the developed toner image is transferred to paper,
Once fixed, printing corresponding to the gradation data in the gradation memory is performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an LED driver IC chip in a gradation control circuit of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional electrophotographic printer.

FIG. 3 is a circuit diagram of an LED head of an electrophotographic printer.

FIG. 4 is a block diagram of a gradation control circuit in a conventional electrophotographic printer.

FIG. 5 is a time chart of signals of a tone control circuit in a conventional electrophotographic printer.

FIG. 6 is a diagram showing the relationship between strobe time and print density of the LED head.

FIG. 7 is a diagram showing a truth table of a decrement circuit of an LED driver IC chip.

FIG. 8 is a block diagram of a gradation control circuit of the present invention.

FIG. 9 is a circuit diagram of an LED driver IC chip with 22 gradations and 2 dot width.

10 is a time chart showing the operation when two LED driver IC chips of FIG. 9 are connected; FIG.

[Explanation of symbols] 51 LED driver IC chip 53
Gradation memory 54-57 Latch circuit (first latch circuit) 58-
61 Selector circuits 63 to 66 Latch circuit (second latch circuit) 68
Decrement circuit 69
Timing control circuits 71 to 74 OR circuit 75 Latch circuits 76 to 79 AND circuit 81 LED array

Claims (2)

[Claims] 1. (a) a gradation memory that stores gradation data consisting of N pieces of data, and (b) a plurality of gradation memory cells that sequentially latch each of the gradation data output from the gradation memory. (c) second latch circuits provided in the same number corresponding to the first latch circuits, and (d) after data is latched in all of the first latch circuits. , means for inputting each data in the first latch circuit into the corresponding second latch circuit,
(e) a decrement circuit that sequentially decrements each data in the second latch circuit at each set timing;
f) A gradation control circuit characterized in that it has means for driving a driving element only when each data in the second latch circuit is larger than a set value. 2. A print head in which N drive elements are arranged in a line forms an electrostatic latent image by exposing the surface of the charged photosensitive drum, and the electrostatic latent image is developed by a developing device. In a printer that generates a toner image, transfers the toner image onto paper using a transfer device, and further fixes the toner image using a fixing device, (a) a gradation memory that stores gradation data consisting of N pieces of data; and (b) the gradation (c) a plurality of first latch circuits that sequentially latch each piece of tone data output from the tone memory; and (c) second latch circuits provided in the same number corresponding to each of the first latch circuits. and (d
) means for inputting each data in the first latch circuit into the respective corresponding second latch circuits after the data is latched in all of the first latch circuits; It has a decrement circuit that sequentially decrements each data in the latch circuit at each set timing, and (f) means for driving the drive element only when each data in the second latch circuit is larger than a set value. A printer featuring