JPH04313274A - Thin-film memory cell and its manufacture - Google Patents

Abstract

PURPOSE:To reduce leak current of a transistor for selection and at the same improve time a drain withstand voltage and then reduce a write/erasure time of a transistor for memory by forming a gate electrode constituting the transistor for memory and a source/drain region at a mutually overlapping position. CONSTITUTION:A semiconductor layer 22 such as polysilicon is formed on an insulation substrate 21 and n<+> high-concentration regions 231, 232, 233, 234 and n<-> low-concentration regions 241, 242, 243, 244 are formed on this semiconductor layer 22. A gate electrode 26 of a transistor for memory MTR is formed on an area between the n<+> high-concentration regions 232 and 233 through an insulation layer 25 and the gate electrode 26 and the n<-> high-concentration regions 232, 233 are overlapped greatly. Gate electrodes 281 and 282 of transistors for selection STR1, 2 are formed on areas between the n<-> low- concentration regions 241 and 242 and between regions 243 and 244 through an insulation layer 27 and then the n<-> low-concentration regions 241, 242, 243, 244 are formed in self-aligned manner with the gate electrodes 281 and 282.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film memory cell comprising a memory transistor and a selection transistor, and a method for manufacturing the thin film memory cell.

0002

[Prior Art] EEPROM is a MO with a structure in which electric charge can be stored in a gate insulating film using an electrical method.
This is a PROM that uses S transistors as memory cells, and charges can be erased electrically.

[0003] Conventional EEPROMs include EEPROMs using single-crystal silicon wafers. That is, EEP
In a memory element used in a ROM, a P well is formed in a silicon wafer, and a source diffusion layer in an n+ high concentration region and a drain diffusion layer in an n+ high concentration region are formed in this P well. A gate electrode is formed between the source diffusion layer and the drain diffusion layer via a SiO2 layer and a Si3 N4 layer. Note that a memory using a TFT in which a silicon amorphous semiconductor layer is formed on an insulating substrate is being considered.

0004

However, EEPROMs using silicon wafers have the disadvantage that they are limited to silicon wafers and are affected by lattice defects. Also,
By isolating each transistor in a TFT, the steps required to form an element isolation structure can be omitted, resulting in a cost advantage.
There is no advantage in forming a P-well, which is a common electrode, for element isolation. Also, TFT
In the memory using the silicon amorphous, the drain current Id due to the intrinsic nature of the silicon amorphous is small, making it unsuitable for large capacity and high integration.

The present invention has been made in view of the above-mentioned circumstances, and it is possible to reduce the leakage current of the selection transistor, improve the drain breakdown voltage, and shorten the write/erase time of the memory transistor, thereby increasing the capacity. It is an object of the present invention to provide a thin film memory cell and a method for manufacturing the thin film memory cell that are suitable for high integration.

[0006]

[Means for Solving the Problems] In order to solve the above problems, the present invention forms a gate electrode and a source/drain region constituting a memory transistor at positions that overlap each other, and a drain region of a selection transistor is formed at a high height. LDD (Light) consisting of a concentrated impurity region and a low concentration impurity region
ly Doped Drain) structure, and the high concentration impurity region is formed by self-alignment at a position that does not overlap with the gate electrode of the selection transistor.

[0007]

[Operation] By forming the gate electrode and the source/drain regions that make up the memory transistor in positions that overlap with each other, electron-hole pairs are efficiently generated and injected into the gate insulating film, resulting in electrical Write/erase time can be reduced. And the drain region of the selection transistor is an LD consisting of a high concentration impurity region and a low concentration impurity region.
By forming the D structure, drain breakdown voltage can be improved. Furthermore, leakage current can be reduced by forming the selection transistor at a position where the gate electrode and the high concentration impurity region of the drain region do not overlap.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional view of a memory cell according to the invention. For example, a semiconductor layer 22 such as polysilicon is formed on an insulating substrate 21 such as glass, and this semiconductor layer 22 includes n+ high concentration regions 231, 232, 233, 234 and
- Low concentration regions 241, 242, 243, 244 are formed. A gate electrode 26 of a memory transistor MTR made of Al or the like is interposed between the n+ high concentration regions 232 and 233 via a second insulating layer 25 of silicon nitride or the like.
is formed. The insulating layer 25 is made of silicon nitride SiN with a Si/N ratio higher than the stoichiometric ratio of 0.75, for example, and can capture and release electrons and holes by hot electrons and the Fowler-Nordheim effect. It is something that can be done. This insulating layer 25 may have a two-layer structure of a SiO2 thin film and Si3 N4. in this case,
Memory transistor MTR has gate electrode 26 and n+
The high concentration regions 232 and 233 are formed to have a large overlap to provide a large capacity. Said n- low concentration region 2
A gate electrode 281 made of polysilicon or the like of the selection transistor STR1 is formed between the n- low concentration regions 243 and 242 via a first insulating layer 27 made of SiO2 or the like. For example, S
A gate electrode 282 made of polysilicon or the like of the selection transistor STR is formed via the first insulating layer 27 made of iO2 or the like. In this case, n- low concentration region 24
1, 242 is formed in self-alignment with the gate electrode 281 of the selection transistor STR1, and is formed to have a sufficiently small capacitance so that it can be ignored. In addition, the n- low concentration regions 243 and 244 are also connected to the selection transistor STR2.
The capacitance is formed in self-alignment with the gate electrode 282, and the capacitance is made sufficiently small to be negligible. The first insulating layer 27 is formed to cover the entire structure. Said n
A source electrode 30 made of, for example, Al is connected to and formed in the + high concentration region 231, and the n+ high concentration region 2
A drain electrode 31 made of, for example, Al is connected to and formed at 34 . A method for manufacturing the thin film memory cell shown in FIG. 1 will be described.

For example, plasma C is applied to the entire surface of the insulating substrate 21.
By depositing polysilicon by VD or the like and separating the elements by etching, an island-shaped semiconductor layer 22 as shown in FIG. 1 is formed. Next, although not shown, the entire upper surface of the semiconductor layer 22 is covered with a photoresist, and openings are formed in the portions of the semiconductor layer 22 facing the n+ high concentration regions 231, 232, 233, and 234 using photolithography. Donor impurities such as P ions are doped through the opening.

Next, an insulating film 25 is formed by low pressure CVD or the like, and then the gate electrode 26 of the memory transistor MTR and the gate electrodes 281 and 282 of the selection transistors STR1 and STR2 are formed. This method is self-evident to those with specialized technical knowledge, so a description thereof will be omitted. However, the insulating layer 27, which is shown as one layer in FIG. 1, is formed in two steps in the actual manufacturing process, and is formed before forming the gate electrodes 281 and 282.

After this, n- low concentration regions 241, 242
, 243, 244 are doped with donor impurities. In this case, it is efficient if the gate electrodes 26, 281, and 282 are doped at the same time. Also, n-
Ion plantation to the low concentration regions 241, 242, 243, and 244 is more preferably carried out by self-alignment using the gate electrodes 281, 282 as masks, since accuracy can be ensured and work efficiency can be improved.

Thereafter, the donor impurities doped into the n+ high concentration regions 231, 232, 233, 234 and the n− low concentration regions 241, 242, 243, 244 are diffused by annealing, and the portions where the insulating layer 27 is not formed are The thin film memory cell shown in FIG. is completed. Therefore, in this thin film transistor, the source region 232 of the memory transistor MTR is also used as the drain electrode 232 of the selection transistor STR1, and the drain electrode 33 of the memory transistor MTR is also used as the source region of the selection transistor STR2. There is.

The memory transistor MTR is composed of a MOS transistor having hysteresis characteristics as shown in FIG. That is, in the write state, electrons are captured in the insulating layer 25 between the gate electrode 26 and the channel region, and the memory gate voltage VMG-drain current Id characteristic exhibits an enhancement type, and in the erase state, holes are injected into the insulating layer 25. This shows depression-type characteristics. That is, once the memory gate voltage VMG is set to Vp, the write state is maintained, and the memory gate voltage VM
Once G is set to -Vp, it has a non-volatile characteristic that maintains the erased state.

Furthermore, the gate electrode 26 and source/drain regions (n+
By forming the high-concentration regions 232, 233) at mutually overlapping positions, electron-hole pairs are efficiently generated, and hot electrons are injected into the gate insulating film 25 during writing when +Vp is applied to the gate electrode 26. Also, during erasing by applying -Vp to the gate electrode 26, holes are efficiently injected into the gate insulating film 25.

In addition, in the case of an n-channel selection transistor whose semiconductor layer is made of polysilicon, if there is an overlap between the selection gate electrode and the drain region, electron-hole pairs that are easily generated due to this overlap are As shown in FIG. 3A, the leakage current increases when the selection gate voltage VCG<0 due to the action of the holes. In addition, the drain region (n+ high concentration region 232, 234) is connected to the selection transistor STR.
1. When formed by self-alignment with the gate electrodes 281 and 282 of STR2, the characteristics shown in FIG. can. However, in an EEP ROM, a high electric field is applied to the drain region (n+ high concentration regions 232, 234), so reducing this leakage current is especially important. , STR2 has an LDD structure as shown in Figure 3.
As shown in C, the effect of further reducing leakage current was confirmed.

FIG. 2(a) is a circuit diagram of the memory cell shown in FIG. The source electrode 30 is the selection transistor STR1
The drain (n+ high concentration region 232) of this selection transistor STR1 is connected to the source (n+ high concentration region 231) of the memory transistor MTR
+ connected to the high concentration region 232). The drain of this memory transistor MTR (n+ high concentration region 233
) is connected to the source (n+ high concentration region 233) of the selection transistor STR2, and this selection transistor S
The drain of TR2 (n+ high concentration region 234) is connected to the drain electrode 31. The memory transistor M
A gate electrode 26 is provided in TR, a gate electrode 281 is provided in the selection transistor STR1, and a gate electrode 282 is provided in the selection transistor STR2.

That is, as shown in FIG. 2B, in the case of batch erasing, the memory gate electrode 26 is grounded, the voltage VON is applied to the selection gate electrodes 281 and 282, and the source electrode 30 and drain electrode 31 It is sufficient to apply a voltage Vp to . In this case, the memory gate voltage VMG is -V
p, and holes are trapped in the insulating layer 25, resulting in an erased state.

In the case of selective writing, the memory gate electrode 26
, applying a voltage Vp to the selection gate electrode 281 and the source electrode 30, respectively, and grounding the drain electrode 31,
The selection gate electrode 282 of the memory cell to be selected is set to VON, and the selection gate electrode 282 of the memory cell not selected is set to VO.
It should be FF. In this case, the selection gate electrode 282
When VON is set, the memory gate voltage VMG becomes Vp, electrons are trapped in the insulating layer 25, and a write state is established.

In the case of reading, the memory gate electrode 26 and the source electrode 30 are grounded, the voltage VON is applied to the selection gate electrode 281, the voltage Vd is applied to the drain electrode 31, and the selection gate electrode of the memory cell to be read is applied. 28
2 may be taken as VON. In this case, the selection gate electrode 2
If the selected memory cell is in the erased state by turning on VON 82, the memory transistor MTR is in the on state, so a drain current flows and the state of "0" is read out. On the other hand, in the write state, since the memory transistor MTR is in the off state, no drain current flows and a state of "1" is read. Naturally, the selection gate electrode 282 of a memory cell that is not read is set to VOFF.

[0021]

[Effects of the Invention] As described above, according to the present invention, electron-hole pairs can be efficiently generated by forming the gate electrode and the source/drain regions of a memory transistor at mutually overlapping positions. By injecting it into the gate insulating film, the electrical write/erase time can be shortened. In addition, by forming the drain region of the selection transistor into an LDD structure consisting of a high concentration impurity region and a low concentration impurity region, the drain breakdown voltage can be improved. Furthermore, leakage current can be reduced by forming the selection transistor at a position where the gate electrode and the high concentration impurity region of the drain region do not overlap.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a circuit diagram and an operation explanatory diagram showing the connection state of FIG. 1;

FIG. 3 is a characteristic diagram showing selection gate voltage-drain current characteristics of the selection transistor according to the present invention.

FIG. 4 is a characteristic diagram showing hysteresis characteristics of a memory transistor according to the present invention.

[Explanation of symbols]

21...Insulating substrate, 22...Semiconductor layer, 231-234...n
+ High concentration area, 241 to 244...n- Low concentration area,
25... Second insulating layer, 26... Memory transistor MT
R gate electrode, 27...first insulating layer, 281, 282
...Gate electrode of selection transistor STR, 30...Source electrode, 31...Drain electrode.

Claims (4)

[Claims] 1. A selection transistor is arranged in a memory transistor such that a source region or a drain region of the selection transistor is also used as a drain region or a source region of the memory transistor, and the memory transistor is configured. gate electrodes and source/drain regions are formed at mutually overlapping positions, the drain region of each selection transistor is formed by a high concentration impurity region and a low concentration impurity region, and the high concentration impurity region is formed by a high concentration impurity region of the selection transistor. A thin film memory cell characterized by being formed in a position that does not overlap the gate electrode. 2. The thin film memory cell according to claim 1, wherein a selection transistor is connected in series to each of the source region and drain region of the memory transistor. 3. Impurity ions are implanted into a portion of the semiconductor layer that overlaps with the gate electrode of the memory transistor to form a source/drain region of the memory transistor, and impurity ions are implanted into a portion of the semiconductor layer that does not overlap with the gate electrode of the selection transistor. Ions are implanted to form a source/drain region of a selection transistor made of a high concentration impurity region, and impurity ions are implanted into a semiconductor layer portion on the gate electrode side of the selection transistor adjacent to the source region or drain region of the selection transistor. 1. A method of manufacturing a thin film memory cell, comprising forming a low concentration impurity region by implanting the impurity region so that the source region or drain region of a selection transistor is also used as the drain region or source region of a memory transistor. 4. The method of manufacturing a thin film memory cell according to claim 3, wherein the semiconductor layer is polysilicon.