JPH04313215A - Low-pressure or vacuum baking apparatus and baking treatment method - Google Patents
Low-pressure or vacuum baking apparatus and baking treatment methodInfo
- Publication number
- JPH04313215A JPH04313215A JP7876791A JP7876791A JPH04313215A JP H04313215 A JPH04313215 A JP H04313215A JP 7876791 A JP7876791 A JP 7876791A JP 7876791 A JP7876791 A JP 7876791A JP H04313215 A JPH04313215 A JP H04313215A
- Authority
- JP
- Japan
- Prior art keywords
- baking
- pressure
- resist film
- semiconductor wafer
- hot plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- 239000002904 solvent Substances 0.000 abstract description 12
- 238000005530 etching Methods 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 239000013557 residual solvent Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- SVONRAPFKPVNKG-UHFFFAOYSA-N 2-ethoxyethyl acetate Chemical compound CCOCCOC(C)=O SVONRAPFKPVNKG-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/40—Treatment after imagewise removal, e.g. baking
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】この発明は、減圧或は真空ベーク
装置及びベーク処理方法、特に、半導体製造工程におけ
るレジスト膜等のベークに使用する減圧或は真空ベーク
装置及びベーク処理方法に関するものである。[Field of Industrial Application] This invention relates to a reduced pressure or vacuum baking device and a baking method, and more particularly to a reduced pressure or vacuum baking device and a baking method used for baking resist films, etc. in semiconductor manufacturing processes. .
【0002】0002
【従来の技術】従来、半導体製造工程においては、半導
体ウエハ上にレジスト溶液を塗布しプリベークにより溶
媒を除去した後、露光、現像を行い、溶媒、水を除去す
るためポストベークを行い、レジスト膜を形成していた
。さらに、このレジスト膜を介してウエットエッチング
を行い、エッチング液を除去するためにポストベークを
行い、次いで、ドライエッチングを行った後、レジスト
膜を除去していた。[Prior Art] Conventionally, in the semiconductor manufacturing process, a resist solution is applied onto a semiconductor wafer, the solvent is removed by pre-baking, then exposure and development are performed, and post-baking is performed to remove the solvent and water. was forming. Further, wet etching is performed through this resist film, post-baking is performed to remove the etching solution, dry etching is performed, and then the resist film is removed.
【0003】図2は、従来の写真製版で用いられるベー
ク方法のうちで、ホットプレート上で行うベーク装置を
示す概略断面図である。図において、支持台1に設けら
れたホットプレート2上に、半導体ウエハ3が載置され
ている。ホットプレート2の上部には、オーブンカバー
4が設けられている。FIG. 2 is a schematic cross-sectional view showing a baking device that performs baking on a hot plate in a baking method used in conventional photolithography. In the figure, a semiconductor wafer 3 is placed on a hot plate 2 provided on a support stand 1. An oven cover 4 is provided on the top of the hot plate 2.
【0004】従来のベーク装置は上述したように構成さ
れ、レジスト溶液を塗布した半導体ウエハ3をホットプ
レート2上に載置し、半導体ウエハ3を加熱することに
よってレジスト溶液中の溶媒を蒸発させる。特に現像後
のポストベークにおいては、図3に示すように、180
℃までは収縮によりレジスト膜の単位面積当たりのスト
レスは増大し、それと共に、ウエットエッチングを行っ
たときのサイドエッチ量(図中、黒丸で示す)も増大し
ていることが判る。一方、残存溶媒を取り切るためには
、残存溶媒量(図中、白丸で示す)が1以下(相対値)
となる150℃以上に昇温する必要がある。なお、上記
ウエットエッチングは、バッファードフッ酸によるSi
O2エッチングを行ったものである。従って、残存溶媒
を除去することと、ストレスを小さくしてウエットエッ
チング時のサイドエッチ量を小さくすることとは両立し
ない。The conventional baking apparatus is constructed as described above, in which a semiconductor wafer 3 coated with a resist solution is placed on a hot plate 2, and the solvent in the resist solution is evaporated by heating the semiconductor wafer 3. Especially in the post-bake after development, as shown in FIG.
℃, the stress per unit area of the resist film increases due to shrinkage, and at the same time, the amount of side etching (indicated by black circles in the figure) increases when wet etching is performed. On the other hand, in order to remove the remaining solvent, the amount of remaining solvent (indicated by a white circle in the figure) must be 1 or less (relative value).
It is necessary to raise the temperature to 150°C or higher. Note that the above wet etching is performed on Si using buffered hydrofluoric acid.
O2 etching was performed. Therefore, removing the residual solvent and reducing the amount of side etching during wet etching by reducing the stress are not compatible.
【0005】[0005]
【発明が解決しようとする課題】上述したような真空ベ
ーク装置では、写真製版工程のレジストパターン形成後
のベークにおいて、特に図3に見られるように、ベーク
温度が増大すればレジスト中のストレスは増大し、ウエ
ットエッチングを行った際にはサイドエッチ量が大きく
なる。つまり、レジスト膜と半導体基板との密着性が低
下する。また、ベーク後レジスト膜中の残存溶媒が多け
れば、次工程のドライエッチングの際、レジスト膜が流
れるリフローを起こし、エッジが傾斜してレジスト膜が
後退するという問題点があった。その他にも、ベーク温
度が高ければ、レジスト膜中の低分子成分で昇華点の低
い物質が昇華し、異物発生の原因となるという問題点が
あった。[Problems to be Solved by the Invention] In the vacuum baking apparatus as described above, during baking after resist pattern formation in the photolithography process, as shown in FIG. 3, as the baking temperature increases, stress in the resist decreases. The amount of side etching increases when wet etching is performed. In other words, the adhesion between the resist film and the semiconductor substrate decreases. Further, if there is a large amount of residual solvent in the resist film after baking, there is a problem in that during the next step of dry etching, the resist film will reflow, resulting in tilted edges and receding of the resist film. Another problem is that if the baking temperature is high, low-molecular-weight substances with low sublimation points in the resist film sublimate, causing the generation of foreign matter.
【0006】この発明は、このような問題点を解決する
ためになされたもので、ベーク中に減圧することで、レ
ジスト膜中の溶媒を効率良く蒸発させることができ、ベ
ーク温度も従来より下げることができるので、レジスト
パターンに発生するストレスを抑えることができ、レジ
ストの耐熱性も向上させることができる減圧或は真空ベ
ーク装置及びベーク処理方法を得ることを目的とする。The present invention was made to solve these problems, and by reducing the pressure during baking, the solvent in the resist film can be efficiently evaporated, and the baking temperature can also be lowered than before. An object of the present invention is to provide a reduced pressure or vacuum baking apparatus and a baking treatment method that can suppress stress generated in a resist pattern and improve the heat resistance of the resist.
【0007】[0007]
【課題を解決するための手段】この発明の請求項1に係
る減圧或は真空ベーク装置は、半導体ウエハを加熱状態
で減圧あるいは真空に排気する排気手段を設けたもので
ある。また、この発明の請求項2に係るベーク処理方法
は、半導体ウエハを所定温度に加熱し、常圧から10T
orrの圧力範囲に減圧してベーク処理を行うものであ
る。Means for Solving the Problems A depressurization or vacuum baking apparatus according to claim 1 of the present invention is provided with an exhaust means for depressurizing or vacuuming a semiconductor wafer in a heated state. Further, in the baking method according to claim 2 of the present invention, the semiconductor wafer is heated to a predetermined temperature, and the temperature is increased from normal pressure to 10T.
The baking process is carried out by reducing the pressure to a pressure range of orr.
【0008】[0008]
【作用】この発明においては、ベーク中に減圧にするこ
とにより、レジスト溶液又はレジスト膜中の溶媒を効率
良く蒸発させることができ、かつ、ベーク温度を従来よ
り下げることができるので、レジストパターンにかかる
ストレスを抑えることができる。これにより、レジスト
膜と半導体基板との密着性を向上させることができ、レ
ジストパターンの耐熱性も向上させることができる。ま
た、ベーク中の昇華物の発生も低減させることができる
。[Function] In this invention, by reducing the pressure during baking, the solvent in the resist solution or resist film can be efficiently evaporated, and the baking temperature can be lowered than before, so that the resist pattern This stress can be reduced. Thereby, the adhesion between the resist film and the semiconductor substrate can be improved, and the heat resistance of the resist pattern can also be improved. Furthermore, generation of sublimate during baking can also be reduced.
【0009】[0009]
【実施例】図1は、この発明の一実施例による減圧或は
真空ベーク装置を示す概略断面図である。なお、各図中
、同一符号は同一又は相当部分を示している。図におい
て、支持台1に加熱手段としてホットプレート2が設け
られ、このホットプレート2上に半導体ウエハ3が載置
されている。この半導体ウエハ3には、写真製版におけ
るリソグラフィー工程においてレジスト溶液が塗布され
露光、現像によりパターニングされたレジスト膜が形成
されている。ホットプレート2の上部には、半導体ウエ
ハ3を気密に覆うオーブンカバー4が設けられている。
気密にされたオーブンカバー4内は、排気手段例えば真
空ポンプ5により常圧から10Torrの範囲の圧力に
減圧されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a schematic sectional view showing a reduced pressure or vacuum baking apparatus according to an embodiment of the present invention. Note that in each figure, the same reference numerals indicate the same or equivalent parts. In the figure, a hot plate 2 is provided as a heating means on a support stand 1, and a semiconductor wafer 3 is placed on this hot plate 2. A resist solution is applied to this semiconductor wafer 3 in a lithography process in photolithography, and a resist film is formed by patterning by exposure and development. An oven cover 4 is provided above the hot plate 2 to airtightly cover the semiconductor wafer 3. The pressure inside the airtight oven cover 4 is reduced to a pressure in the range from normal pressure to 10 Torr by an evacuation means, such as a vacuum pump 5.
【0010】上述したように構成された減圧或は真空ベ
ーク装置においては、半導体ウエハ3をホットプレート
2上に載置した後、ホットプレート2上をオーブンカバ
ー4により気密に覆う。次いで、気密にされたオーブン
カバー4内を常圧から10Torrの範囲の圧力に減圧
した状態で、ベーク処理を行う。これによって、レジス
ト膜の溶媒を蒸発除去し、レジスト膜を硬化させる。従
って、レジスト膜の溶媒を効率良く除去できると共に、
ベーク温度を従来より下げることができるため、レジス
ト膜と半導体基板との密着性を向上させることができる
。
また、レジスト膜中の残存溶媒の影響によるレジスト膜
の耐熱性の低下を防ぐことができるので、リフローを防
止しより精密なエッチングが可能となる。さらに、レジ
スト膜中の昇華物の発生も減少させることができる。な
お、どの程度の圧力に減圧すれば良いかは、レジスト膜
(有機膜)や有機溶媒の種類に依存する。上記圧力範囲
では、例えばノボラックレジン−ナフトキノンジアジド
系(ポジ型)の有機膜、有機溶媒としてエチルセロソル
ブアセテート等が効果的に除去できる。In the reduced pressure or vacuum baking apparatus configured as described above, after the semiconductor wafer 3 is placed on the hot plate 2, the hot plate 2 is hermetically covered with the oven cover 4. Next, a baking process is performed while the inside of the airtight oven cover 4 is reduced in pressure from normal pressure to 10 Torr. As a result, the solvent in the resist film is evaporated and the resist film is cured. Therefore, the solvent of the resist film can be removed efficiently, and
Since the baking temperature can be lowered than before, the adhesion between the resist film and the semiconductor substrate can be improved. Further, since it is possible to prevent a decrease in the heat resistance of the resist film due to the influence of residual solvent in the resist film, reflow can be prevented and more precise etching can be performed. Furthermore, generation of sublimated substances in the resist film can also be reduced. Note that the level of pressure that should be reduced depends on the type of resist film (organic film) and organic solvent. In the above pressure range, for example, a novolac resin-naphthoquinone diazide (positive type) organic film, ethyl cellosolve acetate as an organic solvent, etc. can be effectively removed.
【0011】なお、上述した実施例では、半導体ウエハ
3をホットプレート2上に載置したが、ポストベーク炉
内に半導体ウエハ3を収容し、溶媒を蒸発させてレジス
ト膜を硬化させてもよく、上述と同様の効果を奏する。In the above embodiment, the semiconductor wafer 3 is placed on the hot plate 2, but the semiconductor wafer 3 may be placed in a post-bake oven to evaporate the solvent and harden the resist film. , the same effect as described above is achieved.
【0012】0012
【発明の効果】この発明は以上説明したとおり、半導体
ウエハを加熱状態で減圧あるいは真空に排気する排気手
段を設け、常圧から10Torrの圧力範囲に減圧して
ベーク処理を行うので、レジスト膜の溶媒を効率良く除
去できると共に、ベーク温度を従来より下げることがで
きるため、レジスト膜と半導体基板との密着性を向上さ
せることができ、レジスト膜中の残存溶媒の影響による
レジスト膜の耐熱性の低下を防ぐことができ、さらに、
レジスト膜中の昇華物の発生も減少させることができる
という効果を奏する。Effects of the Invention As explained above, the present invention is provided with an evacuation means that reduces the pressure or evacuates the semiconductor wafer in a heated state, and performs the baking process by reducing the pressure from normal pressure to 10 Torr. As the solvent can be removed efficiently and the baking temperature can be lowered than before, the adhesion between the resist film and the semiconductor substrate can be improved, and the heat resistance of the resist film due to the influence of residual solvent in the resist film can be improved. It is possible to prevent the decline, and furthermore,
This has the effect of reducing the generation of sublimates in the resist film.
【図1】この発明の一実施例による減圧或は真空ベーク
装置を示す概略断面図である。FIG. 1 is a schematic sectional view showing a reduced pressure or vacuum baking device according to an embodiment of the present invention.
【図2】従来の減圧或は真空ベーク装置を示す概略断面
図である。FIG. 2 is a schematic cross-sectional view showing a conventional reduced pressure or vacuum baking device.
【図3】ベーク温度に対するレジスト膜の諸特性の関係
を示す線図である。FIG. 3 is a diagram showing the relationship between various properties of a resist film and bake temperature.
1 支持台 2 ホットプレート 3 半導体ウエハ 4 オーブンカバー 5 真空ポンプ 1 Support stand 2 Hot plate 3 Semiconductor wafer 4 Oven cover 5 Vacuum pump
Claims (2)
上記半導体ウエハを加熱状態で減圧あるいは真空に排気
する排気手段とを備えたことを特徴とする減圧或は真空
ベーク装置。Claim 1: A heating means for heating a semiconductor wafer;
A depressurization or vacuum baking apparatus comprising an evacuation means for depressurizing or evacuating the semiconductor wafer in a heated state.
記半導体ウエハの周囲を常圧から10Torrの圧力範
囲に減圧してベーク処理を行うことを特徴とするベーク
処理方法。2. A baking process, which comprises heating a semiconductor wafer to a predetermined temperature and reducing the pressure around the semiconductor wafer from normal pressure to 10 Torr.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7876791A JPH04313215A (en) | 1991-04-11 | 1991-04-11 | Low-pressure or vacuum baking apparatus and baking treatment method |
DE19924200038 DE4200038C2 (en) | 1991-04-11 | 1992-01-02 | Process for curing a developed photoresist layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7876791A JPH04313215A (en) | 1991-04-11 | 1991-04-11 | Low-pressure or vacuum baking apparatus and baking treatment method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04313215A true JPH04313215A (en) | 1992-11-05 |
Family
ID=13671056
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7876791A Pending JPH04313215A (en) | 1991-04-11 | 1991-04-11 | Low-pressure or vacuum baking apparatus and baking treatment method |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPH04313215A (en) |
DE (1) | DE4200038C2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009200423A (en) * | 2008-02-25 | 2009-09-03 | Asahi Glass Co Ltd | Method for manufacturing reflective mask for euv lithography |
JP2010103480A (en) * | 2008-09-25 | 2010-05-06 | Tokyo Electron Ltd | Reduced-pressure drying device and reduced-pressure drying method |
CN106353975A (en) * | 2016-11-25 | 2017-01-25 | 天津津芯微电子科技有限公司 | LDI (Laser Direct Image) exposure device and LDI exposure system |
CN106773535A (en) * | 2016-12-12 | 2017-05-31 | 中国科学院光电技术研究所 | High-precision photoresist surface shape control method |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0427113A (en) * | 1990-04-23 | 1992-01-30 | Tadahiro Omi | Resist treatment device, resist treatment method, and resist pattern |
SG105487A1 (en) | 2000-03-30 | 2004-08-27 | Tokyo Electron Ltd | Substrate processing apparatus and substrate processing method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63202912A (en) * | 1987-02-18 | 1988-08-22 | Nec Kyushu Ltd | Baking device for semiconductor substrate |
JPS63260028A (en) * | 1986-11-19 | 1988-10-27 | Tokyo Ohka Kogyo Co Ltd | Heat stabilizer for photoresist |
JPH0382112A (en) * | 1989-08-25 | 1991-04-08 | Hitachi Ltd | Charged particle beam lithography and device therefor |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0740547B2 (en) * | 1987-03-24 | 1995-05-01 | ウシオ電機株式会社 | Resist processing method |
DE3837648A1 (en) * | 1988-11-05 | 1990-05-10 | Basf Ag | DEVICE FOR WASHING PHOTOPOLYMER PRINTING PLATES BY MEANS OF SOLVENTS, DRYING OF THE PRESSURE PLATES AND RECOVERY OF THE SOLVENTS |
-
1991
- 1991-04-11 JP JP7876791A patent/JPH04313215A/en active Pending
-
1992
- 1992-01-02 DE DE19924200038 patent/DE4200038C2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63260028A (en) * | 1986-11-19 | 1988-10-27 | Tokyo Ohka Kogyo Co Ltd | Heat stabilizer for photoresist |
JPS63202912A (en) * | 1987-02-18 | 1988-08-22 | Nec Kyushu Ltd | Baking device for semiconductor substrate |
JPH0382112A (en) * | 1989-08-25 | 1991-04-08 | Hitachi Ltd | Charged particle beam lithography and device therefor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009200423A (en) * | 2008-02-25 | 2009-09-03 | Asahi Glass Co Ltd | Method for manufacturing reflective mask for euv lithography |
JP2010103480A (en) * | 2008-09-25 | 2010-05-06 | Tokyo Electron Ltd | Reduced-pressure drying device and reduced-pressure drying method |
CN106353975A (en) * | 2016-11-25 | 2017-01-25 | 天津津芯微电子科技有限公司 | LDI (Laser Direct Image) exposure device and LDI exposure system |
CN106773535A (en) * | 2016-12-12 | 2017-05-31 | 中国科学院光电技术研究所 | High-precision photoresist surface shape control method |
Also Published As
Publication number | Publication date |
---|---|
DE4200038A1 (en) | 1992-10-22 |
DE4200038C2 (en) | 1998-07-09 |
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