JPH04311246A - Interruption acceptance circuit - Google Patents

Abstract

PURPOSE:To set a desired mode out of various kinds of interrupt modes and, at the same time, to avoid wrong acceptance caused by noise with a simple configuration by providing a combinatorial logic circuit. CONSTITUTION:A combinatorial logic circuit 5 logically processes the parallel outputs of a shift register 2 and, when the parallel outputs are continuously high in level by (n) or more bits in the shifting direction from an interruption request signal input terminal 1 side, outputs an interruption accept signal to an output terminal 41. When the parallel outputs are continuously high in level by the (n) bits in the shifting direction from the input terminal 1 side, the circuit 5 outputs the interruption accept signal to another output terminal 42 also. When the parallel outputs are continuously low in level by the (n) or more bits in the shifting direction from the input terminal 1 side, the circuit 5 outputs the accept signal to an output terminal 43 and, when the parallel outputs are continuously low in level by the (n) bits, outputs the accept signal to another output terminal 44 also. A multiplexer 6 selects the interruption accept signals outputted to the output terminals 41, 42, 43, and 44 and sets an interrupt mode.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt reception circuit used in a computer system by being installed in an interrupt controller or the like that controls interrupt requests from peripheral circuits to a CPU.

0002

2. Description of the Related Art Conventionally, interrupt reception circuits have been constructed using RS flip-flops and D flip-flops. FIG. 6 shows an interrupt reception circuit using an RS flip-flop, and FIG. 8 shows an interrupt reception circuit using a D flip-flop.

The interrupt reception circuit shown in FIG. 6 inputs an interrupt request signal IRQ to a set input terminal S of an RS flip-flop, and attempts to obtain an interrupt reception signal of H level at a positive phase output terminal Q, for example. Yes, it is possible to accept an interrupt request signal IRQ whose H level indicates an interrupt request. FIG. 7 is a time chart showing the operation in this case. Note that when the interrupt request signal IRQ is inverted and inputted to the set input terminal S, it is possible to accept the interrupt request signal IRQ whose L level indicates an interrupt request.

Further, the interrupt reception circuit shown in FIG. 8 fixes the data input terminal D of the D flip-flop at H level, inputs the interrupt request signal IRQ to the clock input terminal CK, and
The purpose is to obtain an interrupt acceptance signal of H level at the positive phase output terminal Q, and it is possible to accept an interrupt request signal IRQ whose rising edge indicates an interrupt request. FIG. 9 is a time chart showing the operation in this case. Note that when the interrupt request signal IRQ is inverted and inputted to the clock input terminal CK, it is possible to accept the interrupt request signal IRQ whose falling edge indicates an interrupt request.

[0005]

[Problems to be Solved by the Invention] In the interrupt reception circuit shown in FIG. 6, when noise as shown by the broken line in FIG. There was a problem in that there were cases in which the data was output and an incorrect reception was made. In the interrupt reception circuit shown in FIG. 8, when noise as shown by the broken line in FIG. 9 is input to the clock input terminal CK, an interrupt reception signal is outputted to the positive phase output terminal Q, resulting in erroneous reception. There was a problem that it could get lost.

In addition, there are two modes: (1) a mode in which an interrupt request signal whose H level indicates an interrupt request is accepted, a so-called H level interrupt mode, and (2) a mode in which an interrupt request signal whose rising edge indicates an interrupt request is accepted, a so-called rising edge interrupt mode. , ■ A mode that accepts an interrupt request signal whose L level indicates an interrupt request, the so-called L level interrupt mode, and ■ A mode that accepts an interrupt request signal whose falling edge indicates an interrupt request, the so-called falling interrupt mode. An interrupt reception circuit that can set the desired interrupt mode,
When configured using the interrupt acceptance circuits of FIGS. 6 and 8,
Another problem was that it resulted in a complicated circuit configuration.

In view of these points, the present invention provides: (1) an interrupt reception circuit that can avoid erroneous reception due to noise; and (2) H level interrupt mode, rising edge interrupt mode, L level interrupt mode, and falling edge interrupt mode. To provide an interrupt reception circuit that can set a desired interrupt mode among edge interrupt modes, can realize this with a simple circuit configuration, and can avoid erroneous reception due to noise. With the goal.

[0008]

[Means for Solving the Problem] FIG. 1 is a diagram explaining the principle of a first invention of the present invention, and an interrupt reception circuit according to the first invention has an interrupt request signal input terminal 1 and an interrupt request signal input terminal 1. Interrupt request signal IRQ input to input terminal 1
n+i to convert serial to parallel without inverting or by inverting
A shift register 2 with a bit configuration (where n = an integer of 2 or more, i = an integer of 1 or more) and the parallel outputs of this shift register 2 are logically processed, and the parallel outputs of the shift register 2 are output to the interrupt request signal input terminal 1. If n bits or more are continuously at H level or L level in the shift direction from the side, or the parallel output of shift register 2 is at H level or L level continuously for n bits or more in the shift direction from the interrupt request signal input terminal 1 side. In this case, a combinational logic circuit 3 configured to output an interrupt acceptance signal is provided.

[0009]

[Operation] In the first invention, in the case where the shift register 2 having an n+i bit configuration is provided, which converts the interrupt request signal IRQ inputted to the interrupt request signal input terminal 1 into serial to parallel without inverting it, the shift register 2 has an n+i bit configuration. If the combinational logic circuit 3 is configured to output an interrupt acceptance signal when the parallel output is at the H level continuously for n or more bits in the shift direction from the interrupt request signal input terminal 1 side, the H level is the interrupt request signal. It is possible to accept an interrupt request signal IRQ indicating the following. In other words, in this case, the interrupt request signal IRQ whose H level indicates an interrupt request is issued as an interrupt only when the H level continues for a period longer than n-1 cycles in the clock cycle supplied to the shift register 2. Accepted as a request signal.

[0010] Furthermore, in the case where a shift register 2 having an n+i bit configuration is provided which converts the interrupt request signal IRQ inputted to the interrupt request signal input terminal 1 into serial to parallel without inverting it, the parallel output of the shift register 2 is used as the interrupt request signal. If the combinational logic circuit 3 is configured so that an interrupt acceptance signal is output when n bits or more are continuously at L level in the shift direction from the input terminal 1 side, an interrupt request whose L level indicates an interrupt request. Signal IRQ can be accepted. In other words, in this case, the interrupt request signal IRQ, whose L level indicates an interrupt request, will cause an interrupt only if the L level continues for a period longer than n-1 cycles in the clock cycle supplied to the shift register 2. Accepted as a request signal.

Furthermore, in the case where a shift register 2 having an n+i bit configuration is provided which converts the interrupt request signal IRQ inputted to the interrupt request signal input terminal 1 into serial to parallel without inverting it, the parallel output of the shift register 2 is used as the interrupt request signal. Continuously high for n bits in the shift direction from the input terminal 1 side
If the combinational logic circuit 3 is configured to output an interrupt acceptance signal when a level is output, it is possible to accept an interrupt request signal whose rising edge indicates an interrupt request. In other words, in this case, the interrupt request signal IR whose rising edge indicates an interrupt request
After rising, Q is accepted as an interrupt request signal only when the H level continues for a period longer than n-1 cycles of the clock supplied to the shift register 2.

[0012] Furthermore, in the case where a shift register 2 having an n+i bit configuration is provided, which converts the interrupt request signal IRQ inputted to the interrupt request signal input terminal 1 into serial/parallel data without inverting it, the bits on the input terminal side of the shift register 2 are If the combinational logic circuit 3 is configured to output an interrupt acceptance signal when n bits are continuously output at L level, it is possible to accept the interrupt request signal IRQ whose falling edge indicates an interrupt request. can. In other words, in this case, the interrupt request signal IRQ, whose falling edge indicates an interrupt request, remains at L level continuously for a period longer than n-1 cycles of the clock supplied to the shift register 2 after falling. Only then will it be accepted as an interrupt request signal.

Furthermore, the interrupt request signal IRQ input to the interrupt request signal input terminal 1 is inverted and serial-parallel converted.
When a shift register 2 with a +i bit configuration is provided, if the parallel output of the shift register 2 is at H level continuously for n bits or more in the shift direction from the interrupt request signal input terminal 1 side, an interrupt acceptance signal is output. When configuring the combinational logic circuit 3, it is possible to accept an interrupt request signal IRQ whose L level indicates an interrupt request. In other words, in this case, the interrupt request signal IRQ, whose L level indicates an interrupt request, will cause an interrupt only if the L level continues for a period longer than n-1 cycles in the clock cycle supplied to the shift register 2. Accepted as a request signal.

Furthermore, the interrupt request signal IRQ input to the interrupt request signal input terminal 1 is inverted and serial-parallel converted.
When a shift register 2 with a +i bit configuration is provided, if the parallel output of the shift register 2 is at L level continuously for n or more bits in the shift direction from the interrupt request signal input terminal 1 side, an interrupt acceptance signal is output. When configuring the combinational logic circuit 3, it is possible to accept an interrupt request signal IRQ whose H level indicates an interrupt request. In other words, in this case, the interrupt request signal IRQ
is the clock period supplied to shift register 2 and is n−
Only when the H level continues for a period longer than one cycle is it accepted as an interrupt request signal.

Furthermore, the interrupt request signal IRQ input to the interrupt request signal input terminal 1 is inverted and serial-parallel converted.
When a shift register 2 with +i bit configuration is provided, if the parallel output of the shift register 2 is at H level for n bits consecutively in the shift direction from the interrupt request signal input terminal 1 side, an interrupt acceptance signal is output. When configuring the combinational logic circuit 3, it is possible to accept an interrupt request signal IRQ whose falling edge indicates an interrupt request. In other words, in this case, the falling edge of the interrupt request signal IRQ indicates an interrupt request.
is accepted as an interrupt request signal only when it continues to be at L level for a period longer than n-1 cycles of the clock supplied to the shift register 2 after falling.

Furthermore, the interrupt request signal IRQ input to the interrupt request signal input terminal 1 is inverted and serial-parallel converted.
When a shift register 2 with a +i bit configuration is provided, if the parallel output of the shift register 2 is at L level continuously for n bits in the shift direction from the interrupt request signal input terminal 1 side, an interrupt acceptance signal is output. When configuring the combinational logic circuit 3, it is possible to accept an interrupt request signal IRQ whose rising edge indicates an interrupt request. In other words, in this case, the interrupt request signal IRQ whose rising edge indicates an interrupt request
is accepted as an interrupt request signal only when it remains at H level for a period longer than n-1 cycles of the clock supplied to the shift register 2 after rising.

Therefore, as shown in FIG. 2, which is a diagram illustrating the principle of the second aspect of the present invention, an interrupt request signal input terminal 1 and an interrupt request signal IRQ inputted to this interrupt request signal input terminal 1 are provided. convert serial to parallel without inverting n
It has a shift register 2 with a +i bit configuration and first, second, third, and fourth output terminals 41, 42, 43, and 44, and performs logical processing on the parallel outputs of the shift register 2, and If the output is at H level continuously for n bits or more in the shift direction from the interrupt request signal input terminal 1 side, an interrupt acceptance signal is output to the first output terminal 41, and the parallel output of the shift register 2 becomes an interrupt request signal. If n bits are continuously at H level in the shift direction from the input terminal 1 side, an interrupt acceptance signal is also output to the second output terminal 42, and the parallel output of the shift register 2 is output to the interrupt request signal input terminal 1.
If n bits or more are continuously at L level in the shift direction from the side, an interrupt acceptance signal is output to the third output terminal 43, and the parallel output of the shift register 2 is output from the interrupt request signal input terminal 1 side in the shift direction. The combinational logic circuit 5 is configured to output an interrupt acceptance signal to the fourth output terminal 44 when n bits are continuously outputted at L level.
and first, second, third, and fourth output terminals 41, 42, 4
When configured with a multiplexer 6 for selecting the interrupt acceptance signal outputted to the terminals 3 and 44, one of the H level interrupt mode, rising edge interrupt mode, L level interrupt mode, and falling edge interrupt mode is provided. A desired interrupt mode can be set.

That is, when selecting the interrupt acceptance signal output to the first output terminal 41, it is possible to accept the interrupt request signal IRQ whose H level indicates an interrupt request. However, in this case, the interrupt request signal IRQ, whose H level indicates an interrupt request, will not be accepted unless it remains at the H level for a period longer than n-1 cycles of the clock supplied to the shift register 2.

Furthermore, when selecting the interrupt acceptance signal outputted to the second output terminal 42, it is possible to accept an interrupt request signal IRQ whose rising edge indicates an interrupt request. However, in this case, the interrupt request signal IRQ, whose rising edge indicates an interrupt request, will not be accepted unless it remains at an H level continuously for a period longer than n-1 cycles of the clock supplied to the shift register 2 after rising. do not have.

Furthermore, when selecting the interrupt acceptance signal outputted to the third output terminal 43, it is possible to accept an interrupt request signal IRQ whose L level indicates an interrupt request. However, in this case, the interrupt request signal IRQ, whose L level indicates an interrupt request, will not be accepted unless it remains at the L level for a period longer than n-1 cycles of the clock supplied to the shift register 2.

Furthermore, when selecting the interrupt acceptance signal outputted to the fourth output terminal 44, it is possible to accept an interrupt request signal IRQ whose falling edge indicates an interrupt request. However, in this case, the interrupt request signal, whose falling edge indicates an interrupt request, is n in the clock cycle supplied to the shift register 2 after falling.
It is not accepted unless the L level continues for a period longer than -1 cycle.

In addition, in FIG. 2, when the shift register 2 is configured to invert the interrupt request signal IRQ inputted to the interrupt request signal input terminal 1 and perform serial-to-parallel conversion, the first output terminal 41 When selecting the interrupt acceptance signal output to the second output terminal 42, the interrupt request signal IRQ whose L level indicates an interrupt request can be accepted; when selecting the interrupt acceptance signal output to the second output terminal 42, , can accept the interrupt request signal IRQ whose falling edge indicates an interrupt request, and the third
When selecting the interrupt acceptance signal output to the fourth output terminal 43, it is possible to accept the interrupt request signal IRQ whose H level indicates an interrupt request, and select the interrupt acceptance signal output to the fourth output terminal 44. If you select
An interrupt request signal IRQ whose rising edge indicates an interrupt request can be accepted.

However, the interrupt request signal IRQ whose L level indicates an interrupt request will not be accepted unless it remains at the L level continuously for a period longer than n-1 cycles of the clock cycle supplied to the shift register 2. The interrupt request signal IRQ, whose falling edge indicates an interrupt request, cannot be accepted unless it remains at the L level continuously for a period longer than n-1 cycles of the clock supplied to the shift register 2 after falling, and the interrupt request signal IRQ goes to the H level. The interrupt request signal IRQ, which indicates an interrupt request, has a clock cycle supplied to the shift register 2 for a period longer than n-1 cycles.
An interrupt request signal whose rising edge indicates an interrupt request cannot be accepted unless the H level is continuous. The point that it will not be accepted unless you do so is the same as the previous example.

[0024]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 3 to 5.

FIG. 3 is a diagram showing an embodiment of the present invention.
In the figure, 7 is an interrupt request signal input terminal into which the interrupt request signal IRQ is input, 8 is a 4-bit shift register that inverts and converts the interrupt request signal IRQ input into the interrupt request signal input terminal 7 from serial to parallel. 9 is a clock input terminal, 10 is a combinational logic circuit, and this combinational logic circuit 1
0 is composed of inverters 11 and 12, a NOR circuit 13, an exclusive OR circuit 14, and AND circuits 15 to 17.

Further, 18 to 21 are interrupt mode setting signal input terminals to which interrupt mode setting signals D1, D2, D1 bar, and D2 bar are input, and 22 is an interrupt mode setting signal D.
1, D2, D1 bar, and D2 bar to select the outputs OA, OB, OC, and OD of the combinational logic circuit 10, and this multiplexer 22 is
It is composed of AND circuits 23 to 26 and a NOR circuit 27. Note that 28 is an interrupt acceptance signal output terminal.

Here, the outputs QA and Q of the shift register 8
B, QC, QD and the outputs OA, O of the combinational logic circuit 10
The relationship between B, OC, and OD is shown in Table 1.

[0028]

[Table 1]

Note that the inverters 11 and 12 are used to prevent the output OB of the combinational logic circuit 10 from becoming H level when the outputs QA, QB, QC, and QD of the shift register 8 all become L level. belongs to.

Furthermore, interrupt mode setting signals D1, D2,
D1 bar, D2 bar, and the activation of AND circuits 23 to 26,
Inactive and outputs of combinational logic circuits OA, OB, OC, O
Among D, the relationship with the output selected by the multiplexer 22 is as shown in Table 2.

[0031]

[Table 2]

Therefore, the outputs QA and Q of the shift register 8
B, QC, QD and the outputs OA, O of the combinational logic circuit 10
B, OC, OD, and interrupt mode setting signals D1, D2,
D1 bar, D2 bar and the outputs OA and O of the combinational logic circuit
Outputs selected by the multiplexer 22 among B, OC, and OD and the logical states of the interrupt acceptance signal output terminal 28 are as shown in Tables 3 and 4.

[0033]

[Table 3]

[0034]

[Table 4]

If the L level signal output to the interrupt acceptance signal output terminal 28 is used as the interrupt acceptance signal, as is clear from Table 3, when selecting the output OA of the combinational logic circuit 10, An interrupt request signal IRQ whose H level indicates an interrupt request can be accepted. That is, an H level interrupt mode can be set. However, in this case, the interrupt request signal IRQ, whose H level indicates an interrupt request, has a continuous H level for a period longer than two clock cycles supplied to the shift register 2, as shown in FIG. It cannot be accepted without it.

[0036] Also, as is clear from Table 3,
When selecting the output OB of the combinational logic circuit 10, it is possible to accept an interrupt request signal IRQ whose rising edge indicates an interrupt request. That is, a rising edge interrupt mode can be set. However, in this case, the interrupt request signal IRQ whose rising edge indicates an interrupt request remains high for a period longer than two clock cycles supplied to the shift register 2 after rising, as shown in FIG. It will not be accepted unless the levels are consecutive.

Furthermore, as is clear from Table 4, when the output OC of the combinational logic circuit 10 is selected, it is possible to accept the interrupt request signal IRQ whose L level indicates an interrupt request. That is, an L level interrupt mode can be set. However, in this case, the interrupt request signal IRQ whose L level indicates an interrupt request is continuously at the L level for a period longer than two clock cycles supplied to the shift register 2, as shown in FIG. It cannot be accepted without it.

[0038] Also, as is clear from Table 4,
When selecting the output OD of the combinational logic circuit 10, it is possible to accept an interrupt request signal IRQ whose falling edge indicates an interrupt request. That is, a falling edge interrupt mode can be set. However, in this case, the interrupt request signal IRQ whose falling edge indicates an interrupt request has a period longer than 2 cycles in the clock cycle supplied to the shift register 2 after falling, as shown in FIG. , it will not be accepted unless the L level is consecutive.

As described above, according to this embodiment, a desired interrupt mode can be set among the H level interrupt mode, rising edge interrupt mode, L level interrupt mode, and falling edge interrupt mode. This embodiment realizes this with a simple circuit configuration.

Furthermore, in this embodiment, when setting the H level interrupt mode, the interrupt request signal IRQ whose H level indicates an interrupt request has a clock period longer than 2 cycles supplied to the shift register 2. Period, H
It will not be accepted unless the levels are consecutive. In addition, when setting the rising edge interrupt mode, the interrupt request signal IR whose rising edge indicates an interrupt request.
Q is not accepted unless it remains at the H level continuously for a period longer than two cycles of the clock supplied to the shift register 2 after rising. In addition, when setting the L level interrupt mode, the interrupt request signal IRQ whose L level indicates an interrupt request is kept at the L level for a period longer than two clock cycles supplied to the shift register 2.
It will not be accepted unless the levels are consecutive. In addition, when setting to falling interrupt mode, the interrupt request signal IRQ whose falling edge indicates an interrupt request is
After falling, unless the L level remains continuous for a period longer than two clock cycles supplied to the shift register 2, it will not be accepted. Therefore, according to this embodiment, erroneous reception due to noise input to the interrupt request signal input terminal 7 can be avoided.

In the above embodiment, the shift register 8, the combinational logic circuit 10, and the multiplexer 2
2, but instead, it is configured with a shift register and a combinational logic circuit, and the combinational logic circuit is set to H level interrupt mode, rising edge interrupt mode, L level interrupt mode, or rising edge interrupt mode. If configured so that only the falling edge interrupt mode can be set, this can also be used exclusively for a specific interrupt mode.

[0042]

According to the first aspect of the present invention, when the interrupt request signal IRQ is configured to receive the interrupt request signal IRQ whose H level indicates an interrupt request, the interrupt request signal IRQ
Q is the clock period supplied to shift register 2 and is n
Only when the H level continues for a period longer than -1 cycle is accepted as an interrupt request signal. Also, L
Interrupt request signal IRQ whose level indicates an interrupt request
When configured to accept interrupt request signals, this interrupt request signal IRQ is accepted as an interrupt request signal only when the L level continues for a period longer than n-1 cycles of the clock cycle supplied to the shift register 2. Also,
When configured to accept an interrupt request signal IRQ whose rising edge indicates an interrupt request, this interrupt request signal IRQ is transferred to the shift register 2 after rising.
The interrupt request signal is accepted only when the H level continues for a period longer than n-1 cycles of the clock supplied to the interrupt request signal. Further, when accepting an interrupt request signal IRQ whose falling edge indicates an interrupt request, this interrupt request signal IRQ is transmitted for a period longer than n-1 cycles in the clock cycle supplied to the shift register 2 after falling. Only when the L level continues, it is accepted as an interrupt request signal. Therefore, erroneous reception due to noise input to the interrupt request signal input terminal 1 can be avoided.

Furthermore, according to the second invention of the present invention, H
level interrupt mode, rising edge interrupt mode,
You can set the desired interrupt mode between L level interrupt mode and falling edge interrupt mode.
Moreover, this can be realized with a simple circuit configuration.

Further, according to the second invention, when setting the H level interrupt mode, the interrupt request signal IRQ whose H level indicates an interrupt request is transferred to the shift register 2.
The interrupt request signal is accepted only when the H level continues for a period longer than n-1 cycles of the clock supplied to the interrupt request signal. In addition, when setting to the L level interrupt mode, the interrupt request signal IRQ whose L level indicates an interrupt request has a continuous L level for a period longer than n-1 cycles in the clock cycle supplied to the shift register 2. Only in this case, it is accepted as an interrupt request signal. In addition, when setting the rising edge interrupt mode, the interrupt request signal IRQ whose rising edge indicates an interrupt request remains at an H level for a period longer than n-1 cycles in the clock cycle supplied to the shift register 2 after rising. It is accepted as an interrupt request signal only if it is consecutive. In addition, when setting the falling edge interrupt mode, the interrupt request signal IRQ whose falling edge indicates an interrupt request has a period longer than n-1 cycles in the clock cycle supplied to the shift register 2 after falling. , is accepted as an interrupt request signal only when the L level is continuous. Therefore, erroneous reception due to noise input to the interrupt request signal input terminal 1 can be avoided.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating the principle of the first invention of the present invention.

FIG. 2 is a diagram explaining the principle of the second invention in the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a time chart for explaining the operation of an embodiment of the present invention.

FIG. 5 is a time chart for explaining the operation of an embodiment of the present invention.

FIG. 6 is a diagram showing an example of a conventional interrupt reception circuit.

FIG. 7 is a time chart showing the operation of the interrupt acceptance circuit in FIG. 6;

FIG. 8 is a diagram showing another example of a conventional interrupt reception circuit.

FIG. 9 is a time chart showing the operation of the interrupt acceptance circuit of FIG. 8;

[Explanation of symbols]

1 Interrupt request signal input terminal 2 Shift register 3, 5 Combinational logic circuit 6 Multiplexer

Claims (2)

[Claims] Claim 1: An interrupt request signal input terminal (1) and an n+i bit configuration in which an interrupt request signal (IRQ) inputted to the interrupt request signal input terminal (1) is serial-parallel converted without inverting or by inverting the interrupt request signal (IRQ). (However, n = integer greater than or equal to 2, i =
Logic processing is performed on the shift register (2) of the shift register (an integer greater than or equal to 1) and the parallel output of the shift register (2), and the parallel output of the shift register (2) is connected to the interrupt request signal input terminal (
1) When n bits or more are continuously at H level or L level in the shift direction from the side, or when the shift register (
A combinational logic circuit (3) configured to output an interrupt acceptance signal when the parallel output of (2) is at H level or L level for n bits consecutively in the shift direction from the interrupt request signal input terminal (1) side. ). 2. An interrupt request signal input terminal (1) and an n+i bit configuration in which the interrupt request signal (IRQ) inputted to the interrupt request signal input terminal (1) is serial-parallel converted without inverting or by inverting the interrupt request signal (IRQ). (However, n = integer greater than or equal to 2, i =
(integer greater than or equal to 1) shift register (2), first and second
, third and fourth output terminals (41, 42, 43, 44), performs logical processing on the parallel outputs of the shift register (2), and outputs the parallel outputs of the shift register (2) as the interrupt request signal. If n bits or more are continuously at H level from the input terminal (1) side in the shift direction, an interrupt acceptance signal is output to the first output terminal (41), and the parallel output of the shift register (2) is The interrupt request signal input terminal (1
) side in the shift direction, an interrupt acceptance signal is also output to the second output terminal (42), and the parallel output of the shift register (2) is the interrupt request signal. n in the shift direction from the input terminal (1) side
If the level is L level continuously for more than one bit, an interrupt acceptance signal is output to the third output terminal (43), and the parallel output of the shift register (2) is output from the interrupt request signal input terminal (1) side. a combinational logic circuit (5) configured to output an interrupt acceptance signal also to the fourth output terminal (44) when n bits are continuously at L level in the shift direction; 2, 3rd, and 4th output terminals (4
1, 42, 43, 44) and a multiplexer (6) for selecting an interrupt acceptance signal outputted to the interrupt receiving circuit (1, 42, 43, 44) and setting an interrupt mode.