JPH04308952A - Address setting method for input and output terminal - Google Patents

Abstract

PURPOSE:To reduce to one or two the number of terminals of the transmission control LSi of a slave station, which fetch the multiple bit output of a multiple bit address setting plate equipped with each slave station, at the time of setting the address in a transmitting terminal (slave station) constituting a series transmission system, even when many terminals are conventionally necessitated. CONSTITUTION:An address setting terminal TM 1 of a transmission control LSi 1 is used as the input terminal of a multilevel signal (for example, analog voltage, output pulse of a pulse generator, and carry signal of an N-ary counter or the like), the AD conversion value of this analog voltage, the count value of the output pulse in a prescribed time, or the number of an input pulse to the N-ary counter until the generation of the carry signal, are searched in the LSi 1, and this value is used as the address of the pertinent slave station.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of setting addresses to input/output terminals constituting a serial transmission system such as a device built-in type used, for example, in a machine control device, a vending machine, an automobile, or the like. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

0002

[Prior Art] Figure 11 shows three typical serial transmission systems.
Two configurations are shown. In the figure, M is the master station, S (S1 to S
n) are first to nth (#1 to #n) slave stations serving as input/output (transmission) terminals. Figure (a) shows a multi-drop configuration in which all slave stations S1 to Sn are connected to a common set of serial transmission lines L, and Figure (b) shows a loop configuration in which one The series transmission line L1 of the set is connected to the first slave station S1.
A set of serial transmission lines L2 are input to the second slave station S2 via the first slave station S1 or signal-processed by the slave station S1, and so on. A set of serial transmission lines L from the final slave station Sn
The configuration is such that n is input to the master station M. Same figure (
c) has a 1:N coupling (star coupling) configuration, and the master station M and slave stations S1 to Sn each have one set of serial transmission lines L1 to Ln.
: Combined with 1. Any of the three configurations mentioned above are used in equipment-integrated serial transmission systems.
The multi-drop configuration (a) is often used due to its reliability and ease of connection when adding slave stations S.

Although not limited to serial transmission systems,
When a plurality of slave stations S are connected, each slave station requires an address for its identification. In the above three series transmission system configurations, an address for slave station identification is not absolutely necessary in the loop configuration in (b) and the 1:N configuration in (c), but it is essential in the multidrop configuration in (a). be. Generally, this address assignment is performed by providing an address setting board ASB in each slave station as shown in FIG.
How to set the n-bit address set by executed. Note that the address output line that is not short-circuited to the ground is pulled up to the DC power supply VCC via a resistor R, and exhibits an H level. Therefore, in this case, if the number of slave stations S is 8 or less (depending on the data transmission method, it may not be possible to distinguish between master stations and slave stations, but in that case the master stations are included in the number), then 3 When the number of slave stations is 2n or less, an n-bit address setting board ASB is required, such as 4 bits when the number of slave stations is 16 or less.

0004

In an equipment built-in system, input and output signal installation locations are scattered, so the number of slave stations is approximately 10 to 50. In this case, a 5- to 6-bit setting board is required for address setting. Generally, a dedicated LS is used for the transmission control circuit of a slave station from the viewpoint of economy and miniaturization.
i or one-chip CPU is used, but even if it is LSi,
Even if it is a one-chip CPU, the number of terminals on the package is required to be small from the point of view of cost, and generally 16 pins to 2 pins are required.
It is about 4 pins. Dedicated LSi or one-chip CPU
As described in Japanese Patent Application No. 63-323520, which is the applicant's earlier application, the address signal is assigned to the parallel input and output terminals for ON/OFF signal input and output. ) also has a shared method, but essentially it is desired to reduce the number of terminals used for address setting. SUMMARY OF THE INVENTION An object of the present invention is to provide an address setting method for an input/output terminal that can extremely reduce the number of terminals required for address setting (to about 1 or 2 terminals).

[0005]

[Means for Solving the Problems] In order to solve the above problems, the address setting method of claim 1 provides a method for setting multi-values of three or more values in an input/output terminal (transmission slave station S, etc.) constituting a transmission system. A single terminal (TM
1, etc.), and the address of this input/output terminal is set by the multi-value signal,

[
The address setting method according to a second aspect of the present invention is the address setting method according to the first aspect, wherein the multi-value signal is an analog voltage;

[0007] The address setting method according to claim 3 is as follows:
In the address setting method described in , a resistive voltage divider type voltage setter (
2 etc.),

[0008] The address setting method according to claim 4 is the address setting method according to claim 1.
In the address setting method described in , the multilevel signal is a pulse output from a pulse generator (such as 3),

[0009] The address setting method according to claim 5 is as follows.
In the address setting method described in , the pulse generator is a pulse generator (such as 31) specific to this transmission system.
and a frequency divider (32, 33, etc.) provided at the relevant input/output terminal, and

[0010] The address setting method according to claim 6 is the address setting method according to claim 1.
In the address setting method described in , the input/output terminal is provided with a pulse generating means (digital output unit 18, etc.) and an N-ary counter (4, etc.) for counting the pulses,
The multilevel signal is made to be a carry signal (4a, etc.) output from this N-ary counter.

[0011]

[Operation] In the inventions related to claims 1, 2, and 3, an analog-to-digital converter (A/D converter) and a memory area for address setting are provided inside the dedicated LSi or one-chip CPU, and the dedicated LSi Or one chip C
External to the PU, means is provided to generate a voltage specific to each slave station by resistive voltage division or the like. If, for example, 20 different voltage values (accuracy of ±2.5%) are generated by this, the A/D converter inside the dedicated LSi or one-chip CPU converts these voltage values into 8-bit binary. The dedicated LSi or one-chip CPU stores this A/D converted value in the address setting memory area and uses it as its own address. In this way, the dedicated LSi or one-chip CPU can identify 20 addresses just by preparing one address identification terminal (
setting) becomes possible.

[0012] In the inventions related to claims 1, 4, and 5, a pulse input means is provided inside the dedicated LSi or one-chip CPU.
A memory area for address setting is provided, and means for generating pulses unique to each slave station is provided outside the dedicated LSi or one-chip CPU. For example, an oscillator that generates 1023 pulses per T seconds and a frequency divider that divides the frequency by 1/N are provided. Then, a counter is provided as the pulse input means inside the dedicated LSi or one-chip CPU, and the contents of the pulse counter accumulated over T seconds are read out, stored in the address setting memory area, and set as the own address. .

[0013] Further, in the inventions according to claims 1 and 6, a signal change detection means, an address setting memory area, and a signal output means are provided inside the dedicated LSi or one-chip CPU, and the signal change detection means, address setting memory area, and signal output means are provided outside the dedicated LSi or one-chip CPU. is provided with a means (for example, an N-ary counter) for signal calculation unique to each slave station, and this signal calculation means is provided with the dedicated LSi or one-chip C
It is configured to give a signal from the PU. This allows the output signal from the dedicated LSi or one-chip CPU to be calculated by an external signal calculation circuit, such as an N-ary counter (
The dedicated LSi or one-chip CPU recognizes the number of pulses (signal change occurs at N pulses) and stores the outputted number of pulses (N) in the address setting memory area, and sets it as its own address.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a main part of a slave station according to an embodiment of the invention according to claims 1, 2, and 3, in which address setting is provided by a voltage divided by resistors. In the same figure, S
is a (transmission) slave station, L is a serial transmission line, 1 (1A) is a transmission control LSi constituting this slave station S, and 2 is a voltage setter for address setting. This transmission control LSi1A
is a CPU 11 that performs transmission control, data transfer control, and address identification processing, a ROM 12 that stores processing programs, a RAM 13 that stores transmission data and its own address, and a serial transmission line L that is not shown in the figure. A serial input/output unit (SIO) 14 executes data transmission between the master station (and other slave stations depending on the transmission method), and counts the time required for transmission control and program execution, and transmits it to the CPU 11. It consists of a timer 15 and an analog-to-digital converter (ADC) 16 that converts analog input values into digital values. Outside the transmission control LSi 1A, there is a resistor voltage divider type voltage setter 2 for setting the address of this transmission slave station S, and its output is connected to the input section of the ADC 16 described above.

FIG. 2 is a flowchart showing the address recognition operation of the CPU 11 when the system of the transmission control LSi 1A shown in FIG. 1 is activated (when the voltage rises). In addition, the following 101-1
Reference numerals 06 indicate steps in FIG. To explain the operation of FIG. 1 using FIG. 2, the supply voltage VC to the transmission slave station S
When C rises, this voltage VCC is also supplied to the transmission control LSi1. When the CPU 11 detects a voltage rise with a voltage rise detection circuit (not shown) (101), it clears its own predetermined register, clears a predetermined area of the RAM 13, transfers data in the ROM 12 to a predetermined area of the RAM 13, etc. Initial processing is executed (102). Next, the ADC 16 is activated (103), and the voltage setting device 2
The address setting voltage (and therefore the converted output value of the ADC 16) is read (104). This address setting voltage is read in, for example, 8 bits, but depending on the precision of the resistor, the lower several bits are discarded and the upper bits are stored in the address storage area on the RAM 13 (105). For example, when a resistor with a precision of ±1% is used, the lower three bits are discarded and the upper five bits are used as the address value. When the series of operations described above is completed, the transmission control LSi1A:
It becomes in a state in which transmission control operations can be executed, and enters an idle state in which it waits for a transmission operation from the master station (106).

Next, regarding the aforementioned resistor voltage divider type address setter (that is, voltage setter), the voltage divider resistor R0 on the power supply side is set to 500KΩ (±
1% or less). In addition, the voltage dividing resistor R1 on the ground side is
Prepare a total of 20 pieces, with a minimum of 100Ω and up to 2KΩ in 100Ω increments. Then, the output voltage value of the voltage setter 2 becomes 20 mV in 1 mV increments from the minimum 1 mV. This voltage is multiplied by 50 using an amplifier not shown, and the full scale becomes 1023 mV.
When input to the ADC 16, 20 addresses can be identified using the upper 5 bits. In this way, transmission control L
One terminal TM1 is connected to Si1A as an address setting terminal.
By simply preparing the , you can set 20 addresses.

FIG. 3 shows the main part of a slave station in which address setting is given by pulses, as an embodiment of the invention according to claims 1, 4, and 5. Within this transmission slave station S,
1 (1B) is a new transmission control LSi, and 3 is a fixed-cycle pulse generator. The internal configuration of this transmission control LSi 1B that differs from that in FIG.
There is no analog-to-digital converter (ADC).

FIG. 4 is a flowchart showing the address recognition operation of the CPU 11 when the system of the transmission control LSi 1B shown in FIG. 3 is started. In the flowchart of FIG. 4, steps 111 to 115 are replaced with those in FIG. Next, the operation of FIG. 3 will be explained based on FIG. 4. The supply voltage VCC to the transmission slave station S in FIG.
Until the i1B CPU 11 completes the initial processing,
The operation is the same as in FIGS. 1 and 2 (101, 102). When the CPU 11 in FIG. 3 completes the initial processing, it sets a predetermined time limit Tms in the timer 15.
(111), immediately reads the contents of the counter (CNT) 17, and sets this counter initial value (CNT0) to R.
Set it in the work area of AM13 (112). Then, wait for the timer 15 to overflow (Tms elapsed) (113, repeat branch N→113). If timer 15 overflows in this way (113, branch Y),
The contents (CNT1) of the counter (CNT) 17 are immediately read out (114), and this value CNT1 is first stored in the RAM 13.
The counter initial value CNT0 that was set in the work area of
is subtracted, and the subtraction result is stored in the address area on the RAM 13 (115). In addition, in this case, depending on the case,
As described later, the address value that has been subjected to a certain conversion is stored in the RAM.
It is stored in the address area above 13.

Next, an example of the configuration of the pulse generator 3 is shown in FIG. In this example (1023/T)KH
An oscillator 31 unique to this transmission system that generates 1023 pulses at the time limit Tms is prepared, and it is connected to a 1/N frequency divider 32 attached to this slave station, and further a 1/4 frequency divider 3.
3 to supply pulses to the transmission control LSi1B. When the value of N is 1 to 16, the count value of the counter (CNT) 17 is the value enclosed by the frame in FIG. That is, at this time, the transmission control LS
By simply preparing one terminal TM1 as the address setting terminal of i1B, 16 addresses can be set. The contents of the counter (CNT) 17 shown in FIG.
Since 16 bits are represented, it is not intuitive. To make this easier to understand, 8 bits → 16 bits (4 bits)
It is a good idea to prepare a conversion table. FIG. 6 shows the structure of this conversion table.

FIG. 7 shows the main part configuration of a slave station according to an embodiment of the invention according to claims 1 and 6, which uses a system in which an address setting is provided by externally processing a signal generated by a transmission control LSi. . The difference between FIG. 7 and FIG. 3 is that the new transmission control LSi1 (1C) has a digital output section (
DO) 18, from which a pulse signal is output and input to the N-ary counter 4 external to this LSi1C, and the output of the N-ary counter 4 is input to the counter (CNT) 17. be.

FIG. 8 is a flowchart showing the address recognition operation of the CPU 11 when the system of the transmission control LSi1C shown in FIG. 7 is started. FIG. 8 shows steps 121 to 1 in contrast to FIG. 4.
Part 27 has been replaced. Next, the operation of the CPU 11 in FIG. 7 will be explained based on FIG. 8. When the supply voltage VCC to the transmission slave station S in FIG. 7 rises, the voltage is also supplied to the transmission control LSi1C as in the case of FIGS. 2 and 4. CPU in Figure 7
11 is a voltage rise detection circuit (not shown) which, when detecting a voltage rise (101), clears its own predetermined register, clears a predetermined area of the RAM 13, and clears the RAM 13.
Initial processing such as transferring ROM data to a predetermined area is executed (102). When this initial processing is completed, the CPU 11 reads the contents of the counter (CNT) 17 and stores this value CNT0 in the work area of the RAM 13 (121). Next, set “1” to the digital output unit (DO) 18 (122), and then set “0” to DO18.
is set (123) and a pulse is generated. This pulse is input to the N-ary counter 4.

The N-ary counter is configured to generate one carry signal (carry signal) 4a when N pulses are input. Therefore, the CPU 11 uses a counter (C
NT) Reads the content CNTN of 17 (124), and subtracts the counter initial value CNT0 previously stored in the work area of the RAM 13 from this CNTN value (125). If the value of (CNTN-CNT0) is not "1" (branch N), the number of operations of DO18 is increased by 1 and RAM1 is
Set it in another work area on 3 (127) and DO again.
18 to output the pulse externally (122, 123
). And again, the contents of counter (CNT) 17 CNTN
(124), and from this CNTN value, RA
Subtract CNT0 stored in the work area of M (1
25). Then, when the value of (CNTN-CNT0) is "1" (branch Y), +1 is added to the contents of the work area on the RAM where the number of operations of DO18 is set, and the value is R
It is stored in the address area on AM13 (126).

As explained above, the N-ary counter 4 in FIG. When a maximum of 64 is required, a 6-bit binary counter can be used. In this way, by preparing a total of two addresses, one address setting terminal TM1 and one auxiliary terminal (DO output terminal) TM2, in the transmission control LSi1C, it is possible to set a larger number of addresses than the original 64. It is.

FIG. 9 shows the main part configuration of a slave station as a modified embodiment of FIG. 1, in which the transmission control LSi is provided with two sets of address setting terminals TM1, TM1-1 and TM1-2. Figure 9
The difference from Figure 1 is the resistor voltage divider type address setter (
There are two sets of voltage setting devices (2-1, 2-2),
These two sets of voltage setting signals are transmitted to a new transmission control LSi1 (1
D) are input to terminals TM1-1 and TM1-2, respectively, and within the transmission control LSi1D, these address setting voltage signals AS1 and AS2 are input to the multiplexer (MPX).
Analog-to-digital converter (ADC) 1 via 19
6.

In the operation of the CPU 11 in FIG. 9, the operation of reading the address setting voltages AS1 and AS2 is performed by the multiplexer 1.
9, except that it is performed twice, once each through
It is exactly the same as FIG. These two sets of address setters 2-
1 and 2-2, the number of addresses that can be set can be dramatically increased by (number of addresses set by the address setting voltage signal AS1) x (number of addresses set by the same signal AS2). For example, if 100 addresses are required, the number of addresses set for both AS1 and AS2 may be set to 10.

[0026] In addition to the above-mentioned method, there are two methods for determining an address using two sets of address setting means.
The method of using two sets of pulse generators 3 unique to each slave station as described above in FIG. Combinations of methods, pulse generation methods, and signal calculation means methods are conceivable.

[0027]

According to the present invention, the address setting terminal TM1 of the transmission control LSi is configured to be used as a multi-value input instead of a binary input. Address setting is now possible. Furthermore, by providing two multi-value input address setting terminals, it is now possible to extremely easily set about 100 addresses. In addition, both the means for generating multi-values and the means for receiving them are a resistor-divided voltage setter and an analog voltage setter.
It can be constructed using very general and simple means such as a digital converter, a pulse generator and a pulse counter, or even an N-ary counter and a pulse counter. As a result, the address setting method is extremely easy to understand and can be realized at a small cost, so it has extremely high industrial value.

[Brief explanation of drawings]

[Fig. 1] A block diagram showing the main part configuration of a slave station as an embodiment of the invention related to claims 1, 2, and 3.

[Fig. 2] Flowchart showing the address recognition operation of the CPU in Fig. 2.

[Fig. 3] A block diagram showing the main part configuration of a slave station as an embodiment of the invention according to claims 1, 4, and 5.

[Fig. 4] Flowchart showing the address recognition operation of the CPU in Fig. 3.

[Figure 5] Explanatory diagram of the configuration and operation of the pulse generator in Figure 3

FIG. 6 is a diagram showing a configuration example of an address conversion table combined with the pulse generator of FIG. 5;

FIG. 7 is a block diagram showing the main part configuration of a slave station as an embodiment of the invention according to claims 1 and 6.

FIG. 8 is a flowchart showing the address recognition operation of the CPU in FIG. 7.

FIG. 9 is a block diagram showing the main part configuration of a slave station as a modified embodiment of FIG. 1;

FIG. 10 is a diagram showing a configuration example of a conventional address setting means.

[
Figure 11: Diagram showing an example of the configuration of a serial transmission system

[Explanation of symbols]

S Transmission slave station L Serial transmission line 1 (1A to 1D) Transmission control LSi 2 (2-1, 2-2) Voltage setting device 3 Pulse generator 4 N-ary counter 11 CPU 12 ROM 13 RAM 14 Serial input/output section ( SIO)15
Timer 16 Analog-to-digital converter (ADC) 1
7 Counter (CNT) 18 Digital output section (DO) 19 Multiplexer (MPX) 31 Oscillator (OSC) 32 1/N frequency divider 33 1/4 frequency divider

Claims (6)

[Claims] Claim 1: An input/output terminal constituting a transmission system, comprising one or more single terminals into which a multi-value signal representing three or more values is input, and the multi-value signal is used to input a multi-value signal to the input/output terminal. A method for setting an address for an input/output terminal, characterized in that an address is set. 2. The address setting method for an input/output terminal according to claim 1, wherein the multilevel signal is an analog voltage. 3. The address setting method according to claim 2, wherein the analog voltage is output from a resistive voltage setting device provided at the input/output terminal. Address setting method. 4. The address setting method for an input/output terminal according to claim 1, wherein the multilevel signal is a pulse output from a pulse generator. 5. The address setting method according to claim 4, wherein the pulse generator is composed of a pulse oscillator specific to this transmission system and a frequency divider provided at the relevant input/output terminal. An address setting method for an input/output terminal characterized by: 6. The address setting method according to claim 1, wherein the input/output terminal is provided with a pulse generating means and an N-ary counter for counting the pulses, and the multi-level signal is output from the N-ary counter. A method for setting an address for an input/output terminal, characterized in that a carry signal is used as a carry signal.