JPH04308457A - Power supply - Google Patents

Abstract

PURPOSE:To provide a power supply in which overshoot and ripples in output waveform can be suppressed without sacrificing the rising rate. CONSTITUTION:At first, a FET Q1 on the primary of a converter transformer T1 is driven with the output from a third counter 8, i.e., a signal having frequency of 100kHz and a duty of 6:4, and when the voltage detected through a voltage detecting circuit 4 exceeds the voltage of a first reference voltage generating circuit 5-1 due to voltage rise at an output terminal P1, the FET Q1 is driven with the output from a fourth counter 9, i.e., a signal having frequency of 200kHz and a duty of 4:6. When the voltage at the output terminal PL further rises to exceed a predetermined level and thereby the voltage detected through the voltage detecting circuit 4 exceeds the voltage of a second reference voltage generating circuit 5-2, driving of the FET Q1 is stopped. Since the driving frequency of converter is switched to a higher one upon rising of the output to the vicinity of peak level so as to improve response, overshoot and ripples in output waveform are suppressed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device for an AC power supply for developing bias in electrophotographic printers and copying machines.

0002

2. Description of the Related Art Conventionally, an AC power source for developing bias often uses a low-frequency step-up transformer. However, in recent years, the duty ratio has been changed to 3:7 or 4:6 rather than square waves.
It has been found that a rectangular wave with a biased duty ratio of 100 nm has better developing characteristics. Therefore, in order to avoid biased magnetism in the transformer and downsize the transformer, the present applicant has proposed a method to obtain a rectangular wave of arbitrary duty by charging the load capacitance with a high frequency converter and discharging it with a high voltage transistor. , has been put into practical use.

0003

[Problems to be Solved by the Invention] In the conventional example of the biased duty developing bias, it was necessary to charge the load capacitance quickly in order to speed up the rise of the output rectangle. For this reason, the converter output must be made high voltage and large power, but this countermeasure actually increases overshoot and ripple.

[0004] In order to solve this problem, a measure has been taken that has achieved considerable results by charging with high power at the initial stage of startup and reducing the power when the output approaches its peak. However,
There was still the fundamental problem that if the throttle was too narrow, the rise speed would drop dramatically near the peak of the output.

The present invention has been made to solve these problems, and it is an object of the present invention to provide a power supply device that can reduce overshoot and ripple in the output waveform without sacrificing the rise speed. be.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention switches the driving frequency of the converter to a higher frequency to increase the response speed when the output rises to near the peak. Specifically, the power supply device is configured as shown in (1) and (2) below.

(1) A converter transformer, comprising a converter transformer, a driving means for driving the primary side of the converter transformer, a control means for controlling the driving means, and a detecting means for detecting the secondary side output of the converter transformer. 2. A power supply device according to the present invention, wherein the control means switches the drive frequency of the drive means to a higher frequency when the output of the detection means exceeds a predetermined value.

(2) a first counter that gradually decreases the reference clock frequency to a first required frequency; and a second counter that generates a signal with a decreased second required frequency and required duty ratio based on the output of the first counter. a third counter that generates a signal having a third required frequency and a required duty ratio that are decreased based on the output of the first counter;
a fourth counter that generates a signal with a required duty ratio at a first required frequency based on the output of the counter; a converter transformer whose primary side is driven by the output of the third counter and the output of the fourth counter; A rectifier connected to the secondary side of the converter transformer, an output terminal connected to the output side of the rectifier for supplying power to a capacitive load, a switching element connected between the output terminal and ground, and an output terminal connected to the output terminal of the converter transformer. a voltage detection circuit connected between the voltage detection circuit and ground; a first comparator that compares the output of the voltage detection circuit with a first reference voltage; and a second comparator that compares the output of the voltage detection circuit with a second reference voltage. a comparator, a third counter output, and a fourth counter output that are supplied to the primary side of the converter transformer according to the output of the first comparator, the output of the second comparator, and the output of the second counter. control,
and control means for controlling the switching element with the output of the second counter, the control means controlling the switching element until the output of the voltage detection circuit reaches the first reference voltage. The output of the counter No. 3 is supplied to the primary side of the converter transformer, and when the output of the counter No. 3 exceeds the first reference voltage and the second
Until the reference voltage reaches the reference voltage, the output of the fourth counter is supplied to the primary side of the converter transformer instead of the output of the third counter, and when the second reference voltage is exceeded, the output of the fourth counter is supplied. A power supply device that stops supplying power to the primary side of the converter transformer.

[0009]

[Operation] With the configurations (1) and (2) above, when the output exceeds a predetermined value, the drive frequency of the converter transformer is switched to a higher frequency, reducing overshoot and ripple in the output waveform.

0010

[Examples] The present invention will be explained in detail below using examples. (Embodiment 1) FIG. 1 is a block diagram of a "developing bias power source" according to Embodiment 1, and FIGS. 2 and 3 are voltage waveform diagrams of each part thereof. In FIG. 1, 1 is a microcomputer (hereinafter referred to as CPU) which also includes peripheral devices such as memory. The CPU 1 is connected to a sequence controller (not shown) of a main body of a printer (copying machine) through a bus line or a communication port, and exchanges sequence signals. The first counter 6 converts the reference clock of the CPU 1 into f1 (200K
Hz). The second counter 7 further receives a low frequency signal with a repetition frequency f2 (2 KHz) and a duty of 7:3, and the third counter 8 receives a low frequency signal with a repetition frequency f3 (10
The fourth counter 9 generates a high frequency signal with a frequency f1 (200 KHz) and a duty of 4:6.

The switching element Q1 (FET) on the primary side of the high frequency converter transformer T1 is connected to the FET drive circuit 2.
controlled by The outputs of the third counter 8 and the fourth counter 9 are switched and inputted to the FET drive circuit 2 by the CPU 1.

After being rectified by a rectifier D1, the boosted output from the secondary side of the converter transformer T1 charges the load capacitor connected to the output terminal P1, as shown in FIG. 2(c). The output voltage of the output terminal P1 is divided into a predetermined ratio by the voltage detection circuit 4 and inputted to the comparators 3-1 and 3-2. Comparators 3-1 and 3-2 compare the voltage detection output with the voltages of reference voltage generation circuits 5-1 and 5-2 (hereinafter referred to as first reference voltage and second reference voltage) and output the comparison results. Output to CPU 1. When the output detection voltage reaches the first reference voltage, the input of the FET drive circuit 2 is switched from the output of the third counter 8 (f3, 100 KHz) to the output of the fourth counter 9 (f1, 200 KHz). . When the output detection voltage reaches the second reference voltage, the FE
The input to the T drive circuit 2 is stopped. FET drive circuit 2
When the output of the output terminal P1 stops, the level of the output of the output terminal P1 decreases due to discharge of the load capacitance. When the output detection voltage falls below the second reference voltage, the output of comparator 3 is inverted and F
Input to the ET drive circuit 2 is started again. The above operation is shown in FIG. 3 when the time axis is expanded. As shown in the figure, when the output voltage changes to a voltage corresponding to the first reference voltage,
Since the driving state of the FET driving circuit 2 becomes finer, overshoot and ripple in the output voltage are reduced.

The high voltage transistor Q2 is shown in (c) in FIG.
As shown in FIG. 3, it is turned on and off in synchronization with the output of the second counter 7. When the high voltage transistor Q2 is on, the PWM output is stopped.

The frequencies f1, f2, f3, the duty of each counter output, and the first and second reference voltages are set in advance by the CPU.
It is determined based on the data stored in the ROM in 1.

By the way, the output of a converter transformer decreases at high frequencies due to its frequency response characteristics, so unless the drive frequency is kept at a predetermined value, the required rise cannot be obtained. On the other hand, the control characteristics for the reference voltage are determined by the drive frequency of the converter, and when the drive frequency is low, overshoot and ripple become large. For this reason, even if the output is reduced by narrowing the pulse width near the peak of the output as in the conventional example, overshoot and ripple cannot be essentially reduced except by sacrificing the rise speed. However, in this embodiment, the converter output is not only reduced near the peak of the output, but also the converter drive frequency is switched to a higher frequency, so overshoot can be prevented without sacrificing the rise speed.
It becomes possible to reduce ripple.

(Embodiment 2) FIG. 4 is a block diagram of Embodiment 2. In the first embodiment, the outputs of the counters 7, 8, and 9 are once inputted to the FET drive circuit 2 via the CPU 1, but the response speed becomes slow due to the input via the CPU 1, causing ripples and overshoot. cause it to increase.

In order to prevent this, in this embodiment, the AND circuits 22-1, 22-2 and the OR circuit 23 are connected to the third and fourth counters 8, 9 and the first and second comparators 3-1, 3.
-2 outputs are combined and inputted to the FET drive circuit 2 to increase the response speed and minimize ripple and overshoot.

That is, until the voltage at the output terminal P1 starts to rise and the detected voltage of the voltage detection circuit 4 reaches the reference voltage of the comparator 3-1 (corresponding to the first reference voltage of the first embodiment), the comparator 3 -1 and 3-2 outputs are both “H”
However, the outputs of the comparator 3-2 and the fourth counter 9 are blocked by the AND gate 22-2 by the inverter 24, and the outputs of the comparator 3-1 and the third counter 8 are blocked by the AND circuit 22-1 and the OR circuit. The signal is supplied to the FET drive circuit 2 via 23. Furthermore, the voltage of the output terminal P1 increases, and the detected voltage of the voltage detection circuit 4 becomes the voltage of the comparator 3-1.
exceeds the reference voltage, the output of comparator 3-1 becomes “
"L", and the AND circuit 22- through the inverter 24
"H" is supplied to FET drive circuit 2, and only the outputs of comparator 3-2 and fourth counter 9 are supplied to FET drive circuit 2. When the detected voltage of the voltage detection circuit 4 exceeds the reference voltage of the comparator 3-2 (corresponding to the second reference voltage of the first embodiment),
The output of the comparator 3-2 also becomes "L", and the output of the FET drive circuit 2 is stopped. When the voltage of the output terminal P1 decreases due to discharge of the load capacitance and the detected voltage of the voltage detection circuit 4 becomes lower than the reference voltage of the comparator 3-2, the comparator 3
The output of -2 is inverted to "H" and input to the FET drive circuit 2 is started again. In this way, the same effect as in Example 1 is performed with a faster response speed.

In the above embodiment, the first and second reference voltages, the output frequencies and duty ratios of the first, second, third and fourth counters are fixed, but the present invention However, the present invention is not limited to these, and can be implemented by appropriately setting them through built-in programming of the CPU 1.

Further, a comparator, a counter, a D/A converter, etc. can be integrated on the same chip together with a CPU and peripheral circuits.

Furthermore, the present invention can be implemented using a power source other than the developing bias power source, and in this case, the output current can also be controlled.

[0022]

[Effects of the Invention] As explained above, according to the present invention,
When the output rises to near its peak, the drive frequency of the converter is switched to a higher frequency, so overshoot and ripple in the output waveform can be reduced without sacrificing the rise speed.

[Brief explanation of drawings]

[Figure 1] Block diagram of Example 1

[Figure 2] Voltage waveform diagram of each part of Example 1

[Figure 3]
Enlarged view of the time axis of the output rise part in Figure 2

[Figure 4] Block diagram of Example 2

[Explanation of symbols]

1 CPU 2 FET drive circuit 3-1 First comparator 3-2 Second comparator 4 Voltage detection circuit 6-9 counter D1 Rectifier Q2 High voltage transistor T1 converter transformer 22-1, 22-2 AND circuit 23 OR circuit 24 Inverter

Claims (2)

[Claims] 1. A converter transformer, a drive means for driving a primary side of the converter transformer, a control means for controlling the drive means, and a detection means for detecting a secondary side output of the converter transformer. A power supply device,
The power supply device is characterized in that the control means switches the drive frequency of the drive means to a higher frequency when the output of the detection means exceeds a predetermined value. 2. A first counter that reduces a reference clock frequency to a first required frequency; and a second counter that generates a signal having a reduced second required frequency and a required duty ratio based on the output of the first counter. a third counter that generates a signal with a reduced third desired frequency and a desired duty ratio based on the output of the first counter; A fourth counter that generates a duty ratio signal, a converter transformer whose primary side is driven by the output of the third counter and the output of the fourth counter, and two of the converter transformers.
A rectifier connected to the next side, an output terminal connected to the output side of the rectifier and supplying power to a capacitive load, a switching element connected between the output terminal and ground, and a switching element also connected between the output terminal and ground. a first comparator that compares the output of the voltage detection circuit with a first reference voltage; a second comparator that compares the output of the voltage detection circuit with a second reference voltage; The output of the third comparator is supplied to the primary side of the converter transformer according to the output of the first comparator, the output of the second comparator, and the output of the second counter.
and a control means for controlling the output of a fourth counter and the output of a fourth counter, and controlling the switching element with the output of a second counter, the control means comprising: The output of the third counter is supplied to the primary side of the converter transformer until the output of the third counter reaches the first reference voltage, and the output of the third counter is supplied to the primary side of the converter transformer until the output of the third counter exceeds the first reference voltage and reaches the second reference voltage. Instead of the output of the third counter, the output of the fourth counter is
1. A power supply device that supplies the output of the fourth counter to the primary side of the converter transformer and stops supplying the output of the fourth counter to the primary side of the converter transformer when the voltage exceeds the second reference voltage.