JPH04307624A - Loop optimization system - Google Patents

Abstract

PURPOSE:To assure the effective operation of a loop optimization system by deciding the number of loop evolving stages having the highest effect of parallelism in consideration of the characteristic of each loop contained in a program and with the use of a computer which can carry out plural instructions at the same time. CONSTITUTION:A loop analyzing part 24 is provided to check the data reference relation among the loops together with a loop evolving stage number deciding part which decides the number of loop evolving stages having no superposition of addresses among the data based on the analyzing result of the part 24, and a loop optimizing part which performs the evolution of loops and the scheduling of a list based on the deciding result of the loop evolving stage number deciding part. Furthermore the part 24 checks the number of operations and the number of working registers within each loop. Then the loop evolving stage number deciding part decides the number of loop evolving stages where the types of operations are distributed most properly with the proper number of registers based on the checking result of the part 24.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loop optimization method in an electronic computer that allows a plurality of sequences of instructions to be executed in parallel.

0002

2. Description of the Related Art Conventionally, electronic computers have been constructed on the premise that instruction sequences are processed sequentially, and electronic computers have taken out instructions one by one and executed them accordingly.

Pipeline technology has been introduced to speed up the processing of this instruction sequence. This is a technology that decomposes the execution of an instruction into multiple stages, and uses these decomposed execution stages as a unit to simultaneously calculate multiple instructions at different stages.This makes it possible to shorten the processing cycle time. The processing time for the entire instruction sequence has also been reduced. However, even in the pipeline technology, only one instruction is started per cycle, and instructions beyond this limit have not been executed in parallel.

On the other hand, in recent years, technology has been introduced that enables parallel execution on an instruction-by-instruction basis.
It has become possible to process more than one instruction. VLIW (Very Long Instrument)
There are two representative methods: on Word) technology and superscalar technology.

[0005] In the VLIW technology, a predetermined number of instructions are defined as one execution unit, and a computer always executes these instructions simultaneously. Since the computer does not need to determine whether multiple instructions to be processed can be executed simultaneously, and the control is simple, it can be implemented with a small amount of hardware, and the cycle time can be shortened. However, the parallelism of processing must be determined by a compiler or manually, and instructions must be allocated in advance. This instruction assignment is called "instruction scheduling."

On the other hand, superscalar technology is equipped with hardware that examines the possibility of parallel execution by interpreting a sequence of instructions that are assumed to be executed sequentially, as in the past, and if parallel execution is possible, these multiple instructions are executed in parallel. This is a method of controlling the Since this method relies on dedicated hardware to determine whether instructions can be executed in parallel, it is guaranteed that even ordinary programs can be executed while maintaining compatibility with sequential execution. However, when actually aiming to improve performance using the superscalar method, instruction scheduling similar to the VLIW method is used to ensure that the arithmetic unit is as active as possible based on information such as hardware resources and data dependencies. It is essential to go.

[0007] As an instruction scheduling method in these parallel execution systems, instructions are processed based on constraints such as hardware resources and data dependencies, with one basic block (a sequence of instructions without branches or escapes in the program) being processed. "List scheduling" to sort
A method called ``is known. Although this method is easy to implement, it also has the drawback that in general programs, the number of instructions included in one basic block is limited, and therefore sufficient performance improvement cannot be achieved. In order to eliminate this drawback,
When targeting a loop portion of a program, a technique called ``loop unrolling'' may be used in combination, in which the operations within the loop are expanded and processed over multiple iterations. It is also well known that processing loop portions in this manner can provide higher parallelism than applying list scheduling alone.

This "loop unrolling" is a method of unrolling and processing a plurality of adjacent loop iterations. For example, C
Consider loop diagram 3(a) described in language. If this loop is directly converted to assembler, the result shown in FIG. 3(b) is obtained. When this loop is subjected to four stages of loop expansion, the loop shown in Fig. 4(a) is obtained. In the loop unrolling process, four iterations of the loop are combined into one loop iteration to form an equivalent loop. When this loop is converted to assembler, the result shown in FIG. 4(b) is obtained.

As can be seen from the compilation results of the above two loops, the number of instructions subject to instruction scheduling within the loop increases from 7 in FIG. 3(b) to 16 in FIG. 4(b) due to loop unrolling. . Furthermore, in this example, since the operations (sub) at each stage of the loop can be executed independently, it can be converted into a parallelized program suitable for VLIW and superscalar methods by instruction scheduling. A loop optimization technique that processes such loop unrolling inside a compiler without modifying the source program is generally used.

[0010] Although this method of reconfiguring the instruction sequence by combining loop unrolling and list scheduling can achieve higher parallelism than conventional methods, on the other hand, the size of the object program increases due to loop unrolling. There was a drawback to it.

[0011] Furthermore, this method of combining loop unrolling and list scheduling is not necessarily universal. For example, when the data reference relationship within the loop is circular (data recursion), as in the loop shown in Figure 5(a), the loop is unrolled in order to use the results of the previous iteration for the next calculation. However, operations cannot be multiplexed between the two iterations before and after, and the parallelization effect cannot be achieved much. In fact, if you look at Figure 5(b), which is the result of applying four stages of loop unrolling to Figure 5(a) and converting it to assembler, you can see that the number of instructions in the loop has increased, but due to data recursion, there are four s
The ub instructions must be executed sequentially in nature. That is, since sub of (*) has the calculation result of sub of (**) as an operand, it must not be executed until (**) is completely completed. For this reason, there is a problem in that such a loop cannot achieve high parallelization performance even in a VLIW or superscalar computer having a plurality of arithmetic units.

[0012] Also, depending on the code generation method of the compiler, an induction variable (k in this example) may be added to the loop as shown in Figure 6.
Even if there is an array reference that is accessed with , even if loop unrolling is performed, multiplexing of operation execution may be hindered due to induction variable calculation in each stage.

In other words, as shown in FIGS. 5 and 6 above,
If the target is a loop for which the effect of loop unrolling is small, even if conventional loop unrolling processing is performed, the object code size will simply increase and sufficient parallelization effect will not be obtained, and the effective operation of the system will not be achieved. It was becoming an obstacle.

Furthermore, in addition to the above-mentioned problems, the method of reconfiguring the instruction sequence by combining loop unrolling and list scheduling has problems when multiple processing units of a computer are used when the types of operations in the loop are biased. The drawback was that it could not be used effectively and performance did not improve much. That is,
Efficient parallel execution is not possible because the ratio of the number of operations for each type of operation (integer operation, floating point operation) in the loop is not as close to the ratio of the number of operation units of the computer as possible. There wasn't.

This will be explained using FIG. 9 as an example. Considering that the loop shown in Figure 9(a) is executed on a computer with two integer calculation units and one floating-point calculation unit, when the number of loop unrolling stages is changed, the number of integer calculations and floating-point calculations in the loop is The number of operations changes as shown in FIG. 9(b). The closer the ratio of the number of integer operations to the number of floating point operations is to the ratio of the number of integer units to the number of floating point units, the higher the possibility that efficient scheduling will be obtained. In fact, when instruction scheduling is performed by changing the number of loop unrolling stages in the program shown in Figure 9(a), the number of instructions per cycle within the loop changes as shown in Figure 9(b), which is the number of integer operations/floating The optimum value is obtained when the decimal point operation number ratio is close to the operation unit number ratio.

[0016] Furthermore, when performing this combination of loop unrolling and list scheduling, if the loop is unrolled over a certain number of stages, the number of registers used within the loop may exceed the number of registers possessed by the computer. In this case, there are no registers available, so the value is saved to the stack (this situation is called a ``register overflow''). Generally speaking, accessing the stack is inefficient, so if such a register overflow occurs, performance will deteriorate even though loop unrolling has been performed. In fact, looking at FIG. 9(b) for the program shown in FIG. 9(a), when the number of loop unrolling stages is 12 or more, register overflow occurs and the performance deteriorates.

In other words, in order to effectively apply "loop unrolling", as shown above, the optimal number of unrolling stages must be determined based on the number of operations in the loop and the number of registers used in the loop. However, until now, it has not been possible to perform flexible loop unrolling processing that takes advantage of this information.

[0018]

[Problem to be solved by the invention] In this way, conventional VL
IW, in the combined optimization method of loop unrolling and list scheduling proposed for the superscalar method, it is impossible to freely switch the instruction scheduling method according to the characteristics of the program loop itself.
As a result, although the parallelization effect is not so great, the object code size becomes enormous due to the multiple unrolling of loops, which has the disadvantage that the efficient operation of the system may be hindered. Furthermore, because the ratio of the number of operations of the type of operation and the number of operation units of the computer are greatly different, the hardware of the computer cannot be used effectively and a sufficient parallelization effect cannot be obtained, or the number of loop unrolling stages is increased. If the settings are set too high, register overflow occurs and performance deteriorates, which hinders the efficient operation of the system.

The present invention has been made in consideration of such circumstances, and its purpose is to take into account the characteristics of each loop in a program, and to refer to data within the loop.
Processing is performed after determining the number of loop unrolling stages that has the highest parallelization effect and prevents unnecessary increase in object code according to the update relationship. Guarantees effective system operation by determining the number of registers to be used and determining the optimal number of loop unrolling stages that has the highest parallelization effect and does not cause register overflow according to the number of arithmetic units of the computer. The objective is to provide a loop optimization method that [Structure of the invention]

[0020]

[Means for Solving the Problems] A loop optimization method according to the first invention includes a loop optimization unit that performs combined optimization of loop unrolling and list scheduling, and a loop optimization unit that performs a combination optimization of loop unrolling and list scheduling, and a loop optimization unit that performs a combination optimization of loop unrolling and list scheduling, and In addition, there is a loop analysis section that calculates the minimum loop iteration difference where addresses overlap with each other, and a loop that determines the number of loop unrolling stages that can achieve the maximum parallelization effect with the minimum object code size based on the detection results of this loop analysis section. The present invention is characterized in that it includes an unrolling stage number determining section, and performs loop unrolling and list scheduling to optimize the loop portion based on the determination result of the loop unrolling stage number determining section.

[0021] The loop optimization method according to the second invention includes a loop optimization unit that performs combined optimization of loop unrolling and list scheduling, and a loop optimization unit that performs a combination optimization of loop unrolling and list scheduling, and a loop optimization unit that performs a combination optimization of loop unrolling and list scheduling, and a loop optimization unit that performs a combination optimization of loop unrolling and list scheduling, and A loop analysis section that calculates the number of registers, the number of integer operations, the number of floating point operations, the number of integer registers to be used, and the number of floating point registers when applying loop unrolling processing, and the calculation of the computer based on the output results of this loop analysis section. and a loop unrolling stage number determination unit that determines the optimal number of loop unrolling stages that can use the hardware most effectively and does not cause register overflow, taking into account the number of integer units, the number of floating point units, and the number of registers. The present invention is characterized in that loop unrolling and list scheduling are performed to optimize the loop portion based on the determination result of the loop unrolling stage number determination unit.

[0022]

[Operation] According to the first invention, data reference overlap information between loop iterations is obtained in advance from the data reference relationship in each loop part in the program, array access format, etc., and the optimal number of loop unrolling stages is determined based on this. Then, loops are unrolled and instructions are rearranged, so while the parallelization performance of loops that can obtain a high parallelization effect with the conventional method is maintained, it is also , it is possible to minimize the increase in object code size due to loop unrolling.

According to the second invention, the number of integer/floating point operations for each loop in the program and the number of integer/floating point registers used in the loop are determined in advance, and based on this, the number of arithmetic units and the number of arithmetic units possessed by the computer are calculated. Since the optimal number of loop unrolling stages is determined in consideration of the number of registers and the loop is unrolled and instructions are rearranged, performance can be improved even for loops for which conventional methods cannot achieve sufficient parallelization effects. In addition, performance degradation due to register overflow can be prevented.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. ○Example 1

FIG. 1 is a diagram showing the configuration of a compiler to which a loop optimization method according to an embodiment of the present invention is applied. The compiler includes a program input section 21, a syntax analysis section 22,
Loop extraction section 23, loop analysis section 24, loop expansion section 2
5, an instruction schedule section 26, and a code generation section 27.

The source program read by the program input section 21 is converted into intermediate text by the syntax analysis section 22 and input to the loop extraction section 23 . Loop extraction section 23
examines the input intermediate text, detects and extracts the loop part in the program, and sends this content to the loop analysis section 2.
Pass it to 4.

The loop analyzer 24 examines the reference and update addresses of each data appearing in the loop, and examines whether there is a case where a data value generated in one iteration is used in a subsequent iteration. If there is such address overlap, the difference in the number of loop iteration stages where addresses overlap (this value is hereinafter referred to as the "minimum address overlap iteration difference").
is determined and notified to the loop unrolling unit 25.

[0028] For this analysis, a data dependence analysis method may be used in which subscript expressions of arrays that commonly appear on the left and right sides of the loop are checked to see if they can take a common value. In languages that use pointer variables, similar analysis can be performed by tracking changes in pointer values. This data dependence analysis part may be configured as desired depending on the language to be processed and the optimization request specifications.

For example, in the case of the loop shown in FIG. 7A, it can be recognized that data x[i] defined in loop iteration i is referenced in the second subsequent iteration. In this case, the loop analyzer 24 calculates the iteration difference 2 that causes the minimum data address overlap.
is notified to the loop unrolling unit 25. Similarly, in the case of FIG. 8, the data x[i] defined in loop iteration i is referenced in the next iteration, so the loop analysis unit 24 notifies the minimum address overlap iteration difference 1.

The loop unrolling unit 25 performs loop unrolling processing based on the minimum address overlap repetition difference notified here. At this time, if the loop analysis unit 24 notifies the minimum address overlap repetition difference M, the loop is expanded only up to M stages at most. Therefore, for the loop in Figure 7(a), one or two stages of loop unrolling are performed, but three
Do not expand beyond a stage. Also, for the loop in Figure 8, 1
stage only, so loop unrolling is not applied at all.

In fact, even if the loop in FIG. 7(a) is expanded in three or more stages, or the loop in FIG. It is difficult to increase For example, when the two-stage loop is expanded in Figure 8, two sub instructions need to be executed sequentially as in Figure 5, so these instructions cannot be processed in parallel and a high-performance parallel program cannot be achieved. I can't do it. On the other hand, when FIG. 7(a) is expanded into a two-stage loop according to the determination result of the loop analysis unit 24, the assembler output is as shown in FIG. 7(b), but in this case, two sub
Since the instructions process independent data, they can be freely executed in parallel, making it possible to construct parallel programs with good performance. The intermediate text loop-optimized in this manner is translated into machine language by the code generator 26 and output as an object program.

FIG. 2 is a diagram showing the configuration of a compiler to which a loop optimization method according to another embodiment of the present invention is applied. This compiler has a program input section 31 similar to that shown in FIG.
, syntax analysis section 32, loop extraction section 33, loop analysis section 3
4. In addition to a loop unrolling section 35, an instruction scheduling section 36, and a code generation section 37, the system includes an inductive variable analysis section 38.

This embodiment is applied when the improvement in parallelization performance in loop unrolling is hindered by array access involving induction variables calculated at each iteration of a loop as shown in FIG. In this case, the loop unrolling unit 35 determines whether to perform loop unrolling based on the determination result of the loop analysis unit 34 and the determination result of the inductive variable analysis unit 38.

[0034] The induction variable analysis unit 38 includes the loop extraction unit 33
Each data of the in-loop intermediate text inputted from is examined, and if an induction variable k as shown in FIG. 6 appears, the loop expansion unit 35 is notified of this fact. When the loop unrolling unit receives this notification, it optimizes the loop by not unrolling the loop.

Note that this method also has the side effect of shortening the program compilation time and optimization time because unnecessary loop unrolling is not performed, so that the system can be used more effectively. ○Example 2

FIG. 11 shows the configuration of a compiler to which the loop optimization method according to this embodiment is applied. The compiler is
program input section 11, syntax analysis section 12, loop extraction section 13, loop analysis section 14, loop unrolling stage number determination section 15,
It is composed of a loop unrolling section 16, an instruction scheduling section 17, and a code generation section 18.

The source program read by the program input section 11 is converted into intermediate text by the syntax analysis section 12 and input to the loop extraction section 13 . Loop extractor 13
examines the input intermediate text, detects and extracts the loop part in the program, and sends this content to the loop analysis section 1.
Pass it to 4. It is.

The loop analysis unit 14 in this embodiment analyzes intermediate text to determine the number of integer operations, the number of floating point operations, and the number of integer registers and floating point registers used within the loop. For example, Fig. 9(a)
The in-loop operation expressed in tree-format intermediate text is shown in FIG. The loop analysis unit 14 traces these intermediate texts and finds that each tree does not overlap (
The number of operations and the number of registers are determined by assuming that the end nodes (corresponding to different data objects) are registers and the intermediate nodes are operations. Also, at this time, the number of integer/floating point operations and the number of integer/floating point registers are individually determined from the operation type information. In addition, the number of operations for evaluating the loop exit condition is separately determined. Furthermore, if necessary in consideration of the code generation method, the number of integer/floating point temporary registers may be determined assuming that temporary registers are used for intermediate nodes. The respective values for FIG. 10 are as follows: Number of integer operations = 0 Number of floating point operations = 16 Number of address calculations and branch calculations = 4 Number of integer registers = 1 (loop variable k) Number of floating point registers = 12. The loop unrolling stage number determining unit 1 uses the calculated information as
Notify 5.

The loop unrolling stage number determination unit 15 determines the optimal number of loop unrolling stages that will not cause register overflow and will provide the number of operations suitable for the configuration of the computer, based on the output information of the loop analysis unit 14 and hardware information. . Hardware information includes the number of integer units, floating point units, integer registers, floating point registers, integer temporary registers, floating point temporary registers, number of delay cycles for each operation, etc., computer configuration, code, etc. It is given depending on the generation method etc. Furthermore, the hardware information may be registered inside the compiler as information for a specific computer, or may be given as an option when starting the compiler, and in the present invention, any format for inputting the hardware information can be used. It doesn't matter.

Below, there are 2 integer units, 1 floating point unit, 32 integer registers, and 3 floating point registers.
The following explanation assumes a computer in which an integer load instruction has a delay of 1 cycle, a floating point load instruction is also executed in an integer unit and has a delay of 2 cycles, and a floating point operation has a delay of 2 cycles. In order to obtain the optimal number of loop unrolling stages based on the information obtained by the loop analysis section 14, the following calculation is performed.

First, the number of operations when loop unrolling is performed n stages is calculated based on the number of integer operations, the number of floating point operations, the number of integer registers, and the number of floating point registers. The number of registers is used to take into account the cycles in which the arithmetic unit is used in load instructions. Generally, when performing loop unrolling, address addition of arrays within the loop is performed at once for n stages. In addition, the evaluation calculation of the loop termination condition is reduced to once for every n stages, so in the case of a loop that includes a mixture of integer operations and floating point operations, as the number of loop unrolling stages increases, the ratio of integer operations to all operations will decrease. . The integer arithmetic number IOP is I
OP = (Number of integer operations + (Number of integer registers) * 2 + (
Number of floating point registers) *3) * (Number of loop unrolling stages) +
(address, number of branch operations). Here, (number of integer registers) *2 is an integer load instruction that is executed with a one-cycle delay, and (number of floating-point registers) *3 is an integer unit that is used for a floating-point load instruction that is executed with a two-cycle delay. It approximates a cycle. Similarly, floating point arithmetic number FO
P is determined by FOP = number of floating point operations * 3 * (number of stages of loop unrolling). *3 indicates that the floating point arithmetic instruction is executed with a two-cycle delay.

From these values, IFrate=IOP*2/FOP is calculated for each loop unrolling stage number. Since the hardware has two integer units and one floating point unit, the closer IFrate is to 1, the more each type of instruction distribution is adapted to the hardware. At the same time as evaluating the number of operations, the number of registers is also evaluated. In this case, the loop analysis unit 14 further analyzes the obtained register nodes to calculate the number of independent scalar variable nodes and independent array variable nodes. Here, the independent array variable means, for example, if we look at the assembler program for the loop in Figure 3(a) in Figure 3(b), the array y[i] has a register reserved in advance outside the loop ($f2), In the loop y[i+1
] only the register ($f0) is used. When moving to the next stage, values are copied using an inter-register move instruction (mov). In this way, the same array that is accessed with a constant value offset from the loop control variable i can be allocated in one register, so it is counted as corresponding to one register. Array x is an independent array variable because a register is used separately from this. In the program shown in FIG. 9, there are four independent array nodes: X, Y, Z, and U. When calculating the number of registers used in this way, the number of integer registers IREG is IREG = (number of independent integer array nodes) * number of loop unrolling stages + (total number of integer nodes - number of independent integer array nodes)

004
3) An independent integer array node requires another register when the loop is unrolled, so it is multiplied by the number of loop unrolling stages, but other scalar variables do not change within the loop, so one register is sufficient. represents. Similarly, the number of floating point registers FREG is as follows: FREG = (number of independent floating point array nodes) * number of loop unrolling stages + (total number of floating point nodes - number of independent floating point array nodes). The number of loop unrolling stages is determined within the range where the number of these registers does not exceed the number of registers possessed by the computer. FIG. 12 shows a flowchart of the optimal loop expansion stage number determination portion, which combines the number of operations and the number of registers, as described above.

[0044] In this embodiment, a method of evaluating only variable registers has been described, but the register allocation method is fixed, the register usage pattern is also fixed, and certain temporary registers are used. If it is determined, a temporary register may be assigned to the intermediate node of the operation tree, and it may be added to the evaluation.
The arithmetic units may also be further subdivided to uniquely evaluate integer units, floating point addition/subtraction units, floating point multiplication units, etc.

The loop unrolling unit 16 performs loop unrolling processing using the optimum loop unrolling stage number notified from the loop unrolling stage number determination unit 15. When loop unrolling is performed with the notified number of unrolling stages, it is possible to obtain an instruction sequence that best matches the configuration of the number of hardware resources of the computer and the configuration of operations in the unrolled loop without causing register overflow. By rearranging the instructions in the instruction scheduler 17, efficient parallel execution can be performed. The intermediate text loop-optimized in this manner is translated into machine language by the code generator 18 and output as an object program.

Note that this method is applicable regardless of the hardware configuration of the computer used. That is, by simply exchanging the hardware parameters used in the loop unrolling stage number determining section, it is possible to determine the optimum number of loop unrolling stages without changing the internal control at all, and it is applicable to a very wide range of computers.

[0047] Furthermore, embodiment 1 and embodiment 2 can also be implemented in combination. In this case, for example, the loop unrolling stage number determination unit 15 of the second embodiment calculates the minimum difference M in the number of repetition stages at which addresses overlap between reference or update data, which was determined by the loop analysis unit 24 of the first embodiment, and shall be the upper limit when determining. Then, the number of loop unrolling stages determined by the unrolling stage number determination unit 15 is determined to maximize the number of units in the computer without overlapping addresses between reference or update data and without register overflow. It can be used effectively.

[0048]

As explained above, according to the present invention, the data address overlap between different loop iterations is determined in advance from the data reference relationships, array access formats, etc. in each loop part in the program, and based on this, the optimal Since the loop is unrolled and the instructions are rearranged after determining the number of loop unrolling stages, the loop parallelization performance that can be achieved with the conventional method is maintained, while the parallelization efficiency is not so great with the conventional method. For loops that do not increase, a loop optimization method can be used to minimize the increase in object code size due to loop unrolling. Furthermore, the number of integer/floating point operations for each loop in the program and the number of integer/floating point registers used within the loop are determined in advance, and based on this, the optimal loop is determined by considering the number of arithmetic units and registers of the computer. Since the number of unrolling stages is determined and the loop is unrolled and instructions are rearranged, the performance can be improved even for loops for which sufficient parallelization effects cannot be obtained using conventional methods, and performance degradation due to register overflow can be prevented. It is possible to provide a loop optimization method that can prevent this.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of a compiler to which a loop optimization method according to a first embodiment of the present invention is applied.

FIG. 2 is a diagram showing another configuration example of a compiler to which the loop optimization method according to the first embodiment of the present invention is applied.

[Fig. 3] (a) is a source program showing a loop to be processed by the loop optimization method according to the present invention, (b)
) is a diagram representing an assembler program showing the result of compiling the program in (a).

4(a) is a source program showing a loop obtained by performing four stages of loop expansion in FIG. 3(a), and FIG. 4(b) is a diagram showing an assembler program showing the result of compiling the program in FIG. 3(a).

[Figure 5] (a) is a source program showing a loop that includes data recursion inside, (b) is (a)
The figure which shows the assembler program which shows the result of compiling the program by four stage loop expansion.

FIG. 6 is a diagram illustrating a source program showing a loop that includes induction variable access within the loop.

[Figure 7] (a) shows that the minimum address overlap repetition difference is 2.
A source program showing a loop with (b) is (a
) program according to the judgment results of the loop analysis section.
The figure which shows the assembler program which shows the result of stage loop expansion and compilation.

FIG. 8 is a diagram representing a source program showing a loop in which the minimum address overlap iteration difference is 1.

[Fig. 9] (a) is a source program showing a loop to be processed by the loop optimization method according to the present invention, (b)
) is the number of integer operations, the number of floating point operations, when the program in (a) is compiled with different numbers of loop unrolling stages,
FIG. 7 is a diagram showing the number of instructions per cycle in a loop when instruction scheduling is performed.

FIG. 10 is a diagram showing tree format intermediate text of the loop portion of the program in FIG. 9(a).

FIG. 11 is a diagram showing a configuration example of a compiler to which a loop optimization method according to a second embodiment of the present invention is applied.

FIG. 12 is a flowchart of a process for determining the optimal number of loop expansion stages in a loop optimization method according to a second embodiment of the present invention.

[Explanation of symbols]

21 Program input section 22 Syntax analysis section 23 Loop extraction section 24 Loop analysis section 25 Loop expansion section 26 Instruction schedule section 27 Code generation section 31
Program input section 32 Syntax analysis section
33 Loop extraction section 34 Loop analysis section
35 Loop unrolling section 36 Instruction schedule section
37 Code generation section 38 Inductive variable analysis section

Claims (3)

[Claims] 1. A loop optimization method used in an electronic computer capable of executing in parallel a plurality of instruction sequences constituting a program including loop processing in which a sequence of instructions is executed by repeating a plurality of times. The first iterative stage and the second iterative stage have an overlap between the address of the data to be referenced or updated in the iterative stage and the address of the data to be referenced or updated in the second iterative stage in the loop processing.
a program analysis means for determining the minimum step difference between the steps of the repetition step; , a program conversion means for converting the instruction sequence into an instruction sequence equivalent to the instruction sequence in the loop, and a program execution means for executing in parallel the instruction sequence for the number of repetitions expanded in one loop by the program conversion means. A loop optimization method characterized by: 2. The loop optimization method according to claim 1, wherein the program analysis means is provided with an instruction sequence that refers to or updates data using an induction variable that is newly calculated at each iteration stage in the loop processing. A loop optimization method characterized in that a control means is added to prevent the included loop from being expanded by the program conversion means. 3. In a loop optimization method used in an electronic computer capable of executing in parallel a plurality of instruction sequences constituting a program including a loop process in which a sequence of instructions is executed by repeating a plurality of times, the loop processing is performed by loop unrolling. A first step for detecting the number of loop unrolling stages when unrolling within the same loop by the number of stages, and the number of integer operations and the number of floating point operations included in the instruction sequence within the same loop when unrolling is performed with this number of loop unrolling stages. detection means, the number of loop unrolling stages when the loop processing is unrolled within the same loop by the number of loop unrolling stages, and the number of integer registers used within the same loop when unrolling is performed with this number of loop unrolling stages, and a floating number. a second detecting means for detecting the number of decimal point registers, and a ratio obtained from the integer arithmetic number and the floating point arithmetic number detected by the first detecting means, the number of integer arithmetic units possessed by the computer and the floating point arithmetic number; closest to the ratio of the number of units and the second
determining means for determining the number of stages of loop expansion within a range in which the number of integer registers and the number of floating point registers detected by the detecting means does not exceed the number of integer registers and the number of floating point registers possessed by the electronic computer; , a program converting means for expanding into one loop the number of loop unrolling stages determined by the determining means and converting it into an instruction sequence equivalent to an instruction sequence in the loop; and a program converting means for expanding into one loop by the program converting means. and program execution means for executing in parallel instruction sequences for the number of loop unrolling stages.