JPH0430566B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a liquid crystal display device using an array substrate in which display electrodes including switch elements and capacitive elements are formed in a matrix.

[Technical background of the invention and its problems]

Recently, multi-pixel liquid crystal display devices have been using semiconductor integrated circuit technology and thin film technology to create display electrodes equipped with switch elements and display signal storage capacitive elements to control the brightness or lighting/non-lighting of each pixel. An array substrate arranged in a matrix on a semiconductor substrate or an insulating substrate is used.

Figure 1 is an equivalent circuit diagram to explain an example of the configuration of a switch/capacitive element array.
The source or drain of the MOS type FET 1 is electrically connected to one end of the MOS type capacitive element 2 and a display electrode 3 defining a pixel. The gates of MOS type FET1 are commonly connected for each row and are connected to the address line.
Y ₁ , Y ₂ ...Yn are provided, and their drains or sources are commonly connected for each column, and data lines X ₁ , X ₂ ...
Xm is provided. The MOS type FET 1, MOS type capacitive element 2, and address and data lines are formed, for example, on a semiconductor substrate, and furthermore, a display electrode 3 is formed thereon via, for example, an interlayer insulating film.

FIG. 2 is a configuration diagram for explaining a liquid crystal display device as an example of a display device using the switch/capacitor array shown in FIG. 1, in which 3 is a display electrode, 4 is a switch/capacitor element formed For example, a silicon substrate, 5 an interlayer insulating film, 6 a reinforcing substrate, 7 a counter electrode made of a transparent conductive film, 8 a transparent insulating substrate, 9
1 is a spacer and a sealing portion, and 10 is a liquid crystal layer.

The operation of the liquid crystal display device shown in FIG. 2 is performed as follows. That is, in FIG. 1, the address lines Y ₁ , Y ₂ , . . . Yn are sequentially scan-driven by a scan signal from a scan drive circuit, and the MOS FETs 1 are sequentially turned on for a period of TF/n for each line. Here, T _F is the frame scanning period. When data, for example m parallel image signal voltages, are supplied to the data lines X ₁ , X ₂ . . . Xm in synchronization with the above scanning,
The signal voltage is sequentially applied to the MOS type capacitive element 2 for each line.
is written to and retained for the frame scan period (T _F ). This held signal voltage is guided to the display electrode 3, and excites the liquid crystal layer 10 held between it and the counter electrode 7 in accordance with the signal voltage, so that an image is displayed.

This type of liquid crystal display device has the characteristics of low power consumption and thinness compared to those using a cathode ray tube, and portable televisions incorporating it for image display have been developed, and in the future, portable devices will be used. It may be frequently used in display parts.

When the liquid crystal display device is used in the display section of such a portable television, for example, and a function is added to display the time or simple information at all times in addition to displaying the TV image, the liquid crystal display device must be constantly powered. Since a portable small battery is used as a power source at this time, the power consumption of the liquid crystal display device becomes a problem. At present, the battery life when using the liquid crystal display device is about several hours, and the power consumption of the liquid crystal display device is too large to keep the power supply (battery) “ON” all the time. This is the data line
This is because the circuit driving X ₁ , X ₂ . . .

Conventionally, for the above-mentioned reasons, a segment type liquid crystal display device used in calculators, wristwatches, etc. for displaying time and simple information has been provided separately from the liquid crystal display device, and it is necessary to provide these two types of display devices. This has hindered the miniaturization of portable devices.

[Purpose of the invention]

The present invention improves the above-mentioned problems, and has two types of display: pixel display like TV image display, and display of time and simple information with lower power consumption.
The object of the present invention is to provide a small liquid crystal display device that allows selection of different display states.

[Summary of the invention]

In the liquid crystal display device according to the present invention, in addition to a display electrode selection switch element and a display signal storage capacitor element, a capacitor element selection switch element is provided for each display electrode on the array substrate side, while a counter electrode is provided with a capacitive element selection switch element for each display electrode. It is composed of a plurality of band-shaped transparent electrodes each having a width corresponding to an integral number of electrodes. With such a configuration,
All capacitive element selection switch elements are turned on,
It is possible to selectively switch between a multi-pixel display mode that uses capacitive elements and a display mode such as time display that does not use capacitive elements, in which all capacitive element selection switch elements are turned off.

〔Effect of the invention〕

The liquid crystal display device according to the present invention can select two types of display modes within one display screen, that is, a multi-pixel display state such as a television image, and a state where the time and simple information are displayed. Therefore, compared to a system in which two display devices are configured separately and placed side by side in correspondence with two types of display modes, the size of the device can be reduced. In addition, a display state that does not use capacitive elements has fewer display pixels than a multi-pixel display state that uses capacitive elements, but it consumes less power and can easily display the time and simple information according to the present invention. It became.

[Embodiments of the invention]

Embodiments of the present invention will be described using the drawings.

FIG. 3 is an equivalent circuit diagram showing the switch/capacitive element array configuration in this embodiment, in which 11 is a MOS type FET as a switch element for display pixel selection;
2 is a MOS type capacitive element for display signal storage, 13 is a display electrode that defines a pixel, and 14 is a MOS type capacitive element as a switch element for selecting the MOS type capacitive element 12.
They are FETs and are arranged in a matrix. The display electrode 13 is electrically connected to the source or drain of the MOS type FET 11 and the source or drain of the MOS type FET 14, and the MOS type capacitive element 12 is connected to the drain or source of the MOS type FET 14.
One end of the MOS FET 14 is connected, and all gates of the MOS FET 14 are commonly connected to one control terminal (not shown). The gates of the MOS FETs 11 are commonly connected for each row to the first address lines Y ₁ , Y ₂ . . .
Ym is formed, and the drains or sources are commonly connected for each column to form data lines X ₁ , X ₂ . . . Said MOS type FET11, 14, 15, 1
6. The MOS type capacitive element 12, the address line, and the data line are formed on the same silicon substrate, and a display electrode 13 which also serves as a reflection plate is formed from aluminum or the like through an interlayer insulating film thereon. As shown in FIG. 4, the transparent electrodes facing the display electrodes 13 are formed by using a transparent conductive film (In ₂ O ₃ ) on the glass substrate 17 to form a plurality of parallel electrodes having a width corresponding to an integral number of the display electrodes 13. It is arranged as a strip-shaped electrode 21. The strip electrode 21 is a second address line.
Y ₁ ′, Y ₂ ′...Yi′ are formed, and the gap between them is the display electrode 1
3, and one end is taken out to the end of the transparent substrate 17. FIG. 5 is a plan view and a cross-sectional view showing the specific structure of the liquid crystal display device in this embodiment, and 18 is a MOS type FET 1 shown in FIG. 3.
1, 14, MOS type capacitive element 12, address lines Y ₁ , Y ₂ ...Yn, data lines X ₁ , X ₂ ...Xm
A display electrode 13 is formed on the silicon substrate with an interlayer insulating film 19 interposed therebetween. 20 is a reinforcing substrate, 21 is a transparent conductive film (In _2
22 is a liquid crystal layer, 23 is a sealing part which also serves as a spacer, and the area surrounded by dotted lines in FIG. 5 is a display pixel area. Note that the silicon substrate 18 further includes first and second scanning circuits 24 and 25, and first and second scanning circuits 24 and 25.
Data line drive circuits 26 and 27 are formed. The first scanning circuit 24 has address lines Y ₁ ,
Y ₂ ...Yn, and the first and second data line drive circuits 26 and 27 are connected to the data lines X ₁ , X ₂ ... electrically connected at the top. The second scanning circuit 25 connects the second address lines Y ₁ ', Y ₂ '...Yj' through a conductive paste 28 applied to prevent electrical short-circuiting between them.
Y ₁ ', Y ₂ '...Yi', that is, connected to the strip electrode 21.
Figure 6 schematically shows each of the connections described above. One end of the data lines X ₁ , X ₂ ...Xm is connected to a MOS FET.
After passing through the switch consisting of 16, the data lines are driven by connecting multiple lines (two lines in Figure 6) in common to each other so that the data lines appear to be X ₁ ', X ₂ '...Xj'. Connected to circuit 27. Also, in FIG. 6, the second address line Y ₁ ',
The width of the strip electrode 21 that is Y ₂ ′...Yi′ is the display electrode 1
An example is shown in which the value is twice 3.

The liquid crystal display device configured as described above is capable of switching between two types of display modes: when the MOS type capacitive element 12 is used and when the MOS type capacitive element 12 is not used. Each display mode will be described below.

When the MOS type capacitive element 12 is used for display operation, an "ON" signal is applied to all gates of the MOS type FET 15 shown in Fig. 3 to make it conductive.
The data lines X ₁ , X ₂ ...Xm and the first data line drive circuit 26 are electrically connected, and the MOS type
An “OFF” signal is applied to all gates of FET16 to make them non-conductive and the data lines X ₁ , X ₂
...Xm and the second data line drive circuit 27 are separated, and an "ON" signal is applied to all gates of the MOS FET 14 to make it conductive.
One end of the MOS type capacitive element 12 is connected to the display electrode 13.
It is electrically connected to the source or drain of the MOS FET 11. The equivalent circuit at this time is similar to that shown in Fig. 1, and as in the conventional case, the scanning signals from the first scanning circuit 24 are applied to the first address lines Y ₁ , Y ₂ . . . Yn, and these are sequentially selected. . MOS connected to selected address line
FET11 becomes conductive only when the above selection is made.
Display signals output from the first data line drive circuit 26 are input to the MOS type capacitive element 12 through the data lines X ₁ , X ₂ . . . Xm, and the display signals are accumulated and displayed until the next selection. The accumulated display signal is output to the electrode 13. In addition, a common signal from the second scanning circuit 25 is applied to all of the second address lines Y ₁ ', Y ₂ '...Yi' provided facing the display electrode 13, and the second address lines consisting of a plurality of lines are appears to be one electrode facing all of the display electrodes 13. As a result, the liquid crystal layer 22 has the display electrode 13 and the second address line.
A voltage corresponding to the potential difference between the signals applied to each of Y ₁ ', Y ₂ '...Yn' is applied, and an image is displayed according to the voltage.

When performing a display operation without using the MOS capacitive element 12, the MOS FET 15 shown in FIG. 3 is made non-conductive, the MOS FET 16 is made conductive, and the data lines X ₁ , ₂ . . . Further, the first scanning circuit 24 simultaneously applies a common "ON" signal to all of the first address lines Y ₁ , Y ₂ , . . . Yn to make all the MOS FETs 11 conductive. In this case, the display signal output from the second data line drive circuit 27 is applied to the display electrode 13 on the data line.
X ₁ ′, X ₂ ′...Xj′, and the second address lines Y ₁ ′, Y ₂ ′...Yi′
Scanning signals from are sequentially applied. The display operation at this time is the same as the display operation when a normal matrix liquid crystal panel having two orthogonal sets of parallel electrodes is time-divisionally driven in a line-sequential manner. The conventional matrix-type panels have been incorporated into wristwatches and have demonstrated low power consumption.
As can be seen from Figure 6, the number of display pixels during display operation without using the MOS type capacitive element 12 is (X'j) x
(Yi′). For example, the first address lines Y ₁ , Y ₂ ...Yn, which apply scanning signals during multi-pixel display,
240 (Yn = 240), 180 ( _Xm = 180) data lines _{X 1 ,} X ₂ . . . Assuming 18 driveable electrodes (Yi' = 18), 10 of the display electrodes 13
The data lines (240 lines) are connected in common by eight lines after passing through the MOS FET 16, so that there are apparently 30 lines (Xj' = 30).
If the data line is set to 1, the display pixels will be 18 x 39 when the MOS capacitive element 12 is not used, and if the character is composed of 5 x 7 dots, it will be 2 lines x 5.
Can display characters. At this time, the clock pulse frequency in the second data line drive circuit 27 is
When compared with the clock pulse frequency in the first data line drive circuit 26, assuming that the one frame frequency (fF) is the same, f _F ×Yi′×Xj′/f _F ×Yn×Xm=
1/80, and the second data line drive circuit 27 operates at a low speed of several tens of kilohertz. Further, the capacitive component connected to the second data line drive circuit 27 is
Since the MOS type capacitive element 12 is separated and there is only the stray capacitance of the data line, the charging/discharging current is reduced and the clock pulse frequency is also lowered. The number of times the discharge current flows also decreases.
As a result, during display operation when the MOS capacitive element 12 is not used, power consumption is reduced to the extent that there is no problem even if the display operation is always performed using batteries, and simple information such as the time can be displayed at all times. Now it can be displayed.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a conventional switch/capacitive element array, Fig. 2 is a sectional view showing a configuration example of a conventional liquid crystal display device, and Fig. 3 is an equivalent circuit diagram of a switch/capacitive element array in an embodiment of the present invention. The circuit diagram, Fig. 4 is a configuration diagram of the opposing transparent electrode in the same embodiment, and Fig. 5 is a circuit diagram.
Figures a and b are a plan view and a cross-sectional view showing the structure of the liquid crystal display device of the same embodiment, and FIG. 6 is a diagram schematically showing the connection between each electrode and a drive circuit. 11...MOS type FET (switch element for display pixel selection), 12...MOS type capacitive element, 13...display electrode, 14...MOS type FET (switch element for capacitive element selection), 17...glass substrate, 18...
Silicon substrate, 21... Transparent strip electrode, 22...
Liquid crystal layer, 24, 25... Scanning circuit, 26, 27...
...Data line drive circuit.

Claims (1)

[Claims] 1. An array substrate in which a plurality of display electrodes each having a switch element and a capacitor element are arranged in a matrix at the intersection of a first address line and a data line, and a transparent substrate on which a transparent electrode is formed. In a liquid crystal display device configured by sandwiching a liquid crystal layer between a counter substrate, a capacitive element selection switch element is provided between each of the plurality of display electrodes and each capacitive element connected thereto; A transparent electrode is arranged as a plurality of second address lines having a width corresponding to the plurality of display electrodes, a first data line drive circuit is electrically connected to the data line, and the capacitor All the selection switch elements are turned on, the first address lines are selected in sequence, the display signal output from the first data line drive circuit is input to the capacitive element through the data line, and is accumulated. Outputting the accumulated display signal to the display electrode, and
a display mode in which a common signal is applied to all of the second address lines; a second data line drive circuit is electrically connected to the data lines; all the capacitive element selection switch elements are turned off; 1 address line, and apply a display signal output from the second data line drive circuit to the display electrode through the data line, and
1. A liquid crystal display device having a display mode in which a scanning signal is sequentially applied to the address lines.