JPH0430472A - Solid-state image sensor scanning circuit - Google Patents

Abstract

PURPOSE:To protect a solid-state image sensor against malfunction by a method wherein a first conductivity type transistor is provided outside a second conductivity type transistor, and a second conductivity type semiconductor region is buried. CONSTITUTION:P-type well regions 2a and 2b are provided outside P-MOS transistors Tp1 and Qp1 and Tp2 and Qp2, and N-MOS transistors Tn1 and Qn1 and Tn2 and Qn2 are formed inside the regions 2a and 2b respectively. Furthermore, a P-type buried layer 3 is formed like a plate surrounding the regions 2a and 2b and the P-MOS transistors Tp1 and Qp1 and Tp2 and Qp2 to serve as a kind of barrier layer. By this setup, optical holes h photoelectrically converted at a part other than an optical shielding layer 4 are lessened in probability f penetration into the P-MOS transistors Tp1 and Qp1 and Tp2 and Qp2 and absorbed by the layer 3. Therefore,data are protected against damage, and a vertical scanning circuit can be previously protected against malfunction.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a scanning circuit used in a solid-state image sensor,
In particular, the present invention relates to the structure of a shift register built into the scanning circuit.

[Summary of the invention]

The present invention provides a scanning circuit for a solid-state imaging device having a shift register in which transistors of a first conductivity type channel and a second conductivity type channel are arranged in multiple stages on a semiconductor layer of a first conductivity type. A channel transistor is disposed outside the second conductivity type channel transistor, and a first conductivity type channel transistor is disposed below the second conductivity type channel transistor.
By embedding a semiconductor region of a conductivity type or a second conductivity type, the influence of photoelectrically converted carriers can be reduced and malfunction of the scanning circuit can be prevented.

[Conventional technology]

2. Description of the Related Art Conventional scanning circuits for solid-state image sensors, particularly shift registers built into the scanning circuits, use a shift register that utilizes a bootstrap effect in order to reduce power consumption. This shift register stabilizes the output of the scan signal by raising the potential applied to the gate of the N-MOS transistor that controls the output of the scan signal to a level higher than the power supply voltage using a bootstrap capacitor. According to this shift register, it is possible to reduce power consumption and, especially when used as a shift register in a vertical scanning circuit, it is possible to perform normal operation without being affected by light. That is, as shown in FIG. 12, since the N-MOS transistor Tr constituting the shift register is formed in the P-type well region (32) on the N-type substrate (31), the light shielding layer ( Even if the optical hole h photoelectrically converted in a part other than 33) enters the N-MOS transistor Tr side, it is absorbed into the P-type well region (32), so the optical hole h of the N-MOS I-transistor Tr is absorbed into the P-type well region (32). h has no effect at all. However, in the case of the above-mentioned shift register, there is a limit to miniaturization because the pitch required for one bit is long (approximately 27 μm) and an interlace circuit is required separately.

In addition, since a voltage higher than the power supply voltage is applied to the gate, the reliability of the gate withstand voltage is poor, especially in miniaturization designs.
There is this inconvenience.

Therefore, in the past, dynamic
Shift registers using flip-flop circuits have been proposed. In the case of this shift register, since the pitch for one bit is short (5 μm) and an interlacing circuit is not required, the scanning circuit can be made smaller and there is no problem in terms of gate breakdown voltage.

[Problem to be solved by the invention]

However, in a shift register with a CMOS configuration, as shown in FIG.
Since the P-MOS transistor Trp is formed with the light shielding layer (33), the photohole h photoelectrically converted in a portion other than the light shielding layer (33) is, for example, a 2MO3) transistor Trp.
(generally referred to as smear charge wrap-around due to intense edge light), causing the inconvenience of destroying data.

Note that the N-MOS transistor Trn is formed within the P-type well regions (32a) and (32b).

The second problem occurs particularly in vertical scanning circuits. In other words, in the case of a horizontal scanning circuit, the optical hole h
However, in the case of vertical scanning circuits,
Since the time required to hold data is at least the imaging period for one horizontal scan, the amount of intrusion of optical holes h increases, causing a phenomenon in which the data held in the P-MO3I-transistor Trp is destroyed. If the shift register operates in an analog manner, this may cause a clamp operation error, and if the shift register operates in a digital manner, the held data may be inverted.

The present invention has been made in view of these points, and its purpose is to reduce the influence of photoelectrically converted carriers (optical holes) and to prevent malfunctions of scanning circuits. An object of the present invention is to provide a scanning circuit for an image sensor.

[Means to solve the problem]

The present invention provides a transistor (Tn) having a first conductivity type channel and a second conductivity type channel on a first conductivity type semiconductor layer (1).
, Qn ) and (Tp, Qp ) arranged in multiple stages in a scanning circuit for a solid-state imaging device, the transistors (Tn, Q
n'J is a second conductivity type channel transistor CTp,
Qp), and a first conductivity type or second conductivity type channel transistor (Tp, Qp) is placed outside the second conductivity type channel transistor (Tp,
It is constructed by embedding a conductive type semiconductor region (5) or (3).

[Effect]

According to the configuration of the present invention described above, since the first conductivity type channel transistors (Tn, Qn) are arranged outside the second conductivity type channel transistors (Tp, Qp), photoelectrically converted carriers The probability of the (photohole h) entering the transistor (Tp, Qp) decreases, and
The carriers h are blocked or absorbed by the first conductivity type or second conductivity type semiconductor region (5) or (3) formed under the transistors (Tp, Qp), so that the carriers to the transistors (Tp, Qp) are Data destruction due to the intrusion of h does not occur, and malfunction of the scanning circuit is prevented.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 to 10.

FIG. 1 is a circuit diagram showing the configuration of a shift register (8) used in the vertical scanning circuit of the solid-state image sensor according to this embodiment, and FIG. 2 is a circuit diagram showing the structure of the first and second stage transistors in FIG. FIG. 2 is a cross-sectional view showing the configuration of a circuit.

This shift register (A) uses a dynamic flip-flop circuit with a CMOS configuration, and as shown in FIG.
P-MOS to which phase drive pulses φ and T are supplied respectively
) A transistor circuit Tr formed by connecting a transistor Qp and an N-MO3I-transistor Qn is arranged in multiple stages.

In the illustrated example, subscripts 1, 2, 3, . . . are added to each stage.

Specifically, the first stage has an inverter circuit to which the synchronizing pulse Vin is supplied via the first node N1, and the inverter circuit is connected between the P-MOS transistor TP1 and the N-MOS transistor Ttt1. To,
P'-MO to which two-phase drive pulses φ and T are supplied respectively
S) Transistor QPI and NMOS transistor Q,,I
A transistor circuit T, □ is provided by connecting the following two
The stage has an inverter circuit to which the output voltage from the first stage transistor circuit Trl is supplied via the second node N2, and two-phase drive pulses are applied between the transistors T and z constituting this inverter circuit and 192. A transistor circuit Tr2 is provided by connecting transistors Qpz and Qn2 to which T and φ are respectively supplied, and similarly, three stages,
In the 4th stage..., transistor circuits T r 3 + T r 4 + having the same configuration as above
... are connected to each other. The above two-phase drive pulse φ
and T, φ is the transistor QP in the first stage
+, transistors Q and lz in the second stage, transistor Qp3 in the third stage, and so on for each stage.
1 is supplied alternately to the transistor Q in the first stage.
,,I, and in the second stage, the transistor Q p z,
In the third stage, the signal is alternately supplied to each stage, such as to transistor Qp3. In addition, P-M of each inverter circuit
A power supply voltage Vaa is applied to each drain of the N-MOS transistors Tp, T, z, . . . , and a ground potential VSS is applied to each source of the N-MOS transistors 'rat, Tng, . Then, two transistor circuits (T, , 'rrz), (T,3.
'r, , ), . . . are set as one set (one bit), and the output voltages V, , V, .

Looking at the above configuration in the cross-sectional view of FIG. 2, for example, P-type well regions (2a) and (2b) are formed on an N-type silicon substrate (1), and the P-type well regions (2a) and (2b) includes an N-MOS transistor (Tn).

Qn, ) and ('rnz, QnJ are formed, and 2MO3) transistors ('rp, , Qp) are formed on the silicon substrate (1) other than the P-type well regions (2a) and (2b).
ri and (Tp□.

Q,] is formed. Especially in this example, P-MOS)
transistor [T□, Q, ,) and ('r pt+Q, ,
) P-type well regions (2a) and (2b) are formed outside the P-type well regions (2a) and (2b), and N
MOS transistors (Tn, Qn,) and [T, ,
2Q, 2] is formed. Furthermore, P-type well regions (2a), (2b) and P-MOS transistors (
Tp.

Q, , ), (T, □, Qp□), a P-type buried layer (3) is formed in an almost dish shape to form a kind of barrier layer.This P-type buried layer (3) is , is connected to the well regions (2a) and (2b) at its ends. Also, this buried layer (3) is ion-implanted with a P-type impurity, such as boron (implantation amount ~101101z", implantation energy 3 MeV). This ion implantation is preferably performed before forming various transistors.
The potential in the buried layer (3) of the mold is, as shown in FIG.
More than that is fine.

As described above, according to this embodiment, the P-type well region (2) in which the N-MOS transistors Tn and Qn are formed is replaced with the P-MOS transistors rp and Q.

Since the light shielding layer (4) is arranged outside of the P-type well region ( P-type buried layer (3) formed from the periphery of 2) to below the P-MOS transistors Tp and Qp
Since the optical hole h is absorbed by P-MO
Data destruction due to the intrusion of optical holes h into the S transistors Tp and Qp does not occur, and malfunctions in the vertical scanning circuit can be prevented in advance.

Next, another example of the above embodiment will be described with reference to FIG. Components corresponding to those in FIG. 2 are designated by the same reference numerals.

This shift register has almost the same configuration as the shift register (^) according to the above embodiment, but as shown in the figure,
The difference is that an N-type diffusion region having a higher concentration than the substrate (1) is used as the buried layer (5). This buried layer (5) is ion-implanted with an N-type impurity, such as arsenic (implantation amount ~1
01ffC1l-”, implantation energy 3M e V
) is formed under the P-MO3) transistors Tp and Qp. In the case of this N type buried layer (5), it is not necessary to form it so as to surround the P type well region (2) as in the above embodiment.

Here, the potential difference Δφ (see FIG. 5) between the buried layer (5) and the silicon substrate (1) is expressed by the following equation.

Note that k and T are in eV units, and kT/q indicates a voltage caused by heat. Further, Nb and N5ub represent N-type ion concentrations in the buried layer (5) and silicon substrate (1), respectively.

Therefore, in the optical hole h photoelectrically converted in a portion other than the light shielding layer (4), among the optical holes (pit) existing outside the buried layer (5), the P-M
O3) The ratio of optical holes (P, ) entering the transistors Tp and Qp side is determined by the following formula, and if Nb /N5ub >10,
The amount of penetration of the optical holes h is numerically reduced by an order of magnitude.

According to the embodiment shown in FIG. 4 above, as in the embodiment shown in FIG. 2 above, the P-MOS transistor T of the optical hole h
Since the intrusion into p and Qp is reduced, malfunction of the shift register and malfunction of the vertical scanning circuit due to the intrusion of the optical hole h can be prevented.

The above embodiment is based on P-MO3I-transistors Tp and Qp.
By forming a P-type or N-type buried layer (3) or (5) underneath, the penetration of optical holes h is reduced.In addition, although not shown, the silicon substrate (1)
An N-type epitaxial layer with a lower concentration than the substrate (1) is formed on the substrate (1), and on this epitaxial layer, a P-type well region (2) and P-MO3) transistors Tp, Qp, and N-type are formed.
-MO3) transistor Tn.

If Qn is formed, the optical hole h in the silicon substrate (1)
The lifetime of the optical hole h is shortened, and the intrusion of the optical hole h into the 2MO5) transistors Tp and Qp is reduced. Of course, the formation of the epitaxial layer and the structure of the above embodiment may be combined.

By the way, although the above embodiment has described the vertical scanning circuit, the horizontal scanning circuit (11) in FIG. , the influence of the optical hole h can be almost ignored. However, as shown in Fig. 7, the two-phase driving pulses φ and T are in motion even during the period when one pixel is selected, and the operation of these φ and T normally causes current to flow between the power supply and GND. This causes an inconvenience in that the noise flows and appears in the image as noise. Therefore, in this example, the power supply voltage V, d of the horizontal scanning circuit (11) and the ground potential ■88.
Connect the wiring to the power supply voltage ■dd! of the logic gate circuit (12).
and the ground potential (1) 8, 2, the power supply voltage vad3 of the driver circuit (13), and the ground potential VssJ are drawn on separate lines. With this configuration, the two-phase drive pulses φ and T
The current that flows to the power supply and GND due to the operation of 1 does not affect the logic gate circuit (12) or the driver circuit (13), so the generation of noise is reduced. In addition, in FIG. 6, the logic gate circuit (12) does not necessarily need to be installed. In addition, the power supply voltage ■4 extending to the horizontal scanning circuit (11)
4. If the wiring connected to the ground potential ■□1 is separate wiring from other circuits as described above, the pad to which the power supply voltage is supplied and the pad to which the ground potential is supplied may be the same.

On the other hand, in solid-state imaging devices, miniaturization of design is progressing, and in the MOS process due to miniaturization, the polycrystalline silicon layer normally used as wiring becomes wiring with a polycide structure, reducing sheet resistance. It became so. On the other hand, the line width has become thinner to 0.5 μm, and the field insulating layer formed by selective oxidation has also become thinner by about 2,000 people, and as shown in FIG. 8, the line capacitance CL I +
CL2...CLr+ and wiring resistance RLI+ RL
2...The time constant due to R is becoming a problem.

In particular, in HD and TV (high-definition television) systems, the horizontal blanking period is short, and horizontal scanning is started before the output from the vertical scanning circuit reaches the end of the gate line (selection line) to read out the signal. must be done. Here, in FIG. 9, after the output signal is output from the vertical scanning circuit, tl, tl, t3 . It shows how the potential (output signal) changes after time t4 has elapsed.

Now, as shown in FIG. 10, a photodiode D, an amplification transistor TA, a vertical switching transistor T
y and a pixel (2
1) are arranged in a matrix shape.
2), a first vertical scanning circuit (23) that performs row selection scanning, a second vertical scanning circuit (24) that performs reset scanning, and a horizontal scanning circuit (24) that performs signal readout scanning.
25), in this example, among the wirings extending in rows from the first and second vertical scanning circuits (23) and (24), the first The wiring (row selection line) fy extending from the second vertical scanning circuit (23) is formed of, for example, a tungsten silicide layer, and the wiring (reset line) 2 extending from the second vertical scanning circuit (24) is formed of a tungsten silicide layer.
．． For example, 42 layers are formed. Although the tungsten (-) silicide layer is easier to form than the A1 layer,
It has the characteristic of high sheet resistance. Then, the first vertical scanning circuit (23) in which the wiring py made of the tungsten silicide layer with high sheet resistance is formed is arranged on the side where horizontal scanning is started.

In the figure, → indicates the direction of horizontal scanning.

With this configuration, after the first horizontal scan is started, the next horizontal scan can be started from around t2 to t in FIG. 9, and the time constant of the wiring can have a relatively large margin. I can do it. Therefore, a material having a slightly higher sheet resistance can be used for the wiring extending from the vertical scanning circuit. In general, materials with high sheet resistance are easy to form, so in this example, it is possible to simplify the manufacturing process and reduce costs. In addition, since the next horizontal scan can be started after a relatively short period of t2 to t3 has elapsed after the first horizontal scan has started, it is effective for use with HDTVs, high-speed cameras, etc. that have short horizontal blanking periods. Become.

〔Effect of the invention〕

According to the scanning circuit for a solid-state image sensor according to the present invention, the influence of photoelectrically exchanged carriers can be reduced, and malfunctions caused by the carriers can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a shift register built into a scanning circuit for a solid-state image sensor according to this embodiment, FIG. 2 is a cross-sectional view thereof, and FIG. 3 is a potential on line A-A in FIG. FIG. 4 is a cross-sectional view showing another example of this embodiment. FIG. 5 is a characteristic diagram showing the potential on line B-B in FIG. 4. FIG. 6 is a block diagram showing the horizontal scanning circuit. Figure 7 is a waveform diagram showing its operation, Figure 8 is an equivalent circuit diagram showing the main function of the gate line (row selection line), Figure 9 is a characteristic diagram showing the propagation state of the output signal, and Figure 7 is a waveform diagram showing the operation. FIG. 10 is a circuit diagram showing a solid-state imaging device according to this example, FIG. 11 is a sectional view showing a conventional example, and FIG. 12 is a sectional view showing another conventional example. (A) is a shift register, TPI~Tra and QFl~
QPa is P-MOS) transistor, T II IT
1% 4 and Qyl + “” Q n 4 is N-MO
S transistor, Tr1 to T, 4 is a transistor circuit, (1) is a silicon substrate, (2a) and (2b) are P
mold well region, (3) and (5) are buried layers, (4)
is a light shielding layer. Agent Hidemori Matsukuma A Shift register Figure 10

Claims (1)

[Scope of Claims] A scanning circuit for a solid-state imaging device having a shift register in which transistors of a first conductivity type channel and a second conductivity type channel are arranged in multiple stages on a semiconductor layer of a first conductivity type, A solid-state imaging device in which a conductivity type channel transistor is arranged outside the second conductivity type channel transistor, and a first conductivity type or second conductivity type semiconductor region is buried below the second conductivity type channel transistor. Scanning circuit for elements.