JPH04302554A - Pulse train converting device - Google Patents

Abstract

PURPOSE:To arbitrarily designate the start of an already converted pulse train signal by giving the timing of initialization of write and read address counters to a data memory from the external by a synchronizing signal. CONSTITUTION:The address value of the write address counter is initialized by a first synchronizing signal (h) which has the same period as prescribed and is synchronized with the generation timing of the first pulse signal out of plural pulse signals of a first pulse train signal (a). In the same manner, the read address counter is initialized by a second synchronizing signal (1) synchronized with the generation timing of the pulse signal to be placed in the first position of a second pulse train signal (g). Consequently, the pulse signal stored in any address is arbitrarily selected as the pulse signal in the first position of the second pulse train signal (g). Thus, respective bit positions of all pulse signals in one frame of the second pulse train signal (g) can be moved in parallel.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse train converter for converting the arrangement of pulse signals in a pulse train signal containing a plurality of pulse signals within a prescribed period, and in particular, the present invention relates to a pulse train converter for converting the arrangement of pulse signals in a pulse train signal containing a plurality of pulse signals within a specified period. This invention relates to a pulse train conversion device that can be specified arbitrarily.

0002

2. Description of the Related Art A synchronous interface standard was standardized by CCITT (International Telegraph and Telephone Consultative Committee) in the fall of 1988 as a standard for transmitting digital data at high speed in a digital communication network. This new synchronous interface is called SDH (Synchronous Digital Hierarchy) and has a frame structure shown in FIG. That is, this frame structure has 270
It consists of 9 lines of 270 bytes, and the first 9 bytes of the 270 bytes are a header for controlling, monitoring, and maintenance, and each of the next 87 bytes is used to set a destination and an area in which data is stored. Furthermore, frame data indicating the start of the frame is set at the beginning of the frame structure.

When transmitting data with this frame structure, as shown in FIG. 6, a frame signal is placed at the beginning, followed by burst signals specifying data 1, 2, 3, . . . . The burst signal is composed of, for example, 8 bits (1 byte), and the intervals between the burst signals are not constant, as shown in the frame structure of FIG. 5. Furthermore, if there is no data to be transmitted, there is no burst signal for that portion.

[0004] There are pulse train signals made up of burst signals in which a plurality of pulse signals are arranged intermittently, and pulse train signals made up of continuous signals in which a plurality of pulse signals are arranged in succession. A pulse train conversion device has been developed that arbitrarily converts signals between these pulse train signals.

FIG. 7 is a block diagram showing a schematic configuration of a pulse train conversion device having the above-mentioned conversion function. Note that the pulse train converter shown in FIG. 7 has a function of converting a burst signal into a continuous signal.

A first pulse train signal a shown in FIG. 8 input to the input terminal 1 is applied to the data terminal D of the data memory 2, which is a dual port memory having a write-only port and a read-only port. This first pulse train signal a
In this case, N pulse signals each consisting of, for example, a burst signal are formed within a prescribed period T, and the intervals between the pulse signals are arbitrarily set. A first clock signal b indicating the generation timing of each pulse signal of the first pulse train signal a is input from the input terminal 3. The first clock signal b input from the input terminal 3 is applied to the write address counter 4. The write address counter 4 sequentially increases the write address value applied to the address terminal AD of the write-only port of the data memory 2 every time the clock of the first clock signal b is input. Therefore, each pulse signal of the first pulse train signal a is sequentially written to each address designated by the write address counter 4. The write address counter 4 is automatically reset to the initial value 1 when the write address value reaches the number N of pulse signals. That is, the data memory 2 has a storage capacity at least equal to the number of pulse signals included in one period T of the first pulse train signal a.

The first clock signal b input from the input terminal 3 is input to the clock converter 5. This clock conversion circuit 5 includes, for example, a frequency divider, a PLL circuit, a VCO (
It outputs a second clock signal c whose clock interval is fixed to a period (T/N) obtained by dividing the prescribed period T into N equal parts. That is, the clock generation timing of the first clock signal b is converted to the second clock generation timing. The second clock signal c outputted from the clock conversion circuit 5 is outputted to the output terminal 6 and also inputted to the read address counter 7.

The read address counter 7 sequentially increases the read address value applied to the address terminal AD of the read-only port of the data memory 2 every time the second clock signal c is input. Therefore, each of the first to Nth pulse signals stored at each address designated by the read address counter 4 of the data memory 2 is read out in order. The read address counter 7 is automatically reset to the initial value 1 when the read address value reaches the number N of pulse signals. As a result, a continuous signal with narrow intervals between the pulse signals as shown in FIG. 8 is output from the output terminal 8.
A second pulse train signal d having an arrangement of is output.

Note that the data memory 2 stores the write address value by the write address counter 4 and the read address value by the read address counter 7.
When the read address value approaches the specified address value or less,
An alarm signal e is sent to the counter control section 9. When the alarm signal e is input, the counter control section 9 adjusts the relationship between the write timing and the read timing for each address counter 4 and 7 so that the address values do not approach each other.

Therefore, by using such a pulse train converter, a burst signal can be converted into a continuous signal.

FIG. 9 is a block diagram showing a pulse train converter for converting a continuous signal into a burst signal. In this pulse train conversion device, a clock conversion circuit 10 is composed of a synchronous oscillation circuit 10a and a timing generation circuit 10b. Further, the gate signal f outputted from the timing generation circuit 10b and the signal read from the data memory 2 are outputted to the output terminal 8 via the AND gate 11.

In such a pulse train conversion device, a first pulse train signal d1 consisting of continuous pulse signals as shown in FIG. ), each pulse signal of the first pulse train signal d1 is sequentially written into each address area of the data memory 2 in synchronization with the first clock signal c1. . Further, the clock conversion circuit 10 converts the clock interval of the input first clock signal c1 into a clock signal having the lowest clock interval of the burst signal narrower than this clock interval. The next timing generation circuit 10b extracts N clocks having timings that are preset or externally input and have a second arrangement from among the clocks of the clock signal, and generates a second clock signal b.
Create 1. This second clock signal b1 is input to the read address counter 7. Furthermore, a gate signal f having a predetermined pulse width including each clock of the second clock signal b1 is outputted from the timing generation circuit 10b to the AND gate 11.

[0013] Thus, a second pulse train signal a1 is obtained from the output terminal 8 by accommodating a plurality of pulse signals in a second arrangement in the form of a burst signal, using a procedure substantially similar to that of the pulse converter shown in FIG.

[0014]

However, the pulse train converters shown in FIGS. 7 and 9 still have the following problems.

Generally, when performing a performance test of a communication device such as an exchange or a repeater that inputs and outputs a pulse train signal having the frame structure shown in FIG. There is a need to.

For this purpose, by specifying the number of the first pulse signal in one frame as an arbitrary number from 1 to N, N pulse signals in one frame can be arranged at mutual intervals. It is important to be able to arbitrarily specify the presence or absence of a signal at each bit position within one frame from the outside by moving the signal back and forth in parallel while keeping it fixed.

However, even when converting a burst signal into a continuous signal as shown in FIG. 8, and when converting a continuous signal into a burst signal as shown in FIG. The first pulse signal within one frame of period T consisting of N pulse signals in the first pulse train signal is the first pulse signal within one frame of N pulse signals of the second pulse train signal after conversion. equal. Specifically, the leading address of the data memory 2 stores the leading pulse signal within one frame constituting the first and second pulse train signals input/output to/from the pulse train conversion device. When reading, the pulses are always read out in order from the first address and set in the frame memory in order from the first pulse position.

In other words, in these pulse train conversion devices, N pulse signals from number 1 to number N within one frame can be arranged in a burst signal form or a continuous signal form without changing the order. Although it is possible to
It was not possible to specify the pulse signal that comes at the beginning of one frame.

Therefore, it has not been possible to obtain a pulse train signal in which all test conditions can be easily set.

The present invention has been made in view of the above circumstances, and the timing for initializing the write address counter and the read address counter is given externally using the first and second synchronization signals, so that the pulse train can be changed. Pulse string conversion allows you to specify the first pulse signal of any pulse signal within one frame during conversion, and not only converts the generation timing of each pulse signal, but also allows parallel translation of each bit position of all pulse signals within one frame. The purpose is to provide equipment.

[0021]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a write-only device in which a first pulse train signal consisting of a plurality of pulse signals stored in a first arrangement within a specified period is input. A data memory having a port and a read-only port, and sequentially specifying write addresses to the write-only port of the data memory in synchronization with a first clock signal indicating the generation timing of each pulse signal of the first pulse train signal. a write address counter that converts the clock signal, a clock conversion circuit that converts the clock generation timing of the first clock signal to the second clock generation timing, and a clock conversion circuit that converts the clock generation timing of the first clock signal to the second clock generation timing; It has a read address counter that sequentially specifies read addresses to the read-only port of the data memory, and corresponds to the clock generation timing of the second clock signal by sending a plurality of pulse signals from the read-only port of the data memory within a specified period. In a pulse train conversion device for reading out a second pulse train signal stored in a second arrangement, the pulse train converter has the same period as the specified period and the first pulse signal among the plurality of pulse signals in the first pulse train signal. The address value of the write address counter is initialized by a first synchronization signal that is synchronized with the generation timing, and has the same period as the specified period, and in the second pulse train signal among the plurality of pulse signals in the first pulse train signal. The address value of the read address counter is initialized by a second synchronization signal synchronized with the generation timing of the pulse signal to be positioned at the head.

[0022]

[Operation] In the pulse train converter configured as described above, each of the 1st to Nth pulse signals of the first pulse train signal input to the pulse train converter is sent to an address specified by the write address counter in the data memory. The first synchronization signal can be used to specify the address where the first pulse signal is stored. Similarly, each pulse signal from number 1 to number N to be set within one frame of the second pulse train signal is read out from the data memory in address order, but the read start address is specified by the second synchronization signal. becomes possible.

[0023] Therefore, it is possible to arbitrarily select at which address the pulse signal located at the head of the second pulse train signal is stored. Therefore, each bit position of all pulse signals within one frame in the second pulse train signal can be shifted in parallel.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a pulse train converter according to an embodiment. This pulse train converter has a function of converting a burst signal into a continuous signal. Also,
The same parts as in FIG. 7 are given the same reference numerals. Therefore, detailed explanation of the overlapping parts will be omitted.

The first signal input from input terminal 1 shown in FIG.
The pulse train signal a is inputted via the normally closed terminal of the changeover switch 21 to the data terminal D of the data memory 2 constituted by a dual port memory. Further, a delay circuit 22 is connected between the input terminal 1 and the normally open terminal of the changeover switch 21. The first synchronization signal h shown in FIG. 2 is inputted from the input terminal 23 via the normally closed terminal of the changeover switch 24, and the reset terminal R of the write address counter 4 is inputted with the first clock signal b shown in FIG. is applied to Further, a delay circuit 25 is connected between the input terminal 23 and the normally open terminal of the changeover switch 24. Furthermore, from the input terminal 26
A second synchronizing signal i shown in FIG. Further, a delay circuit 28 is connected between the input terminal 26 and the normally open terminal of the changeover switch 27. The respective changeover switches 21, 24, and 27 are simultaneously controlled by a counter control section 29 to which an alarm signal e is input from the data memory 2.

As shown in FIG. 2, the first synchronizing signal h has the first
This shows the generation timing (bit position) of the first (first) pulse signal among N pulse signals from number 1 to number N stored in the arrangement shown in FIG. Therefore, the period of this first synchronization signal h matches the period T of the first pulse train signal a.

[0028] Furthermore, the second synchronization signal i is the same as the first synchronization signal i.
Generation of a pulse signal that should be positioned at the beginning of one frame in the converted second pulse string signal g that should be output from the output terminal 8 among the N pulse signals from number 1 to number N of the pulse string signal a. Indicates timing (bit position). This embodiment indicates that the (N-1)th pulse signal is positioned at the beginning. Therefore, this second
The period of the synchronization signal i matches the period T of the first synchronization signal h.

The counter control unit 29 also receives an alarm signal e from the data memory 2 indicating that the write address value by the write address counter 4 and the read address value by the read address counter 7 have approached a predetermined address or less. Then, a switching signal is sent to each changeover switch 21, 24, 25, and each changeover switch 21, 24, 25 is switched to the normally open terminal side. As a result, the first pulse train signal a, the first
The input timings of the second synchronization signal h and the second synchronization signal i are delayed by the delay time set in each delay circuit 22, 25, and 28. The delay times of the delay circuits 22 and 25 on the input side are set to be equal, but the delay times of the delay circuits 22 and 25 on the input side and the delay time of the delay circuit 28 on the output side are set to different values. There is. Therefore, the timings of the write address and read address in the write address counter 4 and read address counter 7 are shifted. Then, when the write address value and the read address value are separated by a predetermined address or more, the alarm signal e output from the data memory 2 is canceled. Note that the input side changeover switches 21 and 24 and the output side changeover switch 27 do not necessarily need to be switched at the same time, and only the changeover switch on either side may be controlled.

Next, the operation of the pulse train converter constructed as described above will be explained using the time chart shown in FIG.

A first pulse train signal a including N pulse signals arranged in the form of a burst signal shown in FIG. 2 and input to the input terminal 1 is applied to the data terminal D of the data memory 2. Further, the first clock signal b is applied to the write address counter 4. The write address counter 4 is initialized to an address value of 1 by the first synchronization signal h at the timing when the first pulse signal is input. Therefore, in synchronization with the first clock signal input from the input terminal 3, each pulse signal from number 1 to number N of the first pulse train signal a is written in order from address 1 of the data memory 2. . Then, when the next first synchronization signal h is input, the data is written again in order starting from address 1.

The first clock signal b input from the input terminal 3 is input to the clock converter 5. This clock conversion circuit 5 generates a second clock signal c whose clock interval is fixed at a period (T/N) obtained by equally dividing the specified period T by N.
Output. This second clock signal c is output to the output terminal 6 and is also input to the read address counter 7.

The read address counter 7 is initialized to an address value of 1 by the second synchronization signal i input from the input terminal 26 at the timing when the (N-1)th pulse signal is input. Therefore, a difference of two pulse signals occurs between the write address value of the write address counter 4 and the read address value of the read address counter 7.

Therefore, 1 in the second pulse train signal g
The pulse signal read out at the beginning of the frame is (N-1)
This is the second pulse signal. As a result, as shown in FIG. 2, within the second pulse train signal g, (N-1), N,
A total of N pulse signals of 1, 2, . . . (N-2) are stored consecutively.

That is, in the pulse train conversion circuit of this embodiment, the first pulse train signal a having a burst signal arrangement can be converted into the second pulse train signal g having a continuous signal arrangement, and the second synchronizing signal The occurrence position of i (
By shifting the bit position), the first pulse signal within one frame of the converted second pulse train signal g can be set to an arbitrary pulse signal. Therefore, it is possible to shift the bit positions of each pulse signal arranged within one frame by an arbitrary amount.

FIG. 3 is a block diagram showing a schematic configuration of a pulse train conversion device according to another embodiment of the present invention. The same parts as in FIGS. 1 and 10 are given the same reference numerals. This embodiment device has a function of converting a continuous signal into a burst signal.

That is, the clock conversion circuit in the pulse train conversion device shown in FIG. .

In the pulse train converter having such a configuration, the first pulse train signal d1 arranged in a continuous signal form is input from the input terminal 1, the first clock signal C1 is input from the input terminal 3, and the first pulse train signal d1 is input from the input terminal 3. The first synchronization signal i1 is input from 23, and the output side input terminal 26
When the second synchronization signal h1 is inputted to the synchronous signal h1, the first pulse train signal d1 containing the inputted N pulse signals having a continuous signal arrangement is generated using the same procedure as in the embodiment of FIG. is converted into a second pulse train signal j containing N pulse signals having a burst signal arrangement. At the same time, all pulse signals within one frame of the second pulse train signal j are translated in parallel so that the pulse signal specified by the second synchronization signal h1 becomes the first pulse signal.

In this way, by using each of the pulse train converters shown in FIGS. 1 and 3, the N pulse signals existing within one frame of the pulse train signal can be rearranged into burst signals or continuously. It is possible to easily rearrange the signal arrangement, and the pulse signal to be positioned at the beginning of the N pulse signals can be specified using the synchronization signal. Therefore, each pulse signal of the pulse train signal output from this pulse train conversion device can be translated in parallel to an arbitrary bit position.

FIG. 4 is a block diagram showing a schematic configuration of a pulse train converter according to still another embodiment of the present invention. The same parts as in FIG. 1 are given the same reference numerals. Therefore, detailed explanation of the overlapping parts will be omitted.

In this embodiment, the changeover switch 21
A serial/parallel conversion circuit 30 is inserted between the data terminal D of the write-only port of the data memory 2 and the data terminal D of the read-only port of the data memory 2, and a parallel/serial converter circuit 30 is inserted between the data terminal D of the read-only port of the data memory 2 and the output terminal 8. A conversion circuit 31 is inserted.

With the pulse train conversion device configured in this manner, the number of cycles for writing and reading one pulse train signal to and from the data memory 2 is reduced, so that the pulse train conversion processing speed can be increased.

[0043]

As explained above, according to the pulse train conversion device of the present invention, the timing for initializing the write address counter and the read address counter can be externally given by the first and second synchronization signals. It consists of Therefore, not only can an array of N pulse signals within one frame of a pulse train signal be converted into a burst signal or a continuous signal, but also an arbitrary number of pulse signals within one frame can be converted into a burst signal or continuous signal. The pulse signal can be set as the leading pulse signal, each bit position of all pulse signals within one frame can be moved in parallel, and the selection range of the output pulse train signal can be easily expanded.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a pulse train conversion device according to an embodiment of the present invention;

[Fig. 2] A time chart showing the operation of the same embodiment device;

FIG. 3 is a block diagram showing a schematic configuration of a pulse train conversion device according to another embodiment of the present invention;

FIG. 4 is a block diagram showing a schematic configuration of a pulse train conversion device according to yet another embodiment of the present invention;

[Figure 5]
A diagram showing the frame structure of a synchronous interface,

[Fig. 6] A diagram showing a pulse train signal with the same frame configuration,

[Fig. 7] A block diagram showing a schematic configuration of a conventional pulse train conversion device,

[Fig. 8] A time chart showing the operation of the conventional device.

FIG. 9 is a block diagram showing a schematic configuration of another conventional pulse train conversion device;

FIG. 10 is a time chart showing the operation of the conventional device.

[Explanation of symbols]

1, 3, 23, 26...input terminal, 2...data memory, 4
...Write address counter, 5, 10...Clock conversion circuit,
7...Read address counter, 11...And gate, 21
, 24, 27... Changeover switch, 22, 25, 28... Delay circuit, 29... Counter control section, 30... Series/variable series conversion circuit, 31... Parallel/serial conversion circuit.

Claims (1)

[Claims] [Claim 1] A plurality of pulse signals are first transmitted within a specified period.
a data memory (2) having a write-only port and a read-only port into which a first pulse train signal stored in an array is input, and a timing at which each pulse signal of the first pulse train signal is generated; a write address counter (4) that sequentially specifies write addresses to write-only ports of the data memory in synchronization with a first clock signal; and a second clock generation timing for the first clock signal. Clock conversion circuit that converts to clock generation timing (
5) and a read address counter (7) that sequentially specifies a read address to the read-only port of the data memory in synchronization with the second clock signal output from the clock conversion circuit, A plurality of pulse signals are transmitted from the read-only port of the memory within the specified period to a second pulse signal corresponding to the clock generation timing of the second clock signal.
In the pulse train conversion device for reading out a second pulse train signal stored in an arrangement, the generation of a first pulse signal among a plurality of pulse signals in the first pulse train signal having the same period as the specified period. The address value of the write address counter is initialized by a first synchronization signal synchronized with the timing, and the address value of the write address counter is initialized by a first synchronization signal that has the same period as the specified period, and the second synchronization signal among the plurality of pulse signals in the first pulse train signal. A pulse train conversion device, characterized in that the address value of the read address counter is initialized by a second synchronization signal synchronized with the generation timing of a pulse signal to be positioned at the head of the pulse train signal.