JPH03201842A - Buffer device - Google Patents

Abstract

PURPOSE:To make circuit scale compact by sharing one memory means for phase difference between transmission and reception data and further deviating access timing even when the competition of access is generated. CONSTITUTION:When an address to be accessed by respective two ports is competed, a memory means 31 gives a priority right to one port and inhibits the access to the other port. Thus, since a detecting means 38 (27) connected to one inhibited port stops referring a transmission clock, an address generating means 23 (24) stops the address output operation during the inhibition. Since the inhibition is released when the access of the port on the priority right side is finished, the operation is restarted and the address, which is competed at the time of the above mentioned competition, is accessed again. Therefore, since timing is deviated afterwards, the competition of the access is not generated between the two ports. Thus, transmission and reception systems can be exchanged through the common memory 31.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is used, for example, in an interface of an electronic exchange used in connection with an ISDN line, and is used to communicate between mutually asynchronous communication channels. The present invention relates to improvements in elastic buffer devices used to absorb phase differences that are a problem when transmitting and receiving transmission frames.

(Prior Art) In recent years, with the advancement of communication technology and the diversification of communication forms, various communication network systems have been developed.
egrated 5 services digital
network). This l5DN provides telephone, data, facsimile communication, and various communication processing services in one digital communication network.
A communication system using DN is configured as follows, for example.

In other words, this system has an 15DN switch to which a digital circuit switching network, a packet switching network, a common line signaling network, etc. In the home, this network termination device is connected to a home bus, and communication terminal devices such as a telephone device, facsimile device, voice mail device, printing device, personal computer, etc. are connected to the home bus. Then, desired communication is performed between communication terminal devices by selectively using a plurality of communication channels for each subscriber line. For example, in a primary group basic interface with a transmission rate of 192 bits/s, two B channels of 64 bits/s and 16
It is possible to time-division multiplex the K bit/sec D channels and use these channels to transmit data and the like.

The configuration of the electronic exchange in such an 15DN network is described in the sixth section.
As shown in the figure.

The basic configuration of an l5DN switch is an l5DN interface 3 that interfaces with the l5DN network, and an l5D
A time division switch unit 1 for exchanging digital data sent and received from the N network, a PLL (phase locked loop) circuit 2 for synchronizing the sampling frequency of the 15DN network and the sampling frequency of the electronic exchange, and an interface 5 for the extension telephone. , a central control circuit 4 that controls the time division switch unit 1, the L5DN interface 3, the extension telephone interface 5, etc., and controls the exchange in response to call route creation, call termination monitoring, and other L5DN services. .

An example of operation when the l5DN interface 3 is a primary group interface will be shown below.

FIG. 7 is a block diagram showing the internal configuration of the ISDN primary group interface 3, and as shown in the figure, the receiver 6
, sampling & framing circuit 7, clock extraction circuit 8, reception converter 9, transmission converter lO1
It is composed of a frequency divider 11, a protocol control circuit 12, a transmitter 13, a PLL circuit 14, an elastic buffer 15, and the like.

A M 1 (Alter
The receiver 6 converts the nateMark Inversion code signal into a signal compatible with the operating level of the digital IC in the circuit, such as the TTL level or CMOS level. The output signal of the receiver 6 is a signal obtained by normalizing the AMI code, and a clock signal is superimposed on this signal. Therefore, we separate this clock and l5
The clock extraction circuit 8 generates a clock for sampling the data received from the DN.

Based on the clock signal separated and output by the clock extraction circuit 8, the sampling and frame 2 fufu circuit 7
samples the received data, then extracts frame bits from this sampled received data,
Each channel of the received data is sequentially output as serial data at a speed of 1,544 Mbps, starting with channel 1.

In this way, in the sampling and frame 2 fufu circuit 7,
It performs sampling and frame synchronization of the received data from the 15DN line, and sequentially outputs the received data as 1.544 Mbps serial data (PCM data). Here, data up to ch24 (data channel 24) is read by the protocol control circuit 12 and protocol control is performed. As a result of the protocol control, information for CPU control is transferred to the protocol control circuit 12 via the CPU control bus.
and the central control circuit 4, the extension reading control and the time division switch 1 are controlled, and a communication path is formed.

Next, the process until the communication path is formed, that is, until the PCM data output from the sampling and frame 2 fufu circuit 7 is sent to the PCM highway of the electronic exchange will be explained.

The received data obtained by sampling and frame synchronization in the sampling and frame 2 fufu circuit 7 is 1.54
Although I have already mentioned that the speed is 4 Mbps, this received serial data is 24 channels worth (64 Kbps
24; Therefore, 64 Kbps x 24 + framing bits (8 bits) - 1,544 Mbps) are multiplexed, and has a frame pulse indicating chi (channel 1).

The receiving converter 9 for converting from 1.544 Mbps to 2.048 Mbps converts the C
Determine hl (channel 1) and read 1.544 MbpS serial data. The clock signal used for this reading is the output clock of the clock extraction circuit 8, that is, the sampling clock.

The receiving converter 9 converts the output data of the sampling and frame 2 fufu circuit 7 at a transmission rate of 1.544 Mbps to a data rate of 2.048 Mbps. This converted output is sent to the elastic buffer 15, which is an interface with the PCM highway 16 side of the electronic exchange.

The speed conversion is shown in Figure 8(a), and the speed conversion in the receiving system is from 1.544 Mbps to 2.048 Mb.
Since it is converted to ps, 64K per channel
bps, 2,048 Mbps is 64Kbps
Since sX is 32 and the actual number of transmission channels is 24, there are 8 channels left. Therefore, 64K
Data is not transmitted for bpS×8 channels.

In other words, 24 channels from i to channel 24 are multiplexed and transmitted, and at a speed of 1.544 Mbps, this is sent in 125 μs, but 1.544 Mb
When converting the data rate from ps to 2.048 Mbps, it takes 125 μs to convert to 2.048 Mbps, so the capacity is equivalent to 32 channels. However, it increased by 8
The time slots for the channels (time slots 25 to 32) are set to high impedance and are not used for actual data transmission.

The output data whose speed has been converted by the converter 9 in this manner is sent to the elastic buffer 15 and held there for a period of time. The elastic buffer 15 is composed of a memory that stores one frame of data, and is configured to synchronize between the PCM synchronization signal on the converter side (converter 9 and 10 side) and the received frame synchronization signal (frame pulse) in the 15DN interface 3. It plays the role of absorbing the phase between.

There are two main reasons for this. One is that there is no synchronization relationship between the L5DN line side and the PCM highway on the exchange side, so the received data on the L5DN line side and the PCM highway on the exchange side
This is because the phase differs from that of the CM highway, and a buffer is required to absorb this phase difference.

The other reason is that the received data received from the 15DN line contains jitter and wander, and it is necessary to absorb temporal fluctuations.

The elastic buffer 15 is configured to absorb these phase shifts, jitters, and wanders.

In this way, the received data is transferred to the elastic buffer 9 above.
This absorbs phase absorption and fluctuations in the received data such as jitter and wander, and then transmits the PCM0M Highlight 1 from the electronic exchange side. Normally PCM Highway 16 is 2.04
8Mbps, that is, 32 channels of communication path PCM
It is a highway in which data is multiplexed, and switching connections are made by a time division time switch 1. Also, l5D
Since the transmission of the N-order group interface multiplexes 24 channels, the speed conversion described above is necessary.

Transmission from the PCM highway 16 to the 15DN network was received via the elastic buffer 15 at a transmission rate of 2.04
The transmission converter 10 converts 8 Mbps data into 1.
Speed conversion to 544 Mbps. This is Figure 8(b)
As shown in FIG. 3, this is done by removing the last 8 channels of the 32-channel time slot to extract the 24-channel time slots from the 1 channel to the 24th channel. This is given to the frame bit adding circuit 13,
Here, frame bits are added and given to the transmitter 13 to be sent to the 15DN network.

Here, the elastic buffer 15.2.048 Mbps/1.5441 performs phase absorption between the l5DN primary group interface and the time division switch 1 on the exchange side.
Converter which is a 4 bps converter 9. The IO operation clock will be explained.

First, a 1,544 MHz clock created from received data is divided by a frequency divider 11 to create an 8K11z clock. This is obtained by dividing the 1.544 MHz clock by 192. Next, the PLL circuit 14 multiplies the 8 KHz clock to
．． 544 MHz, creating a 2.048 MHz clock.

1.544 MHz is a transmission clock, and the PLL circuit 14 is configured to be able to transmit 1.544 MHz by itself so that it can transmit even if received data cannot be obtained due to line failure or the like. Also, 2.048 M
Data sent at a transmission rate of bps is 1.544
It is also used as a read clock for the transmitting converter IO for speed conversion to Mbps transmission speed.

2.048 MHz is also created in the same way as 1.544 MHz, 2, (148 Mbps/ 1.544 Mbp
2.041i Mb of the transmitting converter 10 that converts
The ps-side data-poor data-inclusive clock is also used as a read clock for the elastic buffer 15 and the receiving converter 9. Further, the converter 9.10 and the elastic buffer 15 operate in synchronization with the frame pulse of the PLL circuit 14.

The reason for using a system that performs such synchronization is as follows.

Typically, the switch and the 15DN interface are configured to create a system that is synchronized at the sampling frequency.

This is because when the transmission speeds are different, a dropout occurs in the data transmission speed. , 2.048 MHz is obtained and given as a clock signal to the time division switch (on the exchange side) to perform frequency synchronization.As a result, although the frequency becomes synchronized, the phase cannot be synchronized. , there will always be a difference in position between channel 1 of the PCM highway 16 and channel 1 of the 15DN.The above-mentioned elastic buffer 15 absorbs this.

Data exchange between the exchange side and the l5DN interface 3 is performed through the elastic buffer 15 in this way, but within the l5DN interface 3
It is necessary to convert the speed from 8 Mbps to 1.544 Mbps.

Also, since a large number of l5DN interface cards are accommodated in one exchange, each l5DN interface 3 operates independently and separately on the exchange side, and the PCM
It is configured so that it is only necessary to exchange data with the highway and CPU control data, and no special control is required. To do this, elastic buffer i5 is used as an interface with PCM highway I6.

Next, the operation of the elastic buffer 15 will be explained.

FIG. 9 is a conceptual diagram of the elastic buffer 15,
When a frame synchronization signal for input data is input, the write address counter WCA is reset, and the input data is written into the memory M from its first address position. The address of the write address counter WCA is sequentially updated by the data clock, and manual data is written to the address position indicated at each time.

On the other hand, reading from the memory M is performed for the address corresponding to the address indicated by the read address counter RCA, but when the frame synchronization signal on the output data side is input, the read address RCA is reset. Data is read out according to the contents of counter RC^.

In this way, since the operation of writing input data to the memory M and the operation of reading it from the memory M are independent, it is possible to absorb the phase of the input end and the output side.

However, the elastic buffer 15 must be provided for each system, such as for absorbing the phase of reception data and for absorbing the phase of transmission data, which inevitably increases the circuit scale.

Therefore, it is conceivable to create a configuration that uses only one frame's worth of memory for both transmitting and receiving, but although this can be expected to reduce the size and cost, the transmitting system and receiving system cannot be synchronized with each other. Because data is handled without thinking, if the input system and output system use a shared memory, data access conflicts are inevitable.

(Problem to be Solved by the Invention) As mentioned above, in the 15DN exchange, there is no synchronization relationship between the phase of the data transmitted within the exchange and the phase of the data transmitted on the network, so errors occur due to the absorption of these phases. A stick buffer is provided, and the data to be exchanged is taken in once and then read out.

On the other hand, since there is no synchronous relationship between the data exchange between the PCM highway and the elastic buffer inside the exchange, and between the elastic buffer and the transmitting and receiving converters, It is not possible to provide a configuration in which only one system of large-capacity memory is provided and this is shared between the transmitting system and the receiving system.

In other words, when the transmitting system and the receiving system use shared memory, data access collisions are unavoidable, so with the elastic buffer, a memory with a memory capacity for each frame is used for transmitting data. , it is necessary to prepare each for receiving data.

Therefore, the circuit scale of the device inevitably increases, and since a plurality of 15DN interfaces are provided in the exchange, there are problems in that the device increases in size and cost store knobs are unavoidable.

Therefore, it is an object of the present invention to provide the desired function without any problem even if the elastic buffer is configured with a memory shared for transmission and reception only for one frame.
It is an object of the present invention to provide a buffer device that can suppress an increase in circuit scale and reduce costs.

[Structure of the invention]

(Means for solving the problem) In order to achieve the above object, the present invention is configured as follows. In other words, the received transmission frame is temporarily held in order to send and receive the transmission frame, which is made up of multiple time slots and is used to transmit data of multiple channels using the time slots assigned to each channel, between different communication channels. The buffer device absorbs the phase difference between the communication paths by reading and transmitting data in synchronization with the time slots on the sending side, the buffer device having memory addresses for at least the number of time slots constituting a transmission frame, It has two access ports, and these ports are made to correspond to the transmission line, and in response to the access command of each port, the port receiving the access command exchanges data, and the two ports address the same address. A shared memory means for transmitting and receiving, which has a contention control function that gives priority to one side and prohibits access to the other in case of contention for access; A buffer means for supplying data from a corresponding port to the memory means, and a frame synchronization signal provided for each of the boats, which synchronizes the frame with a frame synchronization signal obtained from the communication path side corresponding to the boat, and synchronizes the frame with a transmission clock on the communication path side. a detection means for detecting a current time slot in a transmission frame by using the memory means, and stopping detection of the time slot for a period of prohibition for a designated port of the memory means; and a detection means provided for each of the ports and corresponding to the port. address generating means for each port, which generates write address information corresponding to the current time slot and read address information corresponding to the previous time slot based on the outputs of the respective ports; The timing is determined based on the time slot detection output of the detection means corresponding to the port, and the timing at which the address generation means generates the read address information in order to read the transmission data at the timing when the address generation means generates the write address information. The apparatus further comprises timing control means for giving an access command to the corresponding port in order to sometimes write the received data held in the buffer means to the memory means.

(Function) In such a configuration, when sending and receiving transmission frames between different communication paths, a memory means for both sending and receiving having a contention control function is used, and on one side of the communication path, access is made from one port of this memory means. , on the other side of the communication path, the received transmission frame is temporarily held in this memory means by accessing it from the other port of this memory means,
By reading out and sending data in synchronization with the time slot on the exit side, transmission and reception are performed while absorbing phase differences between communication channels.

That is, on each communication path side, the received data obtained from the communication path side is temporarily held in the corresponding buffer means, and the detection means corresponding to each port receives the frame synchronization signal and the frame synchronization signal obtained from the communication path side corresponding to the port. Using the transmission ports and links, frame synchronization is achieved using a frame synchronization signal among these, and the current time slot in the transmission frame is detected by referring to the transmission clock.

Then, the address generation means corresponding to each port generates the write address information corresponding to the time slot immediately before the current time slot and the read address information corresponding to the previous time slot, respectively, based on the output of the detection means corresponding to the port. The signals are generated at different timings, and are applied to the memory means from respective corresponding ports to specify an address. On the other hand, the timing control means corresponding to each port detects the timing of each time slot in the transmission frame on the communication path side based on the output of the detection means corresponding to that port, and the address generation means detects the write address information. At the timing when the read address information is generated, a read access command is given to the memory from the corresponding port in order to read the transmitted data, and when the read address information is generated, the received data held in the buffer means corresponding to the port is transferred to the memory. A write access command is given to write to the means.

Therefore, unless there is a conflict (collision) between the addresses that the two ports attempt to access, data received from one communication channel can be passed to the other communication channel while absorbing the phase difference.

If a conflict occurs, the memory means gives priority to one port and prohibits access to others. Therefore, since the detection means connected to the prohibited port stops referring to the transmission clock, the address generation means connected to the prohibited port stops its address output operation during the prohibition period.

Then, when the access of the port that gained priority is completed, the prohibition is lifted and the operation is resumed, and the address that conflicted in the previous conflict will be accessed again. Thereafter, since the timings are different, there will be no access conflict between the two ports.

As a result, when transmitting and receiving transmission frames between two asynchronous communication channels, it becomes possible to transmit and receive frames between the transmitting system and the receiving system via a common memory, which saves memory. Since the memory can be saved, the circuit can be made smaller.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which reference numeral 31 denotes a dual-port RAM (random access memory) shared by the transmitting system and the receiving system. This dual port RAM is a memory that has two access ports and can be accessed simultaneously from the two access ports.This dual port RAM 31 is a memory that has two access ports and can be accessed simultaneously. It is possible to send the signal /BUSY. In other words, when a request to access the same address is received from two ports at the same time, the dual-port RAM 31 sends a busy signal/BUS to the port that requested access later.
The configuration is such that Y is sent out.

20 and 33 are buffers, 21 and 32 are S/P (serial/parallel) converters that convert serial data to parallel data, and 22 and 34 are P/S (parallel/serial) converters that convert parallel data to serial data. 23 and 24 are address generators that generate addresses from the outputs of the counters 27 and 28, and are constructed from ROM (read only memory) or the like.

Reference numerals 25 and 28 are timing generation circuits that generate read/write signals for the dual-port RAM 31 based on the outputs of the counters 27 and 28. The counters 27 and 28 are cleared in synchronization with the frame synchronization signal and are 2.048 MH
It counts the z clock from "0" to "255".

Buffer 20, S/P converter 21, address generator 23
, the timing generation circuit 25, the counter 28, and the P/S converter 34 are the components on the B side, and the buffer 33 and the S/P
The converter 32, address generator 24, timing generator 26, counter 27, and P/S converter 22 are components on the A side.

On the A side, the input terminal AIN is connected to the S/P converter 3.
2, the parallel-converted data once enters the buffer 33, and is manually input to the data input/output terminal DATA (A) on the A port side of the dual port RAM 31.

Further, output data from the data input/output terminal DATA (^) is serially converted by the P/S converter 22 and sent to the A-side output terminal A OUT. The counter 27 is 2,048 Ml generated from the 8 kHz clock extracted from the 15DN line supplied to the A side.
It is an 8-bit counter that counts the lz clock,
Dual port I? When a wait is applied by the busy signal /BUSY on the A port side of AM 31, during that time,
The count is stopped and reset (O
clear).

The address generator 24 generates address data corresponding to the count value of the counter 27, and
6 to the address input terminals ^0~ on the A port side of M31 to specify the address. Further, the timing generation circuit 26 receives the count value of the counter 27 and generates a write/read signal when the lower bit of the count value reaches a predetermined value.

Further, when the lower bit of the count value of the counter 27 reaches a predetermined value, the buffer 33 closes its gate and sends the held data to the A port side of the dual port RAM 31.

In addition, on the B side, the input of the input terminal BIN enters the S/P converter 21, and the data parallel-converted here temporarily enters the buffer 20 and is transferred to the dual-port l-RAM.
The data is input to the data input/output terminal DATA(B) on the B port side of 31.

Further, the output data from the data input/output terminal DATA (B) is serially converted by the P/S converter 34 and sent to the B side output terminal BOUT. The counter 28 is a 5-bit counter that counts the 2,048 MHz clock that is generated inside the exchange and is supplied to the B side.
When a wait is applied by the busy signal /BUSY on the B port side of the switch, the count is stopped during that time, and is reset (cleared to 0) by the frame synchronization signal extracted from the received frame from the PCM highway inside the switch. It has become.

The address generator 23 generates address data corresponding to the count value of the counter 2B, and
Specify the address by giving it to the address input terminal AO~ on the B port side of M31. Further, the timing generating circuit 25 receives the count value of the counter 26 and generates a write/read signal when the lower bit of the count value reaches a predetermined value. Further, when the lower bit of the count value of the counter 26 reaches a predetermined value, the buffer 20 closes the gate and sends the held data to the B port side of the dual port RAM 31.

FIG. 2 is a diagram showing the operation timing of the apparatus of the present invention shown in FIG. 1, and FIG. 3 is a time chart showing the operation of access collision. These operations will be explained below, but first, the dual port I? AM 31 will be briefly explained using FIG. 5.

As shown in FIG. 5, the dual port RAM 31 has one memory array 3 (2) therein, and this memory array 312 is provided with 82 110 ports.

Of these ports, A boat has 110 ports and 31 ports.
3 and a decoder 315 that specifies an address, and the B port has an I10 buffer 314 and a decoder 316 that specifies an address.

I10 buffers 313 and 314 are memory array 312
The decoders 315 and 318 decode address information input from their own ports to specify read/write addresses of the memory array 312.

Here, in the dual port RAM 31, the above two I
Memory array 312 can be accessed simultaneously from any of the 10 ports. Therefore, there is a problem of access conflict occurring. That is, this is a case where the same address is attempted to be accessed from both the A and 8 ports, which are I10 ports, at the same time.

For this purpose, we will monitor the access status of both ports A and 8.
Conflict circuit 317 that performs conflict prevention control to allow only one access when attempting to access the same address at the same time.
is the provision. In this case, the port whose address is determined first is given priority, and the port that arrives later with the same address
A busy signal/BLI is sent to the port that issued the access request.
SY is sent, and reading/writing from that port is prohibited. Further, at this time, internally, writing to the memory array 312 from the port to which the busy signal /BUSY is output is prevented. (However, "/" indicates negative logic.) The manner in which the busy signal /B[ISY is output is as shown in FIG. 4. However, in the figure, (b) to (d),
(+) indicates each signal of A port, and (f) to (h)
, (j) shows each signal of the B port.

When an access request is made from one port specifying the same address, a busy signal /BtlSY is sent to the other port until the request is completed, so if an access conflict occurs between both ports, On the other hand, the side that makes the request late receives this busy signal /BUSY and is prohibited from accessing it. If the addresses are not the same, both ports can access the port at the same time.

The operation of the dual port RAM 31 has been described above. Next, the operation of the elastic node according to the present invention will be explained.

First, since the elastic buffer is used to absorb the phase difference between the A side (15DN line side) and the B side (PCM/X way side inside the exchange), separate frame synchronization signals, 2.048 The MHz link is input, but the frame synchronization signal on each side and the 2,048 Mbps data input and output are the time slot TS32 of the 32nd channel and the time slot of the 1st channel, as shown in Figure 2. The circuit in FIG. 1 is constructed so as to have a relationship that occurs at the boundary with the slot TSI.

Therefore, when the pulse of the frame synchronization signal is active (negative pulse), it means time slot 1 of 2.048 Mbps serial data.

2.048 Mbps serial data in such a format is written to the dual port RAM 31,
The signals are read out from the opposite port after a certain phase and output as serial data.

First, this process will be explained. First, serial data input manually from the input terminal AIN is converted into parallel data by the S/P converter 32. And buffer 33
Send it to and hold it temporarily. This is dual port 1-RAM
31, the writing timing is determined by the output of the counter 27 on the A side.

For example, among the serial data manually input to the input terminal AIN, is it data of time slot TS2 or dual port I? AM 31 is written in time slot T
After receiving 8 bit data in S2,
The timing generation circuit 26 uses the counter 2 to determine this timing.
Since the write signal (write signal) created by this timing creation circuit 26 is applied to the A port of the dual port RAM 31, the timing at this time is known from the count value of the counter 27. At the same time as the buffer 33 is closed, the data held in the buffer 33 is sent to the data output terminal of the dual port RAM 31.

This timing is performed using the count output of the counter 27 as follows.

For example, the counter 27 counts from "0" to "255" and counts a 2.048 MHz clock, so one time slot (125 μS/
32 slots), 8 clocks are manually input, and the counter 27 increments by 8 counts. Therefore, in one time slot, counter 2
The output of 7 is “ooo b” ~ “111b” (however,
b indicates binary notation) are output sequentially, and as far as we look at the lower 2 bits, the output is the same in any time slot from 1 to 32, so the lower 2 bits, that is, 2° If you use the AND output of bit and 2” bit, you can access twice within one time slot, for example, “72°bit” AND “/2” bit ” A
ND Write when "722bit" - "H" or "/2°bit" AND "/2'bit"A
Timing can be easily created by setting conditions such as ND "22bit" - "H" read.

The data of time slot TS2 written at the same timing in this manner is converted from the counter output by the address generator 24 to the memory address "02H" of the dual port RAM 31 (where 11 indicates hexadecimal notation). .

This address can be created by predetermining the address for the counter output using the ROM.

In this case, the address is changed when reading/writing the dual port RAM 31, and the address is set so that the address written on the A port side is read on the B port side. The same process is performed on the B port side using B components.

An example of operation is shown in FIG. In this operation example, output terminal A
OUT is used for transmission output from the exchange to the l5DN line, output terminal B OUT is used for reception output from the l5DN line to the exchange, and input terminal AIN is used for the reception output from the l5DN line to the exchange.
The case is shown in which the input terminal BIN is used for receiving output from the DN line to the exchange, and the input terminal BIN is used for transmitting output from the exchange to the 15DN line.

Each time slot in a manually-operated frame) TSn
The data (nJ, l, 2, ~31) is written to the dual port RAM 31 at the beginning of the next time slot, and then read from the dual port RAM 31 within the period of the current time slot and output to the output terminal side. be done.

In the dual port RAM 31, addresses are associated with time slots, and written data is written to the corresponding address of the time slot to which the data belongs. Further, data to be read is carried out to an address corresponding to the time slot next to the current time slot so that the data corresponds to the actual time slot when the data is sent out.

Then, on the A side and the B side, a frame synchronization signal and 2.0
Since the 48 MHz clock signals are provided from completely different systems, normally the time slots do not coincide.

Therefore, there is no conflict in the memory address to be accessed, and therefore dual port I? AM31 can be accessed on both the A side and the B side.

In particular, in a frame, time slots are arranged in order from 0 to 32, so before side B reads the data updated on side A,
There is no worry that the data will be updated on the side B, and there is no worry that the data updated on the B side will be updated on the B side before the A side reads it. Therefore, it becomes possible to transmit and receive data using a shared memory.

After performing the above operations, from the input terminal AIN side to the output terminal B
The phase difference T during transmission to the 01JT side can be absorbed, and the output terminal A 0tlT from the input terminal BIN side can be absorbed.
It is possible to absorb the phase difference T during transmission to the side.

In this way, an elastic buffer can be configured by using one dual port RAM and sharing it with the transmitting system and the receiving system. The above is a normal state.

However, if the operation example shown in FIG. 4 occurs, in the operation example shown in FIG. This is the timing at which the data of this time slot TS2 is read.

That is, since the storage address of time slot TS2 is fixed, both the A boat and the B boat access the same address.

When such contention occurs, dual-port RAM 3
1 outputs a busy signal /BUSY to the port that made an access request later, and at the same time prohibits access from that port in the dual port RAM 31.

In this case, since the request is from the B port later, the busy signal /BO8Y is output to the B port, and the counter 2B on the B port side enters a wait state and stops counting. Then, when the access on the A port side is completed, B
The access prohibition on the port side is lifted and the busy signal/BuS
Y becomes inactive, and the storage address of time slot TS2 is accessed to the dual port RAM 31 on the B boat side.

After executing the read of the storage address of time slot TS2, the timing creation circuit 25 creates a timing based on the output of the B-side counter 28, which resumes counting in the same way as when writing, and reads the storage address of time slot TS2 in the dual port RAM 31. The data stored in the serial bus is serially converted by the parallel/serial conversion circuit 34, and is output to the serial bus as data that enters the time slot TS2.

In this way, when an access conflict occurs, address matching and data access occur at the same time, so as mentioned above, the dual port RAM 31 responds to the access request received earlier by the side that issued the access request later. If the busy signal /13USY for the port is activated and, for example, the A side issues an access request first, the busy signal /BUSY for the B side from the dual baud RAM 31 becomes active, and this activation causes the counter on the B side to If the count operation of 28 is waited, counting can be stopped during this time, so that after the A side finishes accessing, the B side can access. That is, when the A side finishes accessing, /BUSY disappears, so the B side's count is restarted, and the access request from the B side can be executed under timing control.

The wait period of the counter 27 in this operation process is
If it only takes one clock of the 2.048 MHz clock, the counter 27 will advance the count again at the next tally after the count is stopped, so the data access on the B side will be 1 clock compared to the normal operation. clock minutes,
It will be possible to implement it even if it is delayed.

In addition, when the above weight occurs when counting,
This shifts the access timing, so
No contention will occur for the next access to the dual port RAM 31.

The counter weight due to contention is 2.048 Ml(z
Up to four clocks, or four times, are allowed.

However, it can be said that access conflicts rarely occur so many times within one frame. Therefore, if the operation is normal, even if access conflicts occur, 1
As a result, problems caused by improper timing will not occur.

In this way, the device consists of multiple time slots,
In order to send and receive transmission frames for transmitting data from multiple channels using the time slots assigned to each channel between redundant communication channels, the received transmission frames are temporarily held and synchronized with the time slots on the sending side. For example, an L5D installed in an electronic exchange is designed to absorb phase differences between transmitting and receiving communication channels by reading and sending out the data.
As an elastic buffer used for absorbing the phase difference between the electronic exchange and the 15DN interface in the N interface, it is possible to secure memory addresses for at least the number of time slots constituting the transmission frame, and each has two access ports. In response to an access command from a boat, data can be exchanged with the boat that received the command, and in the case of conflicting accesses to the same address, one is given priority and the other is prohibited from accessing. a memory means for shared transmission and reception, for example, a dual-port RAM having a contention control function; a first buffer means for temporarily holding received data obtained from one communication channel side and supplying the data to the memory means from one port; Using a frame synchronization signal and a transmission clock obtained from one of the communication channels, the frame synchronization signal is used to synchronize the frame, and the current time slot in the transmission frame is detected by referring to the transmission clock. While receiving a prohibition order,
A first detection means (first counter) that stops referring to the transmission clock, and first address information corresponding to the time slot immediately before the current time slot and its first address information based on the output of the first detection means. a first address generating means for generating second address information corresponding to a previous time slot at different timings and applying the second address information to the one port of the memory means to specify an address; and an output of the first detecting means. The memory detects the timing of each time slot in the transmission frame on the one communication path side based on A read command is given to the means from the one port, and a write command is given from the one port to write the received data held in the first buffer means to the memory means at the timing of generating the second address information. a second buffer means for temporarily holding received data obtained from the other communication path and supplying it to the memory means from the other port; and frame synchronization obtained from the other communication path. A signal and a transmission clock are used to perform frame synchronization with a frame synchronization signal among them, and to detect the current time slot in the transmission frame with reference to the transmission clock, and to detect the current time slot in the transmission frame with reference to the transmission clock, a second detection means (second counter) that stops referring to the transmission clock while receiving a prohibition command; and a second detection means (second counter) that stops referring to the transmission clock; a second address generation means for generating third address information and fourth address information corresponding to the previous time slot at different timings and applying them to the other port of the memory means to specify an address; Detecting the timing of each time slot in the transmission frame on the other communication path side based on the output of the detection means, and reading the transmission data at the timing when the second address generation means generates the third address information. A read command is given to the memory from the other port in order to write the received data held in the second buffer means to the memory means at the timing of generating the fourth address information. The second timing control means provides a write command.

In such a configuration, when sending and receiving transmission frames between different communication paths, a shared memory means for transmitting and receiving having a contention control function is used, and one port of the memory means is accessed on one side of the communication path, and the other side is accessed from one port of this memory means. On the communication path side, by accessing from the other port of this memory means, the received transmission frame is temporarily held in this memory means, and is read out and sent out in synchronization with the time slot on the sending side, thereby changing the position between the communication paths. Transmission and reception absorb phase differences, etc., but it is possible to secure at least as many memory addresses as the number of constituent time slots of the transmission frame, and has two access ports so that each port can respond to access commands from the port that received the command. A shared memory means for transmitting and receiving, which has a contention control function that allows data to be exchanged between the two, and in the event of conflicting access to the same address, gives priority to one and prohibits access to the other.
Use only strains.

On one communication path side, the received data obtained from the communication path side is temporarily held in a first buffer means, and the first detection means uses a frame synchronization signal and a transmission clock obtained from the one communication path side. , among these, the frame synchronization signal is used to achieve frame synchronization, and the current time slot in the transmission frame is detected by referring to the transmission clock. Then, the first address generation means generates first address information corresponding to the time slot immediately before the current time slot and second address information corresponding to the previous time slot, respectively, based on the output of the first detection means. The first timing control means generates the transmission frame on the one communication path side based on the output of the first detection means. detecting the timing of each time slot in the first address generation means and giving a read command from the first port to the memory means in order to read the transmission data at the timing when the first address generation means generates the first address information; At the timing of generating the second address information, a write command is given from the first port in order to write the received data held in the first buffer means into the memory means.

Similarly, on the other communication path side, the received data obtained from the communication path side is temporarily held in a second buffer means, and the second detection means receives the frame synchronization signal and transmission clock obtained from the other communication path side. Among these, the frame synchronization signal is used to achieve frame synchronization, and the current time slot in the transmission frame is detected by referring to the transmission clock.

Then, the second address generation means generates third address information corresponding to the time slot immediately before the current time slot and fourth address information corresponding to the previous time slot, respectively, based on the output of the second detection means. The signals are generated at different timings and are applied from the other port to specify the address of the memory means, while the timing control means of i2 determines the transmission frame on the one communication path side based on the output of the second detection means. detecting the timing of each time slot in the second address generation means and giving a read command from the other port to the memory means in order to read the transmission data at the timing when the second address generation means generates the third address information; At the timing of generating the fourth address information, an operation is performed in which a write command is given from the other port in order to write the received data held in the second buffer means into the memory means.

Therefore, unless there is a conflict (collision) between the addresses that the two ports attempt to access, data received from one communication channel can be passed to the other communication channel while absorbing the phase difference.

If a conflict occurs, the memory means gives priority to one port and prohibits access to the others. Therefore, the detection means connected to the prohibited port stops referring to the transmission clock, so the address generation means connected to the prohibited port stops its address output operation during the prohibition period. Then, when the access of the port that gained priority is completed, the prohibition is lifted and the operation is resumed, and the address that conflicted in the previous conflict will be accessed again. Thereafter, since the timings are different, there will be no access conflict between the two ports.

As a result, when transmitting and receiving transmission frames between two asynchronous communication channels, it becomes possible to transmit and receive frames between the transmitting system and the receiving system via a common memory, which saves memory. Since the memory can be saved, the circuit can be made smaller.

In this way, this device can implement an elastic buffer that absorbs the phase difference between the electronic exchange and the I5DN interface in the I5DN interface housed in the electronic exchange by using the dual port RAM for both transmission and reception. Since it can be operated to absorb the phase difference again after shifting the timing, the desired function can be obtained without any problem even if the elastic buffer is configured using only one frame's worth of memory. This makes it possible to suppress the increase in circuit scale and reduce costs.

Note that the present invention is not limited to the embodiments described above and shown in the drawings, and can be implemented with appropriate modifications within the scope of the gist thereof. For example, in the above embodiments, a dual port RAM may be used. However, if the drive circuit is configured so that different addresses can be accessed simultaneously as a shared memory, other memory elements can be used instead.

〔Effect of the invention〕

As explained above, the present invention can realize the phase difference between transmitted and received data by sharing one dual port RAM, and is configured to shift the access timing even if access contention occurs. The elastic buffer can be configured with a simple circuit using a dual-port RAM for both transmission and reception, and therefore the circuit scale can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a timing chart for explaining its operation, FIG. 3 is a diagram showing the operation of the elastic buffer according to the present invention, and FIG. A diagram explaining the operation when access conflict occurs in the invented elastic buffer, FIG. 5 is a dual port 1? A diagram showing the inside of AM, Figure 6 is l5DN
FIG. 7 is a block diagram showing the internal configuration of the l5DN primary group interface, FIG. 8 is a diagram explaining speed conversion in the configuration of FIG. 7, and FIG. 9 is a diagram explaining the concept of elastic buffer. It is a figure for explaining. DESCRIPTION OF SYMBOLS 1... Time division switch unit, 2... PLL circuit, 3... 15DN interface, 4... Central control circuit, 5... Extension interface, 6... Receiver, 7... Sampling & framing circuit, 8
... Clock extraction circuit, 9-1.544Mbps → 2.048Mbps conversion receiving converter, lo-2,048Mbps -=
Transmission converter for 1.544Mbps conversion, 11
... Frequency divider, 12... Protocol control circuit, 13... Frame bit addition circuit, 14... PLL
Circuit, I5...Elastic buffer, 31...Dual port RAM, 21, 32...Serial/parallel conversion circuit, 20,
33... Buffer, 22, 34... Parallel/serial conversion circuit, 23,
24... Address generation circuit, 25, 26... Timing generation circuit, 27, 28...
·counter.

Claims (2)

[Claims] (1) In order to send and receive transmission frames, which consist of multiple time slots and are used to transmit data from multiple channels using the time slots assigned to each channel, between different communication channels, the received transmission frame is In a buffer device that absorbs the phase difference between the communication channels by holding, reading and transmitting in synchronization with the time slot on the sending side, the buffer device has memory addresses for at least the number of time slots constituting a transmission frame. , has two access ports, and these ports correspond to the transmission line, and in response to the access command of each port, data is exchanged on the side of the port that received the access command, and the two ports have the same address. memory means for shared transmission and reception, which has a contention control function that gives priority to one side and prohibits access to the other in the event of a conflict for access to;
Buffer means is provided for each of the ports and temporarily holds received data and supplies the held data from the corresponding port to the memory means; Detection means for synchronizing frames using a frame synchronization signal, detecting the current time slot in a transmission frame using a transmission clock on the side of the communication path, and stopping detection of the time slot during a period in which the specified port of the memory means is prohibited. and, provided for each port, shifts the timing of write address information corresponding to the current time slot and read address information corresponding to the previous time slot based on the output of the detection means corresponding to that port. an address generating means corresponding to each port, which is provided corresponding to each port, and timing is determined based on a time slot detection output of the detecting means corresponding to the port, and the address generating means generates the write address information. and timing control means for giving an access command to the corresponding port in order to read the transmitted data at the timing and to write the received data held in the buffer means in the memory means at the timing to generate the read address information. buffer device. (2) The address generating means generates write address information corresponding to the time slot immediately before the current time slot and read address information corresponding to the previous time slot, with respective timings shifted, based on the output of the detecting means. Claim (1) characterized in that
Buffer device as described.