JPH0430239B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency discriminator, and in particular to a voltage controlled oscillator (hereinafter abbreviated as VCO) that oscillates at a substantially constant frequency relationship with a horizontal synchronizing signal of a video signal reproduced from a magnetic recording device or the like. ) relates to a frequency discriminator suitable for controlling the frequency discriminator.

In a home VTR, the chrominance signal is band-converted to the lower frequency side of the FM-modulated luminance signal and recorded.
As is well known, when this band-converted color signal is reproduced, it has time axis fluctuations. For this reason, a method is adopted in which this time axis variation is caused in the carrier signal for conversion to the original band, and the time axis variation included in the reproduced color signal is removed. Typical home VTR
A specific method for removing this time axis variation will be explained using a VHS system VTR as an example.

When recording and playing back NTSC TV signals, the carrier frequency is _40fH ( _fH : horizontal scanning frequency)
The frequency is converted so that At the same time 1H (H:
The phase is shifted by 90 degrees every (horizontal scanning period), and the direction of this phase shift is alternately switched between a delay direction and a advance direction for each field. The signal is processed as follows. The color signal converted to a low frequency in this manner is hereinafter referred to as a low frequency converted color signal. This low-pass converted color signal is reproduced to restore the original color subcarrier frequency f _SC (=
3.579545MHz), a color signal processing circuit configured as shown in FIG. 1 is used. 1 is the first input terminal to which the reproduced low-frequency conversion color signal including time axis fluctuation is input; 2 is the second input terminal to which the head pulse synchronized with the rotation of the cylinder in which the video head is mounted is input. , 3 is a third input terminal for inputting a horizontal synchronizing pulse that is separated from the reproduced luminance signal and includes approximately the same time axis variation as the reproduced low-frequency converted color signal, and 4 also receives the reproduced low-frequency converted color signal. 5 is a first multiplication circuit for converting the frequency into a color signal with a _frequency of
6 is a burst gate circuit for extracting the burst component from the first BPF output, 7 is a phase comparison circuit, 8 is an oscillator that oscillates at f _SC , 9 is a frequency discriminator, and 10 is a phase comparison circuit 7. An addition circuit that adds the output and the output of the frequency discriminator 9, 11 is an oscillator (VCO) that oscillates at a center frequency of _160fH , and 12 is an
A 1/4 frequency divider circuit that divides the output of VCO11 into 1/4 and outputs a 4-phase _40fH signal with a phase shift of 90 degrees.
13 is a switching circuit that is controlled by a horizontal synchronizing pulse and a head pulse and outputs a four-phase 40f _H signal by switching it every 1H, realizing a 90° phase delay for each H and a 90° phase lead for each H; 11 is a second multiplier circuit that multiplies the output of the switching circuit 13 and the output of the oscillator output 8; 15 is a phase shift of 90° for each H from the output of the second multiplier circuit 14 (f _SC +40f _H ) This is a second BPF for extracting a continuous frequency signal.

The carrier frequency of the color signal input from the first input terminal 1 is 40f _H +Δf (Δf is frequency variation due to time axis variation). On the other hand, the second multiplier 1
4, the output of the oscillator 8 and the output of the switching circuit 13 are multiplied. If the frequency of the VCO 11 is 160f _H , the frequency of the output of the switching circuit 11 is 40f _H , so the output of the second multiplication circuit 13 is (f _SC +40f _H ) and (f _SC -40f _H ) are obtained. The second BPF 15 extracts the (f _SC +40f _H ) component. This (f _SC +40f _H )
Since the component and the color signal are multiplied by the first multiplication circuit 4, the carrier frequency becomes (f _SC −△f) and (f _SC +240f _H
+Δf) two types of color signals are obtained. first
BPF 5 extracts the color signal of (f _SC −△f) from among these. Since this (f _SC −△f) frequency is the frequency of the burst signal, the phase comparator circuit 7 uses the oscillator 8
When the phases are compared, there is a frequency difference of -Δf, so a comparison output corresponding to this frequency difference is output. VCO11 is controlled by this comparison output, and finally the frequency of VCO11 becomes 160f _H +4△f,
At the output of the switching circuit 13, a signal having the same fluctuation as the time axis fluctuation of the input color signal, 40f _H +Δf, is obtained. At this time, the carrier frequency of the output of the first BPF 5 becomes exactly the same frequency as the output of the oscillator 8, and a safe color signal with time axis fluctuations removed can be reproduced.

Here, the frequency discriminator is not working, but
It will operate until the frequency of the VCO 11 reaches around _160fH . In other words, this VCO11
If the control sensitivity is not sufficiently high and the frequency variable range is not wide, it will not be able to sufficiently absorb time axis fluctuations, resulting in color unevenness. Usually, the frequency variable width is set to 5% or more. On the other hand, as is well known, burst signals are inserted for a period of approximately 3 μs every 1H.
It has a spectrum for each f _H centered on f _SC . Therefore, the system shown in Figure 1 has a stable point for each _fH . Here, if VCO11 is (160f _H −4f _H )
If it oscillates at a frequency (a little more than 2% lower frequency),
The carrier frequency at the output of the first BPF5 is (f _SC −
f _H ) −△f, of which −△f is absorbed,
Eventually, the system will become stable at a frequency of (f _SC −f _H ). In this way, if the frequency of the VCO 11 is not within (160f _H ±2f _H ), a color signal with an incorrect frequency will be reproduced.

Therefore, it is necessary to constantly measure the frequency of the VCO 11 with the frequency discriminator 9, and to always control the VCO 11 within a range that allows the phase comparator circuit 7 to adjust the frequency to the correct frequency.

This frequency discriminator is usually constructed from a digital circuit, and is specifically implemented in the form shown in FIG. 2, for example. 17 is the fourth input terminal for inputting the output of the VCO 11, 18 is the fifth input terminal for inputting the horizontal synchronizing pulse, 19 to 23 are AND gates, 2
4 is a counting circuit, 25, 26, 27 are T-FF, 2
8 and 29 are constant current source circuits. 25-27 T
-FF divides the horizontal sync pulse by 1/8. T-F.
When the output of F.27 is high, that is, in the period from FIG.
It operates to input the output of 1 to the counting circuit 24. The counting circuit 24 is reset by the output of the AND gate 23 during the 1H period (the period shown in FIG. 3) immediately before the output of the T-FF 27 becomes high. The counting circuit 24 operates to count the output of the VCO 11 during the 4H period. If the count value of the counting circuit 24 is 160×4+4 or more (i.e., the frequency of the VCO 11 is 161f _H or more), the output input to the AND gate 20 becomes high, and it is less than 160×4−4 (i.e., If the frequency of the VCO 11 is _159fH or lower), the output input to the AND gate 21 becomes high. As is clear from FIG. 3, this state lasts until xii when the next reset occurs (i.e.,
,,xi period).

The other input of each of AND gates 20 and 21 is controlled by AND gate 22 and remains high for 1H period of this output state. Therefore,
During this period, if the frequency of the VCO 11 is 161f _H or higher, and the output of the AND gate 20 is 159f _H or lower, the output of the AND gate 21 becomes high.

Constant current source 28 outputs VCO1 only when the input is high.
The constant current source 29 is configured to output a current with a polarity that changes the voltage in a direction in which the frequency of 1 is lowered, and the constant current source 29 outputs a current with the opposite polarity only when the input is high.

As above, every 8H, 1H period,
When the frequency of VCO11 is higher than the predetermined frequency,
Or output is output to change the frequency of VCO 11 when the frequency is low.

When the frequency of VCO 11 is between 159f _H and 161f _H , the phase comparator circuit 7 operates to control VCO 11 to the correct frequency, so the frequency discriminator does not need to output an output. be.

Since this frequency discriminator 9 is composed of a digital circuit as described above, it is essentially capable of extremely accurate frequency discrimination, but in reality it has two drawbacks as explained below. Performance improvements are strongly desired.

The first is that it is a contributing factor to so-called color flicker, in which the hue sometimes changes significantly at the top of the screen, and the second is that it is a contributing factor to increasing the hue change at the time of dropout.

These two causes are the same; if the period of the horizontal synchronizing signal input to the frequency discrimination circuit is disturbed, the counting time of the counting circuit 24 changes, causing the constant current source to operate incorrectly. arise.

Home VTRs use two heads, and the head is switched for each field. Therefore, the signal becomes discontinuous at the switching section of the head. In this part, the period of the horizontal sync pulse is correct.
It does not become 1H, but changes by about ±0.2H at maximum. For this reason, if this discontinuous portion falls within the section shown in FIG. 3, the period during which the AND gate 19 is open will not be correctly 4H. Therefore, even if the frequency of VCO11 is correctly set to _160fH , the counting period is 4H.
Therefore, the number of counting pulses differs from 160×4 by the error of the period. For example, if the period of the horizontal sync pulse becomes 1.2H at the discontinuity,
The counting period will be 4.2H. Therefore, the number of counting pulses is 160×4.2=672, which is 32 more. Therefore, it is determined that the frequency is too high, and the constant current source 28 is operated to lower the frequency of the VCO 11.

This discontinuity occurs about 6H before the vertical synchronization pulse, so if it takes time to absorb the frequency disturbance caused by this, it will affect the upper part of the screen.

At the time of dropout, a false horizontal synchronizing pulse is generated due to noise, which also causes the counting period to not reach 4H, which also causes frequency disturbance.

The purpose of the present invention is to avoid color flickering,
Another object of the present invention is to provide a frequency discrimination device that reduces hue disturbance during dropout.

In other words, the malfunction of the frequency discriminator caused by discontinuous dropout of the signal associated with head switching occurs only once, and the output of the frequency discriminator due to the frequency shift of the VCO is continuous over a certain period of time. The constant current source is operated only when the output from the counting circuit occurs two or more times in a row, thereby preventing the frequency discriminator from malfunctioning due to signal discontinuity or dropout. It is intended to prevent

An embodiment of the present invention will be described below with reference to FIG. In Figure 4, 31 is an OR gate, 32 is an OR gate, and 32 is an OR gate.
NAND gates, 33, 38, 43 are AND gates, 35, 36, 37, 39, 40, 41, 42
is an inverter, 34 is D-FF, 44 is RSF.F.
It is. In Figure 4, VCO11 is correct.
When oscillating at 160f _H , the output on the side input to the AND gate 21 is high after the counting circuit is reset until it counts 637 input pulses, and then counts 4 pulses until exactly 637 input pulses are counted. Counting stops when 640 pieces are counted. Therefore, the output of the OR gate 31 is as shown in FIG. 5i. When the outputs of the OR gate 31 and the AND gate 22 are NANDed, they remain in a low state as shown in FIG. 5j. Therefore, since the output of D-FF also remains low, the AND gate output also remains low. Therefore, the Q output of RSF.F. also remains low, and the output of AND gate 33 also becomes low.

Next, let's consider a case where the period since is no longer 4H and the count value has become 636 or less. When the counting operation of the closed counting circuit 24 of the AND gate 19 is completed, the output of the side input to the AND gate 21 remains high, so the output of the OR gate 31 is the fifth
The high state continues from the section as shown in Figure i′. Therefore, the output of the NAND gate 32 is
It becomes low as shown at j' only during the period when the output of is high. After this pulse is delayed by 1H by D-FF, it passes through a circuit (consisting of inverters 35, 36, 37 and an AND gate) that differentiates the rising part of the pulse, so it is input to the set input of RSF.F. as shown in k'. like
A pulse is input between xi and xii. Therefore,
After xii, the RSF.F. output becomes high. However, AND
Since the output of the gate 22 becomes high only during the period, the output of the AND gate 33 continues to be low, so the AND gate 21 never becomes high. Similarly, the interval from
Consider the case where the count is longer than 4H and counting stops at 644 or more. At this time, the output of OR gate 31 is shown in Figure 5.
i″. Therefore, NAND gate 3
The output of 2 will be j″, which is also RSF.F.34
A pulse of k′ appears at the input of , and from xii onwards RSF.
The output of F.34 goes high like e'. However, even at this time, the output of the AND gate 22 becomes high only when , so the output of the AND gate 33 remains low.

In this way, up until now, the counting time has been normal.
The frequency of VCO11 is also set correctly to 160f _H ,
If the count suddenly changes and goes out of the predetermined range, the constant current source that controls the VCO 11 will not operate at all. Next, consider a case where the count value was 636 or less or 644 or more in the previous state, and the count value continues to be 636 or 644 or more.

At this time, during the period in which AND gate 22 becomes high, RSF.F. is in a high state, so AND
The output of the gate 33 becomes high as shown in section m. Therefore, this interval counting circuit 2
The constant current source is operated when the output of No. 4 is high. After this, a circuit that differentiates the fall of the output of 22 (inverters 39, 40, 41, 42
and AND gate 43), a reset pulse is input to the reset input of RSF.F. and xi as shown in h. At this point, RSF.F. becomes low once, but
Since another set pulse is input from the AND gate 38 between xi and xii, the output of the RSF.F. It will be in a state where it will be made to do.

In this way, if the frequency is outside the predetermined range and the count value of the counting circuit 24 is outside the predetermined range, the constant current source will be operated every time from the second time onwards.

As explained above, the constant current source does not operate when the count value of the counting circuit 24 exceeds the predetermined value just once, so this frequency discriminator does not malfunction due to signal discontinuity or dropout. .

For the purpose of explanation, this frequency discriminator was explained as being used in a VHS VTR that handles NTSC television signals, but by simply changing the value of the counting circuit as appropriate,
It is obvious that it can be used to handle TV signals of other formats and also for VTRs of other recording formats.
It is also clear that the present invention can be similarly used to control VCOs, motors, etc. so that they have a predetermined relationship with the horizontal synchronizing pulse, regardless of the color signal processing circuit. It goes without saying that it can also be used for video signal reproducing devices other than VTRs, such as video discs.

As explained above, according to the present invention, it is possible to prevent the frequency discrimination operation from malfunctioning due to an error in the counting period setting due to signal discontinuity, dropout, etc., and thus it is possible to reduce hue disturbance when color flicker or dropout occurs. , performance can be significantly improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a color signal processing circuit of a home VTR, Fig. 2 is a block diagram showing a conventional example of the frequency discriminator shown in Fig. 1, and Fig. 3 is a timing chart of each part of Fig. 2. 4 is a block diagram showing an example of a frequency discriminator according to the present invention, and FIG. 5 is a timing chart of each part of FIG. 4. 24... Counting circuit, 28, 29... Current source, 25,
26, 27...T-FF, 34...D-FF, 44...
RSF.F.

Claims (1)

[Claims] 1 Oscillation from a frequency dividing circuit that divides the horizontal synchronizing signal separated from the video signal and a variable oscillator that occurs during the nH (n is a positive integer, H is the horizontal period) period during the output pulse period of the frequency dividing circuit. A counting circuit that counts pulses, a discrimination circuit that discriminates whether or not the count value of the counting operation of the counting circuit is outside a predetermined range, and generates a discrimination signal if the count value is outside the predetermined range; and a control circuit that controls the oscillation frequency of the variable oscillator until the counting circuit starts the next counting operation when a number of consecutive occurrences (a is an integer of 2 or more) occurs. Device.