JPH04301920A - Semiconductor integrated circuit devie - Google Patents

Abstract

PURPOSE:To improve speed and to reduce noise for reading an interface between logic circuit blocks, signal bus in the logic circuit block and register file. CONSTITUTION:Since the output part of a signal is composed of an NMOS transistor and the input part is composed of a bipolar transistor connecting the base to a fixed potential and the emitter to a constant current source, the signal amplitude of a signal line is reduced at the degree of 100mV. Since the signal amplitude is reduced, the amount of electric charges required for inverting signals is reduced and since a peak current is made small, considerable effect for improving the speed and reducing the noise is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device configured by integrating a plurality of MOS field effect transistors and a plurality of bipolar transistors, and particularly to a hardware configuration for speeding up a signal interface.

0002

2. Description of the Related Art In a semiconductor integrated circuit device configured by integrating a plurality of MOS field effect transistors and a plurality of bipolar transistors, a hardware structure for increasing the speed of a signal interface is disclosed, for example, in Japanese Patent Laid-Open No. 59 No. 28726 discloses a BiCMOS tri-state buffer circuit. The concept of increasing the speed of this circuit is to increase the load driving power by amplifying the current of the CMOS circuit with a bipolar circuit, thereby driving the load at high speed.

[0003] In addition, an example of using a current drive type circuit in a wiring driver and receiver for connecting LSI blocks is described in Japanese Patent Laid-Open No. 61-20346.

0004

However, like the CMOS circuit, the above-mentioned prior art has a signal amplitude approximately equal to the voltage difference between the power supply voltage and the ground potential. Since the signal amplitude is large, the amount of charging and discharging necessary to invert the signal is large, and there is a limit to speeding up the process. Furthermore, since the signal amplitude is large, the current flowing within a unit time is also large, and therefore the generated noise becomes large. The problems of the prior art will be explained in detail with reference to FIG. FIG. 19 shows an example of a tristate output buffer circuit (a) and an input circuit (b) used for an interface between logic blocks. Figure 19
In (a), 201 is an input terminal, and 202 is an enable terminal. When 202 is "H", the output becomes high impedance, and when it is "L", an inverted signal of 201 is output. The basic idea of this output circuit is to configure logic using MOS transistors, amplify current using bipolar transistors, and drive heavy loads due to wiring and fan-out at high speed. Therefore, the signal amplitude of this output circuit is approximately equal to that of a CMOS circuit, and approximately equal to the potential difference between power supply potential 1 and ground potential 2. More precisely, the signal amplitude V of this circuit is determined by the power supply potential being VDD, the ground potential being GND,
If the base-emitter potential of bipolar transistors 203 and 204 is Vbe, then V=VDD-GND-
It becomes 2Vbe. As a specific example, VDD=5V
, GND=0V, Vbe=0.7V, and at this time, the signal amplitude is V=3.6V. In this way, the signal amplitude is 3
．． The high voltage of 6V causes the above-mentioned problem.

FIG. 20 shows an example of a conventional input/output circuit. B
An iCMOS output circuit 211, a CMOS output circuit 212, and a BiCMOS input circuit 213 are connected to a bus wiring 214. First, when the input terminal 202 is "L" and the input terminal 215 is "L", the BiCMOS output circuit 211 is selected and the output of the CMOS output circuit 212 is in high impedance. At this time, the bus wiring is input terminal 20.
According to the state of 1, it becomes 0V or 3.6V. Also,
When the input terminal 202 is "H" and the input terminal 215 is "H", the CMOS output circuit 212 is selected and the output of the BiCMOS output circuit 211 is in high impedance. At this time, the bus wiring is set to 0 according to the state of the input terminal 216.
V or 5V. As described above, according to the conventional circuit system, the signal amplitude of the bus wiring becomes as large as 5V or 3.6V.

An object of the present invention is to provide a semiconductor integrated circuit device that operates at high speed and has low noise.

[0007]

[Means for Solving the Problems] The above object can be achieved by sufficiently reducing the signal amplitude of the bus wiring. The present invention is characterized in that logic circuit blocks composed of at least MOS field effect transistors are connected by a current drive path. Here, the current drive path refers to a path through which I/O signals are transmitted by controlling the flow of current.

To describe the features of the present invention in more detail, the input section of the logic circuit block connected to the bus has a bipolar transistor whose emitter is connected to a constant current source, and the output section has a switching element that controls the current. The signal is transmitted by controlling the current flowing from the emitter of the bipolar transistor via the bus by the switching element.

FIG. 2 shows means for implementing the small amplitude signal interface of the present invention. 200 and 201 are the input section and output section of the logic circuit block. These are mutually connected to signal line 2.
07, from the output section 201 to the input section 200.
Send data to. The input section 200 includes a bipolar transistor 202, an impedance element 203, and a constant current source 20.
It consists of 4. The base of the bipolar transistor 202 is connected to a fixed potential VB, and the collector is connected to a power supply VCC, which is a first potential part, through an impedance element 203.
connected to. The emitter is connected to a constant current source 204 and to a small amplitude signal source 207 . Note that the constant current source 204 may be an impedance element. Further, the output section 201 is composed of a switching element 205 and an element 206 that controls the switching element 205.

0010

[Operation] It will be explained below that this circuit configuration enables a small amplitude signal interface. First, a current I1 always flows through the constant current source 204 of the input section 200. Therefore, when the switch 205 of the output section 201 is off, current cannot flow through the signal line 207.
A current I1 flows through the emitter of the bipolar transistor 202 of the input section 200. The base-emitter forward voltage of the bipolar transistor 202 at this time is VB
Assuming E1, VBE1 can be expressed by the following formula using I1.

VBE1=(KT/q)ln(I1/Is) where q
: electron charge, K: Boltzmann constant, T: absolute temperature,
Is: saturation current. Next, when the switch 205 of the output section 201 is on, a current of I2 flows through the signal line 207. When I2 is set to be sufficiently larger than I1, approximately a current of I2 flows through the emitter of the bipolar transistor 202 of the input section 200. If the base-emitter forward voltage of the bipolar transistor 202 at this time is VBE2, then VBE2 is I
2 can be expressed as the following equation.

VBE2=(KT/q)ln(I2/Is) input section 20
Since the base of the zero bipolar transistor 202 is at a fixed potential VB, the signal amplitude ΔV of the signal line 207 can be expressed by the following equation.

ΔV=(VB-VBE1)-(VB-VBE2)=VB
E1-VBE2 = (KT/q)ln(I2/Is) - (KT/q)ln(I1/Is) = (KT/q)ln(I2/I1) As an example, I2=0.5mA, I1= When set to 20 μA, KT/q at room temperature is 26 mV, so the amplitude of the signal line 207 becomes ΔV=84 mV. As described above, this circuit configuration enables an interface with a signal amplitude several tenths of that of the conventional technology. Furthermore, as is clear from the above equation, the amplitude ΔV of the signal line 207 is determined by the ratio of the current I1 flowing through the constant current source at the input section and the current I2 flowing through the switch at the output section.

Generally, if the output current of a circuit is I, the output load capacitance is C, and the signal amplitude is V, the delay time T of the circuit is:
It can be approximately expressed as T=CV/I. As is clear from this equation, the delay time T of the circuit decreases in proportion to the signal amplitude V. What is important here is that if the signal amplitude V is a sufficiently small value, high-speed signal propagation is possible even if the output current I of the circuit is set to a small value. This means that a high-speed signal interface is possible with a small circuit.

Further, if the inductance of the signal line is L and the output current of the circuit is I, then the noise Vn is Vn=LdI
/dt, and is proportional to the amount of current flowing per unit time. If the signal amplitude is made sufficiently small, the output current I of the circuit can be made small, so that the noise generated in the circuit can be made small.

[0016]

EXAMPLES Next, examples of the present invention will be described in detail below. FIG. 1 shows a semiconductor integrated circuit device which is an embodiment of the present invention. 101 is a plurality of logic circuit blocks 102, 103,
104 and 105 are built in, and these logic circuit blocks are interconnected by an internal bus 106. Further, 107 is a control logic circuit block, which controls the logic circuit blocks 102 to 105. Here, 102a, 103a, 104a, 10 of each logic circuit block
5a is a signal output section, 102b, 103b, 10
4b and 105b are signal input sections. Output sections 102a to 105a of each logic circuit block are composed only of MOS transistors, and input sections 102b to 105b are composed mainly of bipolar transistors. As mentioned above, in the conventional technology, the basic idea was to amplify the current in the input section composed of MOS transistors using a bipolar transistor in the output section, whereas the present invention The usage is completely reversed; a MOS transistor is used for the output section, and a bipolar transistor is used for the input section. FIG. 3 shows FIG. 1 in more detail. Like symbols correspond to like parts. Here, 10
A detailed circuit diagram of the symbols shown in 2b to 105b is shown in FIG. In one embodiment according to FIG. 3, 102a-10
A signal is output from the NMOS transistor shown in 5a, and 1
Signals are input using circuits made of bipolar transistors shown in 02b to 105b to perform interblock interface. The operating principle of the embodiment of the present invention will be explained using FIG. First, the configuration of the circuit will be explained in detail. FIG. 5 is an explanatory diagram when a signal is sent from the logic circuit block 102 to the logic circuit block 103 in FIG. 3, and the same symbols as in FIG. 3 indicate the same parts. The output circuit of the logic circuit block 102 is composed of NMOSs 503 and 504. The gate of the NMOS 503 is controlled by another logic circuit block 107, and the drain serves as an output terminal and is connected to the bus wiring 106.

NMOS 503 is connected in series with NMOS 504, and the source of NMOS 104 is connected to ground potential terminal 2, which is a second potential section. The gate of the NMOS 504 is connected to the internal logic circuit block 501 included in the logic circuit block 102, and is connected to the external logic circuit block 103.
receives the output signal to be sent to. On the other hand, in the logic circuit block 103, the bipolar transistor 505 senses the small signal on the bus 106 and sends the signal to the internal logic circuit block 502. The emitter of the bipolar transistor 505 becomes the input terminal and connects to bus 1.
06, the base is connected to the fixed potential terminal 506, the emitter and the resistor 507 are connected in series to the ground potential terminal 2, and the collector and the resistor 508 are connected in series to the power supply potential terminal 1 which is the first potential part. be done. The signal amplified by the bipolar transistor 505 is sent from the terminal 509 to the logic circuit block 103 by the emitter follower 510.
is sent to an internal logic circuit block 502 included in the . Next, the operation of the circuit will be explained. First, when the control signal from the logic circuit block 107 is "L", that is, when the signal line 512 is "L", the NMOS 503 is turned off and the output terminal becomes a high impedance state. Next, when the control signal from the logic circuit block 107 is "H", that is, when the signal line 512 is "H", the NMOS 503
is turned on, and the output circuit 504 of the logic circuit block becomes ready for transmission. When the signal 513 from the internal logic circuit block 501 is “H”, the current I flows through the NMOS 504.
2 flows. On the other hand, since the direct current I1 always flows through the emitter of the bipolar transistor 505 in the input circuit of the logic circuit block 103, the emitter current of the bipolar transistor 505 is the sum of I1 and I2. When the base current of 505 at this time is Ib, the collector current Ic of 505 becomes Ic=I1+I2-Ib. Since I1 and Ib are usually set to values sufficiently smaller than I2, they can be approximated as Ic=I2. Therefore, the voltage VIL of the collector 509 of the bipolar transistor 505 is as follows, assuming that the power supply potential of 1 is VDD and the resistor 508 is R1.
VIL=VDD-I2・R1, and if the voltage between the base and emitter of the bipolar transistor 510 is Vbe, the voltage at the output terminal 511 of the input circuit is VOL=VD.
D-I2・R1-Vbe. Conversely, when the signal 513 from the internal logic circuit block 501 is “L”, the NMOS5
04 is off and no current flows, and a direct current I1 flows through the emitter of the bipolar transistor 505 in the input circuit of the logic circuit block 103, but since I1 is sufficiently small compared to I2, the bipolar transistor 505 is approximately It can be considered as an off state. Therefore, the voltage VOH of the output terminal 511 at this time is VOH=VDD-Vbe. Further, the bus signal amplitude Vbus, which is the most important value in the present invention, is expressed as follows using current I1 and current I2.

Vbus=(kT/q)ln(I2/I1) where q
: charge amount of electron, k: Boltzmann constant, T: temperature. Specific numerical examples are shown below. I1=20μA, I2=
0.5mA, R1=3.3k ohm, VDD=3.3V
By substituting the values of VOL=0.
85V, VOH=2.5V, Vbus=84mV. It will be verified below whether this numerical example solves the problems of the prior art described above. The problem with the conventional technology is that
The problem was that the signal amplitude was large and there was a limit to speeding up the process. In the prior art, the signal amplitude is 3.6V, whereas in the present invention, it is 84mV, which is about 1/40 of the amplitude. Obviously, the amount of charge required to invert the signal is small and the propagation of the signal is significantly faster according to equation (1) above. Furthermore, since the amplitude is small, the instantaneous output current of the output circuit can be made small, so the generated noise can be made small.

Next, FIG. 6 shows an example in which the present invention is applied to an internal bus of a logic circuit block 610 whose scale corresponds to one logic circuit block 102 to 105 in FIG. First, the overall configuration will be explained. 601 and 602 are low amplitude buses of the present invention, 601 is a source bus that reads data from a register file and takes the data into each logic circuit block, and 602 is a target bus that writes output results from each logic circuit block to the register file. It is. Note that in this embodiment, the source bus 601 has two ports, and the target bus 602 has one port. 603, 604, and 605 are internal logic circuit blocks, each corresponding to a multiplier, a divider, and an adder, for example. 606 is a register file and 609a to 6
09z is a memory cell of RAM or ROM. Each of the memory cells consists of at least a MOS field effect transistor. This register file has a 3-port configuration with 1 write and 2 read ports. Note that in this embodiment, an example of a 3-port configuration was given for ease of explanation; however,
Other bus/register file configurations, such as a 7-port configuration with 4 reads and 3 writes, are also possible. 603a-60
6a and 603b to 606b are input sections shown in FIG. 4, and 603c to 606c and 603d to 605d are output sections. 607 is 603d-605d and 603c-6
6 is an internal control logic circuit block that controls 05c.
08 is an internal control logic circuit block that controls the register file. The operating principle is the same as the above embodiment,
Also in this embodiment, since the signal output section is configured with NMOS transistors and the signal input section is configured with bipolar transistors, the signal amplitudes of bus 601 and bus 602 are approximately 100 mV, which is a very small value. This provides high speed and low noise bus performance. Yet another advantage of embodiments of the present invention is that 603d-605d facilitate bypassing to bus 601. Bypass means that each internal logic circuit block 603, 6
04 and 605 are sent directly to the source bus 601 without being written to the register file. Bypass is used when it is desired to immediately use the operation results of each internal logic circuit block 603, 604, and 605 in the next operation. At the time of bypass, a control signal is raised from the control logic circuit block 607, one of the bypass circuits 603d to 604d is selected, and the calculation result of the selected internal logic circuit block is bypassed to the bus 601. As described above, in the embodiment of the present invention, a bypass circuit can be constructed extremely easily by using two NMOS transistors connected in series, and therefore, compared to the prior art, there are the following advantages.

First, since the signal amplitude is extremely low, high speed and low noise are achieved.

Second, since the circuit configuration includes only two NMOS transistors, the output circuit itself can switch at high speed.

Thirdly, in the present invention, the signal amplitude is small, and therefore the output current of the output circuit can be small, so there is no need to increase the size of the transistor, and the output capacitance of the output circuit is small. Normally, there is a large amount of data that needs to be bypassed, so the output circuit for bypass is connected to the bus 601.
The capacity of the bus 601 largely depends on the output capacity of the bypass output circuit. That is, the present invention, which allows the output capacitance of the bypass output circuit to be reduced, allows the capacitance of the bus to be reduced, and as a result, the bus can be driven at high speed.

As described above, FIG. 3 shows an embodiment in which the present invention is applied to an interface between logic circuit blocks, and FIG. 6 shows an embodiment in which the present invention is applied to an internal bus of a logic circuit block. Further, FIG. 9 shows an example in which the present invention is applied to an actual microprocessor.

In the figure, 900 is a one-chip microprocessor, which includes a program counter 901, an instruction cache 902, a data cache 903, and an integer arithmetic unit 9.
04, a real number arithmetic unit 905 and other control logic circuits. A program counter 901, an instruction cache 902, and an integer arithmetic unit 904 are connected by a data bus 906, and a data cache 903 and an integer arithmetic unit 904 are connected to each other by a data bus 906.
are connected by a data bus 908. The data bus 906 is for the program counter 901 or the integer arithmetic unit 904 to specify the address of the instruction cache 902, and the data bus 907 is for sending data from the data cache 903 to the integer arithmetic unit 904 and the real number arithmetic unit 905. A data bus 908 is used by the integer arithmetic unit 904 to specify the address of the data cache 903. These data buses 906, 907, and 908 all have in common that they have a heavy load capacity and that they are critical paths that affect the performance of the processor. Therefore,
It is extremely effective to apply the present invention to these data buses. By connecting the input/output circuit of the present invention to data buses 906, 907, and 908 as shown in FIG. 9, a small amplitude signal bus interface is possible and high speed is achieved. Although the embodiment of a one-chip microprocessor has been described above, the present invention is also applicable to, for example, an interface between multiple chips on a multi-chip module or an interface between blocks on a wafer scale integration.

FIG. 7 shows another embodiment of the present invention. This embodiment is an example in which the present invention is applied particularly to a register file and a bypass circuit. 708,709,710,714
are each one logic circuit block. this house,
709 and 710 are control logic circuit blocks;
is a memory in which data and instructions to be processed are stored. 714 is an arithmetic logic circuit block of interest. 703, 704, 705, and 706 are internal logic circuit blocks included in 714, and 707 is a register file. 711a to 711z are RAM or ROM memory cells. 712 is a source bus that reads the contents of the register file and takes in data to each logic circuit block, and 713 is a source bus that reads the contents of the register file and takes in data to each logic circuit block.
This is the target bus that writes the output results of . In this embodiment, buses 712 and 714 have logic circuit amplitudes equal to those of normal CMOS or BiCMOS circuits. The low amplitude bus of the present invention is 701
, 702.

703a to 707a are output sections of the present invention, and 701a and 702a are input sections of the present invention shown in FIG. The operation and features will be described below. 703-70
The calculation result of the internal logic circuit block 6 is normally transferred to the bus 7.
13 to the register file, but if this calculation result is to be used immediately in the next step calculation, the calculation result is sent directly from the low amplitude bypass bus 701 to the source bus 712. Also, when data from memory 708 is directly loaded onto source bus 712, the data is sent directly from low amplitude bypass bus 701 to source bus 712. Furthermore, when reading the contents of the register file to the source bus 712, the low amplitude bus 702 is used.
The register file will be explained in detail in the next embodiment. When the operation results of the logic circuit blocks 703 to 706 are to be bypassed to the source bus, a control signal is sent from the control logic circuit block 709 indicating which operation result or data among the logic circuit blocks 703 to 706 and 708 is to be bypassed. According to this control signal, 703a to 706a, 7
08a is selected, and the selected calculation result or data is read out to the low amplitude bus 701. The read operation result is sensed by the input circuit 701a and input to the buffer circuit 715 with selector. On the other hand, one register file data is selected according to the control signal of the control logic circuit block 710, and 711a to 711
z, selected data is read out to the low amplitude bus 702. The read data is sensed by an input circuit 702a and input to a buffer circuit 715 with a selector. A buffer circuit with a selector 715 selects either the signal from the bypass or the data from the register file and outputs it to the source bus 712. The most significant effects of the embodiments of the present invention are the speedup and area reduction of the bypass. When the bypass configuration of this embodiment is realized using the conventional technology shown in FIG. 19(a), the source bus 712
Six driver circuits are connected to. Therefore, the load capacity of the source bus 712 becomes heavy, making it impossible to drive the bus at high speed. Furthermore, since the area occupied by the six driver circuits is large, the overall area becomes large. On the other hand, according to the embodiment of the present invention, only one driver circuit is connected to the source bus 712, and the load capacity of the source bus 712 can be reduced, and the area occupied by the driver circuit is small.
The overall area can be reduced. Note that in this embodiment, a 1-bit circuit configuration is shown for the sake of simplicity, but in reality it is composed of a plurality of bits. For example, in the case of a 64-bit configuration, the grid configuration shown in FIG. Connected.

FIG. 15 shows a modification of the embodiment shown in FIG. Figure 7
1, the signal from the memory 708 is output to the source bus 712 via the sense circuit 701a, whereas in FIG.
In the fifth embodiment, the signal from the memory 708 and the output signal of the sense circuit 701a are selected by the selector 151 and output from the tristate buffer 153 to the source bus 712. Accordingly, the buffer that outputs the data of the register file 707 to the source bus 712 is designated as the tri-state buffer 152. The features of the configuration according to FIG. 15 are as follows.
Since data from the memory is outputted to the source bus 712 without going through the sense circuit 701a, it is particularly possible to import data from the memory to each logic circuit block at high speed.

FIG. 16 shows another modification of the embodiment shown in FIG. In this embodiment, a memory 708, a logic circuit block 704
, 705, 706 are selected by the selector 161, and the output signals from the tri-state buffer 162 are output from the source bus 712.
Output to. Along with this, register file 707
The buffer that outputs the data to the source bus 712 is referred to as a tri-state buffer 163. The feature of the configuration according to FIG. 16 is that the data from the memory and the logic circuit block 70
Since the output results of 4,705,706 are outputted to the source bus 712 without going through the sense circuit 701a, it is possible to particularly high-speed data import from the memory and logic circuit blocks 704, 705, 706 to each logic circuit block. is now possible.

FIG. 17 shows another modification of the embodiment shown in FIG. In this embodiment, logic circuit blocks 704, 705, 70
The output signals of 6 are directly returned to the respective logic circuit blocks without being output to the source bus 712, and are sent to the selectors 171 and 1.
After selecting the data on the source bus and the output results of each logic circuit block at 72 and 173, necessary data is taken into each logic circuit block. A feature of the configuration shown in FIG. 17 is that the output signals of the logic circuit blocks 704, 705, 706 do not pass through the sense circuit 701a and are not placed on the source bus with heavy load capacity. The point is that the output data of 706 can be taken into each logic circuit block at high speed.

FIG. 18 is a modification of the embodiment shown in FIG. 17. In this embodiment, logic circuit blocks 704, 705, 706
The output signal of
2,173 selects the data on the source bus and the output results of each logic circuit block, and also selects the data in the memory 708
The output result of the logic circuit block 703 and the data from the register file are selected by the selector 181 and output from the buffer 715 to the source bus. A feature of the configuration shown in FIG. 18, in addition to the features shown in FIG. 17, is that data can be taken in from the memory 708 and the logic circuit block 703 to each logic circuit block at high speed.

FIG. 8 shows an embodiment in which the present invention is applied to a register file. This embodiment is a register file with a 2-read/2-write configuration, and although any bit/word configuration is possible, it is particularly effective in speeding up reading of a register file with a multi-word configuration. Further, as a matter of course, other configurations are possible for the number of read/write ports. 810 is a writable memory cell; 81 is a writable memory cell;
1a and 811b. Further, a part of the memory cell may be a non-writable ROM. memory cell 8
10 are controlled by address signals W1n, W2n, R1n, and R2n. When W1n and W2n become "H", writing is possible, and when R1n and R2n become "H", reading becomes possible. The drains of NMOS 811a and 811b are connected to data lines 801a and 801b, respectively, as shown in FIG.
Source buses 805a and 805 are connected via sense circuit 802a, amplifier circuit 803a, and buffer circuit 804a shown in
Leads to b. 806 and 807 are multipliers and AL
It is a logic circuit block such as U (Arithmetic Logic Unit). Logic circuit blocks 806 and 807 are connected to target buses 808a and 808b, respectively, and write operation results to register files. With the above configuration, the feature of the embodiment of the present invention is that the signal amplitude of the data lines 801a and 801b of the register file is 10
This is as small as about 0 mV. Therefore, especially when the register file has a large number of words and the load capacitance of the data line is heavy, the present invention is effective in speeding up register file reading and reducing noise. Note that although this embodiment has shown a 1-bit circuit configuration for simplicity, it is actually composed of several bits. For example, in the case of a 64-bit configuration, the circuit configuration shown in FIG. 8 is repeated 64 times, and W1n
, W2n, R1n, and R2n are commonly connected to each bit.

FIG. 10 shows another embodiment of the register file. One data line 11 branches out and is connected to two sense circuits 12a and 12b. This embodiment makes it possible to read the contents of the same register file at two locations.

FIG. 12 shows another embodiment of the input circuit of the present invention. The basic circuit configuration and circuit operation are the same as the circuit shown in FIG. 5103, but the following five points are different. First, the difference in circuit configuration from FIG. 5 is 1.
21, and secondly, MOS transistors 122, 12 for cutting all DC current.
3, 125, 126 and a transfer gate 124; third, a MOS transistor 127 for cutting DC current only during data latching; fourth, MOS resistors 128, 129;
Fifth, it includes a constant voltage power supply diode 120a. Next, we will discuss the circuit operation and effects. Firstly 121
The latch circuit section shown in FIG. 1 outputs an inverted signal of the output signal of the sense circuit when the CK signal is "H", and holds an inverted signal of the output signal when the CK signal is "L". In addition, the circuit 121
Another function of the sensor is to shape the output signal of the sense circuit. The signal output to the output terminal OUTN of the sense circuit has a first power supply potential of VDD and a second power supply potential of VDD.
When SS is set, the high level is approximately set to VDD-0.8V, and the low level is approximately set to VSS+1.6V. The latch circuit section shapes this signal into a full amplitude signal whose high level is VDD and low level is VSS. Second, MOS transistors 122, 123, 124,
125 and 126 are elements for cutting off all direct current. When an "L" signal is input to the DC current control terminal ID, the MOS transistors 122, 123, and 125 are turned on, the MOS transistor 126 and the transfer gate 124 are turned off, and the circuit operates as the normal circuit described in FIG. perform an action. When an “H” signal is input to the DC current control terminal ID, the MOS transistors 122, 123, 12
5 turns off and cuts off the direct current. Further, the MOS transistor 126 turns on and pulls up the node OUTN to VDD, thereby holding the input signal of the latch circuit 121 at "H". This is to prevent a through current from flowing through the latch circuit due to the signal level of the node OUTN becoming unstable. Further, the transfer gate 124 is turned on, shorting the base and emitter of the bipolar transistor 120b, turning off the bipolar transistor 120b, and cutting off the DC current path. Such a function of cutting off direct current is mainly used for evaluating device characteristics of LSI. Thirdly, the NMOS 127 is an element for cutting off part of the DC current while data is latched, thereby reducing the power consumption of the circuit. First, the DC current control terminal I
"L" is input to D, NMOS 125 is on, and the circuit is in operation. Here, clock signal CK
When is “H”, the circuit of the present invention propagates data at high speed,
When the clock signal CK is "L", data is latched. Therefore, when the clock signal CK is "H", the circuit needs to operate at high speed, but when the clock signal CK is "L", the circuit does not need to operate at high speed. Using this latch period, it is possible to reduce the DC current only while the clock signal CK is "L". The gate of NMOS 127 is controlled by clock signal CK. clock signal C
When K is "H", the NMOS 127 is turned on and the emitter follower current of the bipolar transistor 120c flows, and the circuit normally operates at high speed. Clock signal CK is “L”
”, the NMOS 127 is turned off and the emitter follower current of the bipolar transistor 120c is reduced. Such control can reduce the power consumption of the circuit. Fourth, by using the MOS resistors 128 and 129, the resistor The element can be made smaller.Fifth, the low voltage diode 120a allows the base voltage of the saturation prevention clamp transistor 120b to be set to a lower voltage than in the circuit shown in FIG. , the low level of node OUTN decreases, so that the signal amplitude of OUTN can be increased after all.

FIG. 13 shows another embodiment of the input circuit of the present invention. The difference from FIG. 12 is that the transfer gate 130
This is the addition of . While the clock signal CK is at "H", the transfer gate 130 is on and the circuit operates normally. Since data is latched while the clock signal CK is "L", there is no need to input data. Therefore, the transfer gate 130 can be turned off and the DC current path can be cut off. Due to this,
Further reduction in power consumption becomes possible. The embodiments shown in FIGS. 12 and 13 can be applied to all applications in which the circuit shown in FIG. 4 is used.

FIGS. 14 and 140 show other embodiments of the input circuit of the present invention. In the circuit of the present invention, the PNP transistor 141
, 142 is used. The output circuit connected to this circuit configuration is composed of PMOS transistors shown at 143 and 144. In the circuit embodiment using the NPN transistor described above, the rise time of the output signal is shorter than the fall time. This is due to the emitter follower using an NPN transistor, but as shown in Fig.
4 uses an emitter follower using a PNP transistor, so compared to the rise time of the output signal,
It is characterized by a short fall time.

FIG. 11 shows another embodiment of the register file. This embodiment is an example of a differential register file. The memory cell 21 outputs both positive and negative signals, and these signals are input to the gates of the NMOSs 22a and 22b. The on/off state of the NMOS 23 is controlled by the address control signal A1. The differential signals are input to a differential sense circuit 30 via data buses 24a and 24b. This output signal is transmitted to the logic circuit block 28 via the differential amplifier circuit 26, buffer circuit 27, and source bus 29.
sent to. A feature of the embodiment of the present invention is that the low amplitude data buses 24a and 24b are of a differential type. This makes it possible to obtain stronger noise resistance.

[0037]

According to the present invention, it is possible to significantly reduce the signal amplitude of a bus between logic circuit blocks, a bus within a logic circuit block, or a data line of a register file. This has a significant effect on increasing the speed and reducing noise of semiconductor integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an outline of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a conceptual diagram of an input/output circuit of the present invention. .

FIG. 3 is a diagram showing a semiconductor integrated circuit device that embodies FIG. 1;

FIG. 4 is a diagram showing a specific input circuit of the present invention.

FIG. 5 is a diagram in which the present invention is applied between logic circuit blocks.

FIG. 6 is a diagram in which the present invention is applied within a logic circuit block.

FIG. 7 is a diagram in which the present invention is applied to a register file and a bypass circuit.

FIG. 8 is a diagram in which the present invention is applied to a register file.

FIG. 9 is a diagram in which the present invention is applied to a microprocessor.

FIG. 10 is a diagram showing another example in which the present invention is applied to a register file.

FIG. 11 is a diagram showing still another example in which the present invention is applied to a register file.

FIG. 12 is a diagram showing another specific input circuit of the present invention.

FIG. 13 is a diagram showing still another specific input circuit of the present invention.

FIG. 14 is a diagram showing still another specific input circuit of the present invention.

FIG. 15 is a diagram showing another example in which the present invention is applied to a register file and a bypass circuit.

FIG. 16 is a diagram showing still another example in which the present invention is applied to a register file and a bypass circuit.

FIG. 17 is a diagram showing still another example in which the present invention is applied to a register file and a bypass circuit.

FIG. 18 is a diagram showing still another example in which the present invention is applied to a register file and a bypass circuit.

FIG. 19 is a diagram showing a conventional input circuit.

FIG. 20 is a diagram showing a conventional input/output circuit.

[Explanation of symbols]

101...present invention, semiconductor integrated circuit device, 102-105
, 107...logic block, 106...present invention, signal bus,
102a-105a...present invention, input section, 102b-10
5b...present invention, output section, 1...power terminal, 2...ground terminal,
201, 202, 205...input terminals, 203, 204...
Bipolar transistor, 206...output terminal, 301...
Bipolar transistors, 501, 502... Internal logic blocks, 503, 504... NMOS, 505, 510...
Bipolar transistor, 507, 508...Resistor, 60
1,602... Internal bus, 603-605... Internal logic block, 603a-605a, 603b-605b... Present invention, input section, 603c-606c... Present invention, output section, 6
06... Register file, 607, 608... Control logic block, 609a, 609z... Memory cell, 610... Internal logic block having internal bus of the present invention, 701, 70
2...Low amplitude signal line, 701a, 702a...present invention, input section, 703-706...internal logic block, 707...register file, 708-710...control logic block, 7
11a to 711z...Memory cell, 712, 713...Signal bus, 714...Internal logic block of the present invention, 715...Buffer circuit with selector, 801a, 801b...Low amplitude data line, 802a...Sense circuit of the present invention, 803a...Amplification circuit, 804a...buffer circuit, 805a, 805b...
Source bus, 806, 807...internal logic block, 80
8a, 808b...Target bus, 809a, 809b
...Write control transfer gate, 810...Memory cell, 811a, 811b...Invention, output section, 812a,
812b, 813a, 813b...Control line, 11...Data line, 12a, 12b...Sense circuit of the present invention, 13a, 13
b...Signal bus, 21...Memory cell, 22a, 22b, 2
3... Present invention, output section, 24a, 24b... Low amplitude data line, 25a, 25b... Bipolar transistor, 26... Amplifying circuit, 27... Buffer circuit, 28... Internal logic block, 29... Signal bus, 30... Present invention sense circuit.

Claims (24)

[Claims] 1. A semiconductor integrated circuit device having a plurality of logic circuit blocks and a bus interconnecting these logic circuit blocks, wherein at least one of the logic circuit blocks has an output section connected to the bus. , the output section is constituted by a switching element that controls a current in response to an input signal applied to at least one input terminal, and at least one other of the logic circuit blocks is connected to the bus. 1. A semiconductor integrated circuit device comprising an input section, the input section comprising a bipolar transistor whose emitter is connected to a constant current source. 2. The semiconductor integrated circuit device according to claim 1, wherein the bipolar transistor constituting the input section is:
1. A semiconductor integrated circuit device, wherein a base is set at a fixed potential, and a collector-emitter current path is connected between a first potential section and an input terminal. 3. The semiconductor integrated circuit device according to claim 2, wherein the input section further has a base connected to the collector of the bipolar transistor, and a collector-emitter current path is connected to a first potential section and a second potential section. 1. A semiconductor integrated circuit device comprising a bipolar transistor connected between. 4. The semiconductor integrated circuit device according to claim 1, wherein the switching element constituting the output section comprises a MOS field effect transistor, and the MOS field effect transistor has an input voltage applied to at least one input terminal. A semiconductor integrated circuit device forming a source-drain current path between an output terminal and a second potential portion in response to a signal. 5. The semiconductor integrated circuit device according to claim 4, wherein the MOS field effect transistor constituting the output section is a plurality of NMOS field effect transistors connected in series. Device. 6. A data processing device having a plurality of logic circuit blocks and a bus interconnecting these logic circuit blocks, wherein at least one of the logic circuit blocks has an output section connected to the bus. and the output section is constituted by a MOS field effect transistor, and at least one other of the logic circuit blocks has an input section connected to the bus, the input section having a base set at a fixed potential. , characterized in that it is composed of a bipolar transistor whose collector is connected to a first potential section via a first impedance element and whose emitter is connected to a second potential section via a second impedance element. Data processing equipment. 7. The data processing device according to claim 6,
The MOS field effect transistor constituting the output section forms a source-drain current path between the output terminal and the second potential section in response to an input signal applied to at least one input terminal. Characteristic data processing device. 8. The data processing device according to claim 7,
A data processing device characterized in that the output section includes a plurality of NMOS field effect transistors connected in series. 9. The semiconductor integrated circuit device according to claim 4, wherein the input section further has a base connected to the collector of the bipolar transistor, and a collector-emitter current path that is connected to a first potential section and a second potential section. 1. A semiconductor integrated circuit device comprising a bipolar transistor connected between. 10. A semiconductor integrated circuit device arranged on the same substrate, the semiconductor integrated circuit device comprising at least two or more logic circuit blocks each having a bus and a plurality of MOS field effect transistors, This logic circuit block has an output section or an input section connected to the bus for exchanging data between the blocks, and the output section responds to an input signal applied to at least one input terminal. 1. A semiconductor integrated circuit device, comprising switching means for controlling a current, wherein the input section includes a bipolar transistor whose emitter is connected to a constant current source. 11. The semiconductor integrated circuit device according to claim 10, wherein said switch means connects a source between an output terminal and a second potential portion in response to an input signal applied to at least one input terminal. MOS forming drain current path
A semiconductor integrated circuit comprising a field effect transistor, wherein the bipolar transistor has a base set at a fixed potential and a collector-emitter current path connected between a second potential section and an input terminal. Device. 12. A data processing device disposed on the same substrate, the data processing device comprising first and second buses, an output section connected to the first bus, and a memory including a plurality of memory cells including a MOS field effect transistor having an input section connected to a second bus; an input section connected to the first bus; and an input section connected to the second bus. an arithmetic circuit that performs predetermined arithmetic operations, and an output section of the memory and the arithmetic circuit is composed of a MOS field effect transistor, and an input section is composed of a bipolar transistor; 1. A data processing device, wherein a current drive circuit is formed between the first and second buses, respectively. 13. The data processing device according to claim 12, wherein the output section has a source/drain connection between the output terminal and the second potential section in response to an input signal applied to at least one input terminal. It has a MOS field effect transistor forming a current path, and the input part has a base set to a fixed potential, an emitter connected to a constant current source, and a collector connected to a constant current source.
A data processing device comprising a bipolar transistor whose emitter current path is connected between a first potential portion and an input terminal. 14. A data processing device disposed on the same substrate, the data processing device comprising first and second buses, an output section connected to the first bus, and the a memory including a plurality of memory cells including a MOS field effect transistor having an input section connected to a second bus; an input section connected to the first bus;
and an arithmetic circuit that performs a predetermined operation and has first and second output sections connected to a second bus, and the memory and the output section of the arithmetic circuit are MOS field effect The input section is composed of a bipolar transistor whose emitter is connected to a constant current source, and the first bus or the first and second buses are connected between the output section and the input section.
A semiconductor integrated circuit device characterized in that a current drive circuit is formed through a semiconductor integrated circuit device. 15. The data processing device according to claim 14, wherein the output section of the memory and the first and second output sections of the arithmetic circuit each receive an input signal applied to at least one input terminal. It has a MOS field effect transistor that responsively forms a source-drain current path between the output terminal and the second potential section, and the bases of the input sections of the memory and the arithmetic circuit are each set at a fixed potential. is,
A data processing device comprising a bipolar transistor whose collector-emitter current path is connected between a first potential portion and an input terminal. 16. A data processing device disposed on the same substrate, the data processing device including a plurality of buses, an output section connected to at least one of the plurality of buses, and a plurality of buses connected to the plurality of buses. a memory including a plurality of memory cells including a MOS field effect transistor having an input section connected to at least one other of the plurality of buses; and an input section and an output section connected to at least one of the plurality of buses. a plurality of arithmetic circuits that perform predetermined arithmetic operations, and the memory and the output section of the arithmetic circuit are connected between the output terminal and the ground potential section in response to an input signal applied to at least one input terminal. It has a MOS field effect transistor forming a source-drain current path between the memory and the input section of the arithmetic circuit, the base of which is set at a fixed potential, the emitter connected to a constant current source, and the collector-emitter. A data processing device characterized in that a current path includes a bipolar transistor connected between a first potential section and an input terminal. 17. A semiconductor integrated circuit device arranged on the same substrate, the semiconductor integrated circuit device comprising at least two or more logic circuit blocks each having a bus and a plurality of MOS field effect transistors, This logic circuit block has an output section connected to the bus, and the output section is constituted by first and second NMOS field effect transistors connected in series, and the first NMOS field effect transistor in response to a control signal applied to the gate of the second NMOS field effect transistor and an output signal of the logic circuit block applied to the gate of the second NMOS field effect transistor. A semiconductor integrated circuit device characterized by forming a drain current path. 18. A semiconductor memory device arranged on the same substrate, the semiconductor memory device comprising: a memory cell array consisting of a predetermined arrangement of a plurality of memory cells including MOS field effect transistors; a data line; A source-drain current path is connected to each of the plurality of memory cells, and is read from a predetermined memory cell by forming a source-drain current path between one end of the data line and a ground potential portion in response to an address signal. a bipolar transistor whose base is set at a fixed potential and whose collector-emitter current path is connected between the first potential section and the other end of the data line; 1. A semiconductor memory device comprising: a sense circuit having a sense circuit; 19. A semiconductor integrated circuit device having at least two logic circuit blocks configured by integrating a plurality of MOS field effect transistors and a plurality of bipolar transistors, wherein the output circuit of the preceding logic block is The input circuit of the next stage logic block is composed of a MOS field effect transistor, and the input circuit of the next stage logic block is composed of a bipolar transistor whose emitter is connected to a constant current source.The connection between this output circuit and the output circuit allows signals between the logic circuit blocks to be A semiconductor integrated circuit device characterized in that it transmits and receives data. 20. A semiconductor integrated circuit device having at least two logic circuit blocks configured by integrating a plurality of MOS field effect transistors and a plurality of bipolar transistors, wherein the plurality of logic circuit blocks The at least one logic circuit block includes a bipolar transistor which has two steady states with emitter currents of different magnitudes, and the signal amplitude of the signal line is equal to 1. A semiconductor integrated circuit device characterized in that the voltage is determined by the difference in base-mitter forward voltage corresponding to a steady state. 21. In a semiconductor integrated circuit device having a plurality of logic circuit blocks configured by integrating a plurality of MOS field effect transistors and a plurality of bipolar transistors, the output circuit of at least one previous logic circuit block is It has a plurality of NMOSs connected in series between the output terminal and the second potential section, the input circuit of at least one other logic circuit block has an emitter as an input terminal, and a base set at a fixed potential. It has a bipolar transistor, a first impedance element connected to the collector of the bipolar transistor, and a constant current source connected to the emitter, and the output terminal of the output circuit and the emitter of the bipolar transistor of the input circuit are connected to each other. connected to each other by data lines, the bipolar transistors have two steady states with emitter currents of different magnitudes;
A semiconductor integrated circuit device, wherein the signal amplitude of the data line is determined by a difference between base-mitter forward voltages corresponding to two steady states of the bipolar. 22. A data processing device having a plurality of internal logic circuit blocks configured by integrating a plurality of MOS field effect transistors and a plurality of bipolar transistors, at least one of the internal logic circuit blocks.
is a register file, and other internal logic circuit blocks have a first data line for reading data from the register file and a second data line for writing data to this register file.
at least one bipolar transistor is connected to each of the first and second data lines, and the bipolar transistor carries emitter currents of different magnitudes in two steady states. , wherein signal amplitudes of the first and second data lines are determined by a difference between base-mitter forward voltages corresponding to two steady states of the bipolar. 23. A data processing device having a plurality of internal logic circuit blocks configured by integrating a plurality of MOS field effect transistors and a plurality of bipolar transistors, at least one of the internal logic circuit blocks.
is a register file, and other internal logic circuit blocks have a first data line for reading data from the register file and a second data line for writing data to this register file.
, and has means for bypassing a signal from each of the internal logic circuit blocks directly to the first data line, and this bypassing means connects the output terminal and the second potential section to each other. Multiple NMOs connected in series between
an input circuit including an output circuit consisting of an S, a bipolar transistor whose base is set to a fixed potential, a first impedance element connected to the collector of the bipolar transistor, and a constant current source connected to the emitter; The output terminal of the output circuit and the input terminal of the input circuit are connected to a third
are connected to each other by data lines, the bipolar transistors of the input circuit have two steady states with emitter currents of different magnitudes, and the signal amplitude of the third data line corresponds to the two steady states of the bipolar transistor. A data processing device characterized in that the data processing device is determined by the difference in base-mitter forward voltage. 24. The data processing device according to claim 22 or 23, wherein the data processing devices are arranged on the same substrate.