JPH04299835A - Semiconductor device and manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and a manufacturing method which prevent the short circuit between a gate electrode and a source electrode. CONSTITUTION:An n<-> layer 12 is formed on a semiconductor substrate 11 having a drain electrode 41; insulating gates composed of three layers by a gate oxide film 21, a gate electrode 31 and an insulating film 22 are formed at equal intervals on the n<-> layer 12. P-type impurities, e.g. boron, are ion-implanted by making use of the insulating gates as a mask; a P-layer 13 is formed. An insulating film 24 which contains impurities is filled into a region in which both ends of the gate electrode 31 are retreated respectively to the inside from the end of the insulating film 22; it covers the whole side faces of both end parts of the insulating gates; it is used to insulate the gate electrode 31 from a source electrode 42. Impurities, e.g. phosphorus, in the insulating film 24 are diffused into the P-layer 13 from the film; an n<+> layer 15 is formed. The source electrode 42 comes into contact with the diffusion region in the transverse direction of the n<+> layer 14 and with the P-layer 13.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to semiconductor devices such as IGBTs and power MOSFETs having an insulating film on the side surface of an insulated gate, and in particular, a semiconductor element suitable for preventing short circuit between a gate electrode and a source electrode, and a method for manufacturing the same. Regarding.

0002

[Prior Art] Conventional semiconductor devices are disclosed in Japanese Patent Application Laid-open No. 63-249.
It is disclosed in Japanese Patent No. 374, and its configuration will be explained with reference to FIG. IDM, International Electron Device Meeting, (1988) No. 8
Pages 13 to 816 (IEDM, International
onal Electron Devices Mee
ting (1988) pp813-816), the development of IGBTs and power MOSFETs is based on high voltage resistance,
The trend is toward larger currents and faster speeds. When the current is increased, the chip area becomes larger, leading to higher costs. On the other hand, in order to reduce the chip area, it is necessary to improve the output current density. Furthermore, when the breakdown voltage is increased, the n-minus layer 12 becomes thicker, and the resistance becomes larger, making it impossible to increase the current. As a result, it is necessary to improve the output current density even when the breakdown voltage is increased. moreover,
In order to increase the speed, it is necessary to shorten the lifetime of the n-minus layer 12, but in the case of IGBT, the amount of holes injected decreases, the conductivity of the n-minus layer 12 becomes difficult to modulate, and the output current density decreases. do. Therefore, the IGB of this structure
The T or power MOSFET is designed to achieve a large current density by miniaturizing the MOS structure and arranging unit cells at high density. The detailed structure will be explained below.

A high-resistance n-layer 12 is provided on a low-resistance n-type or p-type semiconductor substrate 11 having a drain electrode 41, and a gate oxide film 21 is formed on the n-layer 12.
, a gate electrode 31, and an insulating film 22, insulated gates are formed at regular intervals. When the semiconductor substrate 11 is n-type, it is called a power MOSFET, and when it is p-type, it is called IGBT. Using these insulated gates as a mask, P-type impurities such as boron are ion-implanted to form a P layer 13. An insulating film 24 containing impurities is provided on all side surfaces of both ends of the insulated gate.
4, an impurity contained in the film, such as phosphorus, is diffused into the P layer 13 to form an n-plus type layer 15. The source electrode 42 is connected to the lateral diffusion region of the n-plus type layer 15 and the p-layer 1.
3 is shorted. The insulating film 24 containing impurities is used to insulate the gate electrode 31 and the source electrode 42 immediately after the n-plus type layer 15 is formed. In this way, the P layer 13, n
The contact hole for the positive layer 15 and the source electrode 42 can all be formed in self-alignment with the insulated gate. As a result, the chip area can be reduced and IGBTs and power MOSFETs with high output current density have been realized.

0004

SUMMARY OF THE INVENTION The conventional structure described above has a problem in that the insulating film provided on the side surface of the insulated gate tends to be defective in shape. An example of a case where a shape defect occurs in this insulating film will be described below with reference to FIGS. 23 and 24. An insulating film 24 containing impurities is deposited on the insulating film 22, the side surfaces of the insulated gate, and the entire exposed Si surface, and is subjected to anisotropic dry etching to leave the insulating film 24 containing impurities on the side surfaces of the insulated gate. However, in the anisotropic dry etching step, excessive etching is performed so that the insulating film 24 containing impurities does not remain on the Si surface where the n-plus type layer 15 and the P layer 13 are exposed. This is called over-etching. As a result of this over-etching, the shape of the insulating film 24 provided on the side surface becomes smaller as indicated by X and Y in FIG.
In this state, the gate electrode 31 and the source electrode 42 are short-circuited. Furthermore, when the gate electrode 31 and the source electrode are processed diagonally, the insulating film 24 containing impurities that should be formed on the side surfaces of the insulated gate is processed to cover the side surfaces of the gate electrode 31, as shown in FIG. First, the gate electrode 31 and the source electrode 42 are short-circuited.

An object of the present invention is to prevent short circuits between the gate electrode and the source electrode.

[0006]

[Means for solving the problem] The above problem is achieved by forming a gate insulating film on the surface of a semiconductor layer of one conductivity type having a drain electrode.
an insulated gate in which a gate electrode and an insulating film are sequentially laminated; a well layer of the other conductivity type that reaches below the insulated gate in the semiconductor layer and has a high impurity concentration; and an impurity of one conductivity type provided on a side surface of the insulated gate. a side insulating film including a side insulating film, formed on the insulating film, the side insulating film, and the well layer, and diffusing impurities from the side insulating film into the well layer to form a one conductivity type with a higher impurity concentration than the well layer. In a semiconductor device having a source layer, the problem is solved by filling a region where the end surface of the gate electrode is recessed from the end surface of the insulating film with the side surface insulating film.

The above problem was solved by sequentially laminating a gate insulating film, a gate electrode, and an insulating film on the surface of a semiconductor layer of one conductivity type having a drain electrode, and using a photoresist baked in the shape of the gate electrode on the insulating film as a mask. The gate electrode is processed by anisotropic dry etching to form an end face, the end face of the gate electrode is processed by isotropic dry etching to retreat from the end face of the insulating film, and impurities are removed using the gate electrode as a mask. implant to form a well diffusion layer,
processing by anisotropic dry etching so as to leave a gate insulating film directly under the insulating film, forming an insulating film containing impurities on the entire surface and filling the region where the gate electrode has retreated;
Processing is performed by anisotropic dry etching so that an insulating film containing impurities remains only on the side surfaces of the gate electrode, and heat treatment is performed to diffuse impurities in the insulating film containing impurities into the diffusion layer to form an n-plus layer. However, this problem can be solved by forming the source electrode from above.

[0008]

[Function] According to the above structure, the gate electrode recedes from the edge of the insulating film and the gate insulating film, and the side insulating film is filled in that region, and the side insulating film that insulates and separates the gate electrode and the source electrode. Even if the size is reduced due to over-etching or the like during manufacturing, the gate electrode and source electrode will not be short-circuited. In addition, after recessing the gate electrode, heat treatment is performed to form a thermal oxide film on the edge of the recessed gate electrode, or by filling the entire recessed area with another insulating film, further ensuring short circuit prevention. It can be done.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

First, the structure of the semiconductor device of this embodiment will be explained.

FIG. 1 is a sectional view of the semiconductor element of this embodiment. The difference between this embodiment and the conventional example shown in FIG. 22 is that both ends of the gate electrode 31 are set back inward from the ends of the insulating film 22. The retreated region is filled with an insulating film 24 containing impurities. The insulating film 24 containing impurities that insulates and separates the gate electrode 31 and the source electrode 42 is
In the manufacturing process, over-etching or the like may cause a shape defect as shown in FIG. 23. According to this embodiment, even if the insulating film 24 containing impurities has a defective shape as shown in FIG. 23, the insulating film 24 is formed even at the end of the gate electrode 31 that is recessed from the end of the insulated gate. Therefore, the gate electrode 31 is not short-circuited with the source electrode 42.

Next, a method for manufacturing the semiconductor device of this embodiment will be described.

As shown in FIG. 2, on the n-minus layer 12,
A gate oxide film 21, a gate electrode 31, and an insulating film 22 are sequentially formed, and the photoresist 10 is processed into a predetermined shape by photolithography.

As shown in FIG. 3, the insulating film 22 is processed by anisotropic dry etching using the photoresist 10 as a mask.

As shown in FIG. 4, the gate electrode 31 is further processed by anisotropic dry etching using the same photoresist 10 as a mask. Thereafter, the polysilicon of the gate electrode 31 is isotropically dry etched from the end of the insulated gate using an etching solution containing, for example, hydrofluoric acid and nitric acid to retreat.

As shown in FIG. 5, using the insulated gate as a mask, a P-type impurity, such as boron, is ion-implanted into the removed portion and then diffused to form a P layer 13.

As shown in FIG. 6, anisotropic dry etching is performed again to form a gate oxide film 2 directly below the insulating film 22.
Process so that only 1 remains.

As shown in FIG. 7, an insulating film containing impurities, such as phosphorus glass 24, is deposited over the entire upper surface. At this time,
The region where the gate electrode 31 has retreated is also filled with phosphorus glass 24.

As shown in FIG. 8, processing is performed by anisotropic dry etching so that the phosphor glass 24 remains only on the side surfaces of the insulated gate.

As shown in FIG. 9, the phosphorus in the phosphor glass 24 is then diffused into the P layer 13 by heat treatment to form an n-plus type layer 15.

As shown in FIG. 10, a source electrode 42 is deposited from above, and the source electrode 42, the n-plus type layer 15, and the P
Layer 13 makes contact.

Next, the gate electrode 31, which is a feature of this embodiment,
Explain the regression limit of.

FIG. 11 is a cross-sectional view showing the amount of recession of the gate electrode 31. The amount of retreat A of the gate electrode 31 is determined by the amount of n diffused laterally from the edge of the insulated gate, as shown in FIG.
It is desirable to set the distance up to the bonding interface C between the plus type layer 15 and the P layer 13. This is because when it retreats beyond the junction interface between the n-plus type layer 15 and the P layer 13, even if a voltage is applied to the gate electrode 31, the vicinity of the surface of the P layer 13 directly under the gate electrode 31 will not be inverted to n-type. This is because a channel, which is a path through which electrons flow from the n-plus type layer 15, is not formed, resulting in a problem that the IGBT or power MOSFET does not operate.

FIG. 12 shows another embodiment in which the gate electrode 31 is recessed. Isotropic dry etching is used to process the gate electrode 31, and the gate electrode 31 remaining on the n-minus layer 12 is removed and the end of the gate electrode 31 is set back at the same time. According to this, the end shape of the gate electrode 31 after retreating is such that the lower part (A1 in the figure) does not exceed the end of the n-plus type layer 15 (C in the figure), and the upper part of the gate electrode 31 Since it is isotropic, it is etched more, and the n-plus type layer 1 is etched as shown in B in the figure.
5 (C in the figure). Since the amount of recession of the gate electrode 31 can be further increased, the insulation effect between the gate electrode 31 and the source electrode 42 can be further improved.

Next, another embodiment of the present invention will be shown.

FIG. 13 is a sectional view of a semiconductor device according to another embodiment. As shown in FIG. 12, after the gate electrode 31 is retreated, the ends of the gate electrode 31 are thermally oxidized to form a polysilicon thermal oxide film 32 used for the gate electrode 31. Thereby, the insulation effect between the gate electrode 31 and the source electrode 42 can be further improved.

Further, other embodiments of the present invention will be described.

FIG. 14 is a cross-sectional view of a semiconductor device according to another embodiment. As shown in FIG. 12, between the end of the gate electrode 31 after retreating and the impurity-containing film 24 provided on the side surface of the insulated gate, another insulating film is placed in contact with the side surface of the insulated gate.
For example, SiO2 or SiN is formed. An example of a method for forming this insulating film 33 will be explained below with reference to the drawings.

As shown in FIG. 15, the steps up to processing an insulated gate consisting of three layers of gate oxide film 21, gate electrode 31, and insulating film 22 are the same as those in FIGS. 2 to 10.

As shown in FIG. 16, an insulating film 33 is formed on the entire upper surface.
, for example, depositing SiO2, SiN.

As shown in FIG. 17, processing is performed by anisotropic dry etching so that the insulating film 33 deposited in the previous step remains only on the side surfaces of the insulated gate.

As shown in FIG. 18, an insulating film 24 containing impurities, such as phosphorus glass, is further deposited over the entire upper surface.

As shown in FIG. 19, on the side of the insulated gate,
Processing is performed by anisotropic dry etching so that the phosphor glass 24 remains only on the surface in contact with the insulating film 33 formed in the previous step.

As shown in FIG. 20, phosphorus contained in the phosphorus glass 24 formed in the previous step is diffused into the P layer 13 by heat treatment, forming an n-plus type layer 15, and finally, from above. A source electrode 42 is deposited to complete the process.

According to the embodiments described above, the gate electrode 31 and the source electrode 42 can be insulated and separated more reliably.

Next, an example of application of the semiconductor device of this embodiment will be explained.

FIG. 21 shows a sectional view of a lateral type IGBT or power MOSFET to which this embodiment is applied. In the case of the vertical type, the same effect as the lateral type can be obtained.

In the embodiment described above, since the gate electrode 31 is set back from the end of the insulated gate, the gate electrode 31
The area where the gate oxide film is located directly below is reduced, and the input capacitance can be reduced in proportion to the amount by which the input capacitance between the gate electrode and the source electrode is set back, as in area A in FIG. 10, for example.

According to this embodiment, since the gate electrode 31 is recessed from the end of the insulated gate, even if the insulating film 24 containing impurities formed on the side surface of the insulated gate has a defective shape, the recessed region can be removed. With the insulating film formed in the above, it is possible to reliably insulate between the gate electrode and the source electrode. Therefore, product defects due to short circuits can be prevented, and the yield of breakdown voltage between the gate electrode and the source electrode can be improved from 60% to 90%.

Further, if the end portion of the gate electrode 31 after retreating is oxidized by thermal oxidation, the insulation can be further ensured.

[0041] Then, between the end of the gate electrode 31 after retreating and the insulating film 24 containing impurities provided on the side surface of the insulated gate, a region in contact with the retreated region and the side surface of the insulated gate is
For example, if an insulating film 33 made of SiO2, SiN, etc. is provided, insulation can be further ensured. In addition, the gate electrode 3
By recessing the gate electrode 1, the area where the gate oxide film 21 exists directly under the gate electrode 31 is reduced, so that the input capacitance can be reduced, and as a result, the switching speed can be increased.

[0042]

[Effects of the Invention] According to the present invention, the gate electrode is an insulating film,
Since the region is set back from the end of the gate insulating film and filled with the side insulating film, an effect of preventing short circuit between the gate electrode and the source electrode can be obtained.

Furthermore, after recessing the gate electrode, heat treatment is performed to form a thermal oxide film on the end of the recessed gate electrode, or by filling the entire recessed region with another insulating film, further short circuiting can be achieved. The effect of ensuring prevention can be obtained.

[Brief explanation of drawings]

FIG. 1 is a longitudinal cross-sectional view showing the configuration of a semiconductor device of the present invention.

FIG. 2 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 3 is a longitudinal cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 5 is a longitudinal cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 6 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 7 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 8 is a longitudinal cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 9 is a longitudinal cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 10 is a vertical cross-sectional view showing the manufacturing process of the semiconductor device of the present invention.

FIG. 11 is a longitudinal cross-sectional view showing the amount of recession of the gate electrode of the semiconductor device of the present invention.

FIG. 12 is a longitudinal sectional view showing another embodiment in which the gate electrode of the semiconductor device of the present invention is retracted.

FIG. 13 is a longitudinal cross-sectional view of the semiconductor device of the present invention in which the gate electrode is retreated and its end portions are heat-treated.

FIG. 14 is a vertical cross-sectional view of the semiconductor device of the present invention in which the region where the gate electrode is set back is filled with another insulating film.

FIG. 15 is a longitudinal cross-sectional view showing another manufacturing process of the semiconductor device of the present invention.

FIG. 16 is a vertical cross-sectional view showing another manufacturing process of the semiconductor device of the present invention.

FIG. 17 is a vertical cross-sectional view showing another manufacturing process of the semiconductor device of the present invention.

FIG. 18 is a longitudinal sectional view showing another manufacturing process of the semiconductor device of the present invention.

FIG. 19 is a longitudinal cross-sectional view showing another manufacturing process of the semiconductor device of the present invention.

FIG. 20 is a longitudinal sectional view showing another manufacturing process of the semiconductor device of the present invention.

FIG. 21 is a cross-sectional view of an IGBT or power MOSFET to which the semiconductor device of the present invention is applied.

FIG. 22 is a longitudinal cross-sectional view showing the configuration of a conventional semiconductor device.

FIG. 23 is a longitudinal cross-sectional view showing a state in which a gate electrode and a source electrode are short-circuited during manufacturing of a conventional semiconductor device.

FIG. 24 is a longitudinal cross-sectional view showing a state in which a gate electrode and a source electrode are short-circuited during manufacturing of a conventional semiconductor device.

[Explanation of symbols]

1 Semiconductor device 10 Photoresist 11 Semiconductor substrate 12 n-minus layer 13 P layer 15 n-plus type layer 21 Gate oxide film 22 Insulating film 24 Insulating film containing impurities 31 Gate electrode 32 Thermal oxide film 33 Other insulation films 41 Drain electrode 42 Source electrode

Claims (10)

[Claims] 1. An insulated gate in which a gate insulating film, a gate electrode, and an insulating film are sequentially laminated on the surface of a semiconductor layer of one conductivity type having a drain electrode, and a high impurity concentration that reaches below the insulated gate in the semiconductor layer. a side insulating film containing an impurity of one conductivity type provided on a side surface of the insulated gate, and a side insulating film formed on the insulating film, the side insulating film, and the well layer; In a semiconductor device having a source layer of one conductivity type which has an impurity concentration higher than that of the well layer and has an impurity diffused into the well layer, the side insulating film is provided in a region where the end face of the gate electrode is set back from the end face of the insulating film. A semiconductor device characterized by being filled with. 2. The semiconductor device according to claim 1, wherein the gate electrode is formed so that the amount of recession on the side of the insulating film is larger than the amount of recession of the gate insulating film. 3. At least a recessed position of the gate electrode on the side of the gate insulating film is between an end surface of the gate insulating film and an end of the source layer extending below the insulated gate of one conductivity type. The semiconductor device according to claim 1 or claim 2. 4. Another insulating film is provided between the gate electrode and a side insulating film provided on a side surface of the insulated gate. The semiconductor device described in . 5. The semiconductor device according to claim 4, wherein the other insulating film is a thermal oxide film. 6. The side insulating film provided on the side surface of the insulated gate is made of SiO2, SiN, PSG, or polysilicon, and the other insulating film is made of SiO2, SiN, PSG, or B.
6. The semiconductor device according to claim 5, wherein the semiconductor device is SG. 7. An IGBT using the semiconductor device according to claim 1 or 2. 8. A MOSFET characterized by using the semiconductor device according to claim 1 or claim 2. 9. A gate insulating film, a gate electrode, and an insulating film are sequentially laminated on the surface of a semiconductor layer of one conductivity type having a drain electrode, and a photoresist baked in the shape of the gate electrode is used as a mask on the insulating film. The gate electrode is processed by isotropic dry etching to form an end face, the end face of the gate electrode is processed by isotropic dry etching to retreat from the end face of the insulating film, and impurities are implanted using the gate electrode as a mask. A well diffusion layer is formed using the insulating film, and the gate insulating film is processed by anisotropic dry etching to leave the gate insulating film directly under the insulating film, and an insulating film containing impurities is formed on the entire surface of the insulating film, filling the area where the gate electrode has receded. Then, the insulating film containing the impurity is processed by anisotropic dry etching so that the insulating film containing the impurity remains only on the side surface of the gate electrode, and heat treatment is performed so that the impurity in the insulating film containing the impurity is diffused into the diffusion layer and becomes an n+ 1. A method of manufacturing a semiconductor device, comprising forming a layer and forming a source electrode from above. 10. A gate insulating film, a gate electrode, and an insulating film are sequentially laminated on the surface of a semiconductor layer of one conductivity type having a drain electrode, and a photoresist baked in the shape of the gate electrode on the insulating film is used as a mask to conduct an anisotropic process. The gate electrode is processed by isotropic dry etching to form an end face, the end face of the gate electrode is processed by isotropic dry etching to retreat from the end face of the insulating film, and impurities are implanted using the gate electrode as a mask. A well diffusion layer is formed by forming a well diffusion layer, and processed by anisotropic dry etching so as to leave a gate insulating film directly under the insulating film, and another insulating film is formed on the entire surface, filling the area where the gate electrode has receded. and processing by anisotropic dry etching so that the other insulating film remains only on the side surfaces of the gate electrode, forming an insulating film containing impurities on the entire surface, and containing the impurities only on the side surfaces of the gate electrode. Processing is performed by anisotropic dry etching so that the insulating film remains, and heat treatment is performed so that the impurity in the insulating film containing the impurity is diffused into the diffusion layer to form an n-plus layer, and a source electrode is formed from above. A method for manufacturing a semiconductor device, characterized by: