JPH0429897U - - Google Patents
Info
- Publication number
- JPH0429897U JPH0429897U JP6953590U JP6953590U JPH0429897U JP H0429897 U JPH0429897 U JP H0429897U JP 6953590 U JP6953590 U JP 6953590U JP 6953590 U JP6953590 U JP 6953590U JP H0429897 U JPH0429897 U JP H0429897U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- clock
- circuit
- memory
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002194 synthesizing effect Effects 0.000 claims 2
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electric Clocks (AREA)
Description
第１図は本考案の実施例を示すブロツク図、第
２図乃至第４図は本実施例の動作を説明するフロ
ーチヤート、第５図ａ〜ｈは本実施例の表示態様
を示す模式図である。
３……第１入力手段、４……時計キー、５……
登録キー、６ａ〜６ｄ……上下左右移動キー、８
……パターンメモリ、９……表示部、１１……時
計回路、１２……時計パターン発生回路、１３…
…図形パターン入力部。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 to 4 are flowcharts explaining the operation of this embodiment, and FIGS. 5 a to 5 h are schematic diagrams showing display modes of this embodiment. It is. 3...First input means, 4...Clock key, 5...
Registration keys, 6a-6d...Up/down/left/right movement keys, 8
...Pattern memory, 9...Display section, 11...Clock circuit, 12...Clock pattern generation circuit, 13...
...Graphic pattern input section.
Claims (1)
時間に応答して時計パターンを出力する時計パタ
ーン発生回路と、複数のパターンが格納されたパ
ターンメモリと、該パターンメモリ中のパターン
の１つを選択する手段と、該選択手段により選択
されたパターンと上記時計パターン発生回路より
出力された時計パターンとを合成する手段と、該
合成手段により合成されたパターンを表示する手
段とを備えたことを特徴とする時刻表示回路。 (2) 請求項１記載の時刻表示回路であつて、更
に図形パターン入力部を備え、該入力部より入力
されたパターンを上記パターンメモリ中に格納可
能としたことを特徴とする時刻表示回路。[Scope of Claim for Utility Model Registration] (1) A clock circuit that counts time, a clock pattern generation circuit that outputs a clock pattern in response to the counting time of the circuit, and a pattern memory that stores a plurality of patterns; means for selecting one of the patterns in the pattern memory; means for synthesizing the pattern selected by the selecting means and the clock pattern output from the clock pattern generation circuit; and the pattern synthesized by the synthesizing means. A time display circuit comprising means for displaying. (2) The time display circuit according to claim 1, further comprising a graphic pattern input section, and a pattern input from the input section can be stored in the pattern memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6953590U JPH0429897U (en) | 1990-06-28 | 1990-06-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6953590U JPH0429897U (en) | 1990-06-28 | 1990-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0429897U true JPH0429897U (en) | 1992-03-10 |
Family
ID=31604922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6953590U Pending JPH0429897U (en) | 1990-06-28 | 1990-06-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0429897U (en) |
-
1990
- 1990-06-28 JP JP6953590U patent/JPH0429897U/ja active Pending
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