JPH04297940A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the scale of an error code correction circuit, to improve the yield of the semiconductor memory and to realize high reliability. CONSTITUTION:This semiconductor memory is composed of a shift register SFR0 to temporarily preserve output data composed of information bits D0-D3 and parity bits C0-C2 parallelly outputted from a memory array M, cyclic code correction circuit EC to calculate syndrome corresponding to the transfer cycle of this shift register, and exclusive OR circuit EXOR1 to logically operate the output of the shift register and the output of the cyclic code correction circuit EC.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for suppressing an increase in the size of additional circuitry and improving yield in a semiconductor memory that detects and self-corrects errors.

0002

2. Description of the Related Art A conventional self-correctable semiconductor memory is shown in FIG. In order to simplify the explanation, this semiconductor memory has data consisting of 4 information bits and 3 parity bits.
An example is shown in which a (7, 4) Hamming code correction circuit is applied to correct an error in any one bit of the data. In FIG. 3, M is a memory array, MD is an information data array in this memory array M, MC is a parity data array in the memory array M, D0, D1, D2, D3 are information bits, C0, C1 , C2 are parity bits. 1-1, 1-2, 1-3 are 4-input parity check circuits, 2-1, 2-2, 2-3, 2-4 are 2-input exclusive OR circuits, 3-1, 3-2 , 3-3, 3-4 are three-input AND circuits, 4-1, 4-2, 4-3 are negative elements,
These constitute an error correction circuit EC. S0, S1
, S2, S0N, S1N, and S2N are complementary signals of the syndrome (coded position of error bit), C
D0, CD1, CD2, CD3 are signals indicating the position of bit error, DC0, DC1, DC2, DC3 are information bits after correction, SFR2 is a shift register, CL
K3 is an external clock, and OUT3 is an output signal.

Next, the operation of this circuit will be explained. First, information bits D0 to D3 are extracted from the information data array MD.
and parity bit C from parity data array MC.
0 to C2 are output. Parity checks are performed on the output bits by four-input parity check circuits 1-1 to 1-3 for each group involved in code parity bit generation. Signals S0 to S2 and signals S0N, S1N, and S2N generated by negation elements 4-1 to 4-3 are information bits D0 to
3-input AND circuit 3 that detects bit errors in D3
-1 to 3-4 (syndrome decoder). If there is a 1-bit error among the information bits D0 to D3, the signals CD0 to CD of the 3-input AND circuits 3-1 to 3-4
3, one of the inputs to the two-input exclusive OR circuits 2-1 to 2-4 corresponding to the information bits D0 to D3 becomes "1". If there is no error in the information bits D0 to D3, 3
Signals CD0 to CD3 of input AND circuits 3-1 to 3-4 all become "0". According to signals CD0 to CD3,
The 2-input exclusive OR circuits 2-1 to 2-4 correct the information bits D0 to D3 by inverting them (the ones that become "1" among CD0 to CD3), and correct the information bits DC0 to D3 after correction.
Output C3. After this value is stored in the shift register SFR2, it is serially outputted using an external clock CLK3.

0004

[Problem to be solved by the invention] In the above conventional configuration,
In order to perform parallel correction operations, syndrome decoders 3-1 to 3-4 and negation elements 4-1 to 4 are used depending on the information bit width.
- It was necessary to prepare a 3rd grade. Therefore, as the number of information bits D0 to D3 increases with the increase in memory size, there is a problem in that the scale of the error correction circuit required to maintain the defect repair rate increases.

SUMMARY OF THE INVENTION An object of the present invention is to reduce the scale of an error code correction circuit by using a cyclic code in order to solve the above-mentioned problems, and to improve the yield and reliability of a semiconductor memory.

[0006]

[Means for Solving the Problems] A semiconductor memory according to the present invention includes (1) arranging shift registers whose number of bits corresponds to bits read from a memory array;
) A cyclic code correction circuit is provided which receives data from any one end of the shift register and generates a syndrome.

[0007]

In the present invention, data in a shift register storing information bits is sequentially corrected and supplied to the outside.

The difference from the conventional technology is that (1) there is no need to provide a data inversion circuit corresponding to the information bit width of the memory array M, and error correction can be realized with only one data inversion circuit; 2) Syndrome decoders and the like can be reduced by data transfer through serial operation; and (3) error correction circuits can be shared even in a plurality of memory arrays or in any divided memory array configuration.

[0009]

Embodiment (Embodiment 1) FIG. 1 is a diagram showing a first embodiment of the present invention. In the first embodiment, in order to simplify the explanation, an error in any one bit of a data example consisting of 4 information bits and 3 parity bits is corrected (7, 4
) shows how to perform cyclic code error correction. M is a memory array, MD is an information data array in this memory array M,
MC is also a parity data array in memory array M, D0, D1, D2, D3 are information bits, C0, C1
, C2 are parity bits. SFR0, SFR1
is a shift register, and SFR0 is a latch m1 to m7
SFR1 consists of latches s0 to s7, and SW
1 is a switch, and EXOR1 is an exclusive OR circuit. Furthermore, SRa, SRb, and SRc are 1-bit shift registers, EOR21 and EOR22 are exclusive OR circuits, INV is a negative element, and NOR is a 3-input negative logical sum element. SRa, SRb, SRc and EOR21,E
The OR22 forms a division circuit, the negation element INV and the 3-input negation logic element NOR form a (1, 0, 0) detection circuit for (SRa, SRb, SRc) data, and the division circuit and (1, 0)
, 0) The detection circuit forms a cyclic code correction circuit EC. C
KL is an external clock.

Next, the operation will be explained. Information bits DO to D3 from memory array M and parity bit C
0 to C2 are simultaneously output from each output terminal and latched simultaneously by each latch m1 to m7 of shift register SFR0. The output of latch m7 is connected to terminal i by switch SW1.
1, and data is sequentially shifted to the right by an external clock CLK. Here, the data in the latch m7 is passed to the latch s0, and is also input to the exclusive OR circuit EOR21 in the cyclic code correction circuit EC to generate a syndrome using the external clock CLK. The syndrome generation and correction operations will be explained below.

From terminal i1, information bits D3, D2, D1, D0 stored in latches m7 to m4, latches m3 to
The parity bits C2, C1, C0 stored in m1 are synchronized with the external clock CLK, and the parity bits D3, D2, D1,
Input D0, C2, C1, C0 in this order. Here, C2
, C1 and C0 respectively, C2=D3+D2+D1 (mod2),
...(1) C1=D2
+D1+D0 (mod2),
...(2)C0=D3+D2+D
0 (mod2),
...There is a relationship (3) (mod 2 is 2
(remainder). That is, the data string (D3, D2, D1, D
0, C2, C1, C0), if there is no error, then (1) to
This means that equation (3) always holds true. Specifically, the data string (D3', D2') read from the memory array M
, D1', D0', C2', C1', C0') will be described below. For example, (D
3', D2', D1', D0', C2', C1', C0
'), if there is an error in D0', D0'=D0+1 (mod2),
...(4), where the data string (D3', D2', D1', D
0', C2', C1', C0'), (D3', D2
', D1', D0', C2', C1', C0') = (D
3+0, D2+0, D1+0, D0+1, C2+0, C
There is a relationship as follows: 1+0, C0+0) (mod 2)...(5). Any error-free data string (D3, D2, D1,
D0, C2, C1, C0) are input to the cyclic code correction circuit EC, the output from the (number of input data + 2) rounds is " 0”. This is the test target (D3', D2', D1', D
The test results for (0', C2', C1', C0') are (5)
From the formula, it means that it is equivalent to testing (0, 0, 0, 1, 0, 0, 0). That is, equation (5) is (D3', D2', D1', D0', C2', C1',
C0') = (0, 0, 0, 1, 0, 0, 0) (mod2
)
...is equal to (5'). (0,0,0,1
, 0, 0, 0) are input to the cyclic code correction circuit EC. If there is an error in the mth data counted from the beginning, ([number of data M] + 1
+m) The flag "1" will be set at the output in the third cycle. Therefore, in this example, since M=7 and m=4, the first
In the second round, the output becomes "1". This cyclic code correction circuit E
C is, for example, [Hiroshi Miyagawa, Yoshihiro Iwadare, Hideki Imai; "Coding Theory" pp. 252-253, published October 5, 1973, Shokodo], it can be determined according to the number of information bits, the number of parity bits, and the correction ability.

When the data in latches m1 to m7 are transferred to latches s1 to s7, respectively, the cyclic code correction circuit EC is ready to output the syndrome to the outside. In synchronization with the external clock CLK, the data in the shift register SFR1 is shifted in the order of latches s7, s6, s5, s4, s3, s2, s1 and output from the latch s7, and the error pattern of the cyclic code correction circuit EC is changed. -on detection bit is output. Data is output at each step of the external clock CLK by exclusive ORing of the data in the shift register SFR1 and the data pattern detection bit of the cyclic code correction circuit EC. Therefore, in synchronization with the output of the data in which the data of the latches s1 to s7 are errors, the cyclic code correction circuit EC
The output becomes "1", and the data in latches s1 to S7 are inverted (corrected). In this example, in the 12th round, the output a0' and the syndrome generation circuit (EOR21, EOR22, SRa
, SRb, SRc) with the correction flag "1" (symbol [EOR]), D0'
[EOR] 1=D0+[EOR]1=D0[EOR]0
=D0...(6) is corrected and outputs OUT1.

In this embodiment, the number of memory arrays M is 1, the number of output data is 4, and the correctable bit is 1. However, even if the number of memory arrays M is set arbitrarily and switched at any time, the output data
This can be easily realized by using any number of data and by changing the correction capability of the cyclic code correction circuit EC.

[0014]

[Table 1] (Example 2) FIG. 2 is a diagram showing a second example of the present invention. In the second embodiment, the shift registers SFR0 and SFR1 in the first embodiment are shared, and only the shift register SFR1 is used, thereby further reducing the scale of the additional circuit. FIG. 2 shows a method of performing (7,4) cyclic code error correction on a single memory array M, similar to the first embodiment. In this figure, the same symbols as in FIG. 1 indicate the same things.

The concept of operation is shown below. Information bits D0-D3 from memory array M and parity bits C0-C
2 simultaneously outputs from the output terminal and shifts the shift register SF.
Each of the latches s1 to s7 of R1 latches the data simultaneously, and the data is sequentially shifted clockwise by the external clock CLK. Switch SW1 outputs the shift register SFR1,
Connect to terminal i1. Here, the data in the latch s7 is passed to the latch s0, and is also input to the cyclic code correction circuit EC to generate a syndrome using the external clock CLK. When the data of latches s1 to s7 completes one cycle,
The cyclic code correction circuit EC is ready to output the syndrome to the outside. The switch SW1 is immediately connected to the terminal i2, and the shift register SF is connected to the terminal i2 by the external clock CLK.
The data of R1 is latched s7, s6, s5, s4, s3,
In synchronization with the sequential output of s2 and s1, the error pattern detection bit of the cyclic code correction circuit EC is output. Data of shift register SFR1 and cyclic code correction circuit E
By exclusive OR of error pattern detection bits of C,
Data is output every step of the external clock CLK. Specifically, when the data of the latches s1 to s7 is erroneous, the output of the cyclic code correction circuit EC becomes "1".
'', the data in the latches s1 to s7 are inverted, and the output signal OUT1 is output.

Furthermore, the configurations of the memory array M, shift register SFR1, and cyclic code correction circuit EC in the present invention are not limited to those shown in FIGS. 1 and 2. For example, the number of memory arrays M can be set arbitrarily and switched at any time, the number of output data can be set arbitrarily, and the correction capability of the cyclic code correction circuit EC can also be changed. Further, according to the present invention, a plurality of cyclic code correction circuits EC are provided for the memory array group.
It is also possible to operate at high speed by preparing a plurality of cyclic code correction circuits EC, staggering the periods of syndrome generation and correction data output, and mutually outputting them from a plurality of cyclic code correction circuits EC.

In order to confirm the effect of reducing the additional circuit size range of the present invention, the amount of metal materials in the conventional example, Example 1, and Example 2 was
Compare by number of S transistors. First, the relationship between information bits and parity bits in the single error correction (SEC) circuit shown in this example is as follows: number of code bits: n, number of information bits:
k, parity bit number: m, then according to Hamming's limit formula, n=2m -1

...(7)n=m+k

...(8). [Conventional hardware quantity] The 4-input parity check circuits 1-1 to 1-3 shown in FIG. 3
;2m, syndrome decoder 3-1~3-4;(2+
2m)×k, 2-input exclusive OR circuits 2-1 to 2-4;
12k, output register; 8k, so the total number of transistors Nn is: Nn=22k+26m+2mk
...(9
) [Metal quantities of Examples 1 and 2] Number of transistors in shift register SFR0 of memory array output section; 8n; shift register SFR1 of cyclic code correction circuit EC; 8n; 1-bit shift registers SRa, SRb in division circuit; S.R.
c; 8m, 2-input exclusive OR circuit 2-1 to 2-4; 6
0, INV; 2, NOR; 2m, so the total number of transistors N1 is: N1 = 16n + 10m + 62 = 16k + 26m + 62
...(10) Also, according to the second embodiment, the shift register SFR0 of the memory array output section is not required, so the total number of transistors N2 is: N2 = 8n + 10m + 62 = 8k + 18m + 62
...(11) Equations (9) to (11
), Table 2 compares the amounts of metal materials in practical use, and Figure 4 shows a graph. According to Example 2,
It can be seen that when the number of information bits is 4 or more, the additional circuit scale is smaller than that of the conventional example, and as the number of information bits increases, the effect of reducing the additional circuit scale becomes remarkable.

[0018]

[Table 2]

[0019]

Effects of the Invention The present invention provides a shift register for temporarily storing output data consisting of information data and parity data to be output from a memory array in parallel, and It consists of a cyclic code correction circuit that calculates the error code correction circuit, and a circuit that performs logical operations on the output of the shift register and the output of the cyclic code correction circuit. It is possible to significantly reduce the circuit scale, and the effect is extremely large when applied to image field memory, large-scale ROM, RAM, etc.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a diagram showing the amount of hardware for information bits in the conventional example, the first embodiment, and the second embodiment.

[Explanation of symbols]

M Memory array MC Parity data array MD
Information data array SFR0 Shift register SFR1 Shift register SW1 Switch EC Cyclic code correction circuit EXOR1
Exclusive OR circuit CLK External clock

Claims (1)

[Claims] Claim 1: Consisting of a memory array for storing information data and a memory array for storing parity data, each memory array has a plurality of memory cells and a plurality of word lines and bit lines connected thereto. In a semiconductor memory that self-corrects internally using information data and parity data output to an arbitrary bit line by a word line selected by an address and serially outputs information data, A shift register that temporarily stores output data consisting of information data and parity data output in parallel from the memory array, and a cyclic code that calculates syndromes in accordance with the transfer cycle of this shift register. A semiconductor memory comprising: a correction circuit; and a circuit that performs a logical operation on the output of the shift register and the output of the cyclic code correction circuit.