JPH04297074A - Semiconductor photodetector - Google Patents

Abstract

PURPOSE:To prevent deterioration of high speed response due to the running time of carrier and decrease of quantum efficiency by providing a p-type InP region in an n-type InP layer interposed between n-type InGaAs light absorption layers. CONSTITUTION:An n-type InP buffer layer 2, an n-type InGaAs light absorption layer 3, and an n-type InP layer 4 are sequentially grown on an InP substrate, a p-type region 5 is formed at a predetermined region of the n-type InP layer, and the layer 3 and an n-type InP cap layer 6 are again epitaxially grown. A half is etched to the layer 2 in this state, and the other half is mesa etched to the substrate 1. Thereafter, a surface protective film 7 is grown on the entire surface, a stripelike p-type side electrode 8s provided from an oblique part of the region 5 to the lower substrate 1, and an ohmic electrode 9 is provided on the layers 6 and 2. Thus, a running time in the n-type InGaAs light absorption layer can be accelerated, and further a sufficient quantum efficiency is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light receiving element used in optical communication, optical information processing, etc.

0002

[Prior Art] Compound semiconductor photodetectors have been put into practical use as high-sensitivity photodetectors for optical communications and optical information processing, and InGaAs is widely used as a material for semiconductor photodetectors for wavelengths of 1.55 μm for large-capacity, long-distance optical communications. It is used.

A conventional PIN photodiode using InGaAs has an n-type InP buffer layer 2, an n-type InGaAs light absorption layer 3, and an n-type InP layer 4 stacked on an n-type InP substrate 12, as shown in FIG. p in the n-type InP layer.
It has a structure in which areas are formed. This InGaAs
In order to realize ultra-high-speed response of a PIN photodiode using PIN photodiodes, it is necessary to make the light absorption layer 3 thinner and to reduce the pn junction capacitance in order to shorten the carrier transit time. However, if the light absorption layer is made thinner in order to shorten the transit time, the response speed will be improved, but the quantum efficiency will decrease because more light will be transmitted without being absorbed.

0004

[Problem to be solved by the invention] In the conventional example described above, 2
In the case of a PIN photodiode with a thin light absorption layer of less than μm, the 1.55 μm light incident from the light receiving part is n-In.
It is absorbed in the GaAs light absorption layer, but this light absorption layer is
When it is thin, such as less than μm, there is a problem that the absorption is not completed and a portion of it is transmitted, resulting in a decrease in quantum efficiency.

[0005]

SUMMARY OF THE INVENTION A semiconductor light-receiving device of the present invention has a p-InP region inside an n-InP layer sandwiched between n-InGaAs light absorption layers.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. FIG. 2 shows the process of forming the light receiving element. n-InP buffer layer 2, n-InG on semi-insulating InP substrate 1
The aAs light absorption layer 3 and the n-InP layer 4 are grown in sequence (
Figure 2(a)). In this state, the n-InP layer is shown in Figure 2(b).
, (c) ((c) is a plan view) After forming p region 5 using FIB in the hatched area, n-
An InGaAs light absorption layer 3 and an n-InP cap layer 6 are epitaxially grown (FIG. 2(d)). In this state, half is etched to the InP buffer layer 2, and the other half is mesa-etched to the semi-insulating substrate 1 (Figure 2(e)).
. After that, a surface protective film 7 is grown on the entire surface, and then a striped p-side electrode 8 is formed from the sloped part of the p-InP layer 5 to the substrate 1 below, and also to the n-InP cap layer 6 and the n-InP buffer layer 2. An ohmic electrode 9 is provided, and these two contacts are connected to form an n-side electrode 10. A cross section of the semiconductor light receiving element formed in this manner is shown in FIG. 1(a), and a plan view is shown in FIG. 1(b).

In the PIN photodiode manufactured in this manner, 1.55
μm light is absorbed by the upper n-InGaAs light absorption layer 3, but the light that is transmitted without being absorbed is absorbed by the lower n-InGaAs light absorption layer 3 after passing through the p-InP layer 5. That will happen. At this time, by applying a voltage to the p-side electrode 8 and the n-side electrode 10 so that they are in a reverse bias state, a depletion layer is formed in the n-InGaAs layer 3 provided above and below the p-InP layer 5.
Therefore, carriers generated in the upper and lower n-InGaAs layers 3 can be extracted as a signal. Therefore, the transit time in the n-InGaAs light absorption layer can be made faster, and sufficient quantum efficiency can be obtained.

[0008] Furthermore, when forming the p-region in the FIB, the p-n junction capacitance can be reduced by making the diameter of the p-region the same as the light-receiving diameter.

[0009]

As explained above, the present invention prevents deterioration of high-speed response due to carrier transit time by disposing thin light absorption layers above and below the n-InP layer including the p region, and also prevents the deterioration of high-speed response due to carrier transit time. The decrease in quantum efficiency caused by making the absorption layer thinner can be prevented because it is absorbed by the two light absorption layers. Furthermore, by making the p region in the n-InP layer provided between the two light absorbing layers the same size as the light receiving diameter, the pn junction capacitance can be reduced and faster response can be achieved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view and a plan view of a light receiving element of the present invention.

FIG. 2 is a diagram showing the manufacturing process of the semiconductor light receiving element of the present invention.

FIG. 3 is a diagram showing a conventional example.

[Explanation of symbols]

1 Semi-insulating InP substrate 2 n-InP buffer layer 3 n-InGaAs light absorption layer 4 n-InP layer 5 p region 6 n-InP cap layer 7 Surface protective film 8 P-side electrode 9 N-side ohmic electrode 10 N-side electrode 11 P-side ohmic electrode 12 n-InP substrate

Claims (1)

[Claims] 1. A semiconductor light-receiving device comprising an n-InP layer sandwiched between n-InGaAs light absorption layers and a p-InP region provided inside the n-InP layer.