JPH04296959A - Dma transfer control system - Google Patents

Abstract

PURPOSE:To improve the performance of a DMA transfer control system by reducing the overhead caused by a page fault. CONSTITUTION:When a page fault occurs, a CPU 1 instructs a secondary storage 4 to read the relevant page and also instructs a DMA transfer device 6 to transfer the page to a main storage MS 5. Thus the CPU 1 writes a transfer destination address, a page fault address, and a cache block size. The secondary storages 3 and 4 reads the pages with instructions and output these pages to a system bus 7. A DMA transfer device 6 transfers the outputted date and the transfer destination address to the MS 5 and at the same time compares the transfer destination address with the page fault address. When the coincidence is obtained between both addresses, the device 6 activates the write signal to be applied to a cache memory 2 end then inactivates the write signal when the transfer of date equivalent to a single block size of the memory 2 is over. Then the memory 2 fetches the transfer destination address and the date outputted to the bus 7 and writes them in the memory 2 when a cache write signal is activated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer control method in an information processing apparatus employing a virtual storage method and a cache storage device.

0002

[Prior Art] A DMA transfer device is a magnetic disk device,
When input/output devices such as communication devices and display devices are connected to a common data transfer path, data transfer between the input/output devices (hereinafter referred to as IO) and the main storage device is performed by the central processing unit (hereinafter referred to as IO) in order to increase response time. This is to perform high-speed processing in place of the CPU (hereinafter referred to as the CPU).

Cache storage is a high-speed memory that stores frequently accessed portions of main memory.
This reduces the apparent memory access time from the PU to the memory. A cache miss occurs when the CPU accesses data that is not in cache storage, resulting in reading the block containing the data into main storage.

Conventionally, in a central processing unit that employs a virtual storage system based on demand paging, the program is stored in a secondary storage device such as a magnetic disk when program execution starts, and only the pages needed during instruction execution are stored as the main processor. Put it in your storage device and run it. Therefore, if a page that is not yet in main memory is accessed during instruction execution, a page fault exception will occur.

[0005] When a page fault occurs, the CPU
issues a read command to the secondary storage device, and DM
Issue a transfer command from IO to memory to transfer device A, suspend the program that caused the page fault, and wait for a transfer end interrupt.

After the transfer is completed, the virtual address translation table is updated and the program is restarted. When restarted, no page fault occurs, so the program continues to run until the next page fault occurs. page·
When a fault occurs and the page is restarted, the cache storage device does not contain the data for that page, so the cache
Mistakes occur.

[0007]

[Problem to be solved by the invention] In this way, conventional DM
In the A transfer device, when a page fault occurs, access to the secondary storage device, reading due to a cache miss, etc. occur, which takes processing time and reduces the processing performance of the CPU.

[0008] An object of the present invention is to provide a DMA that reduces the read time by executing a block read of data that caused a page fault in the cache in parallel when accessing a secondary storage device when a page fault occurs. The objective is to provide a transfer method.

[0009]

[Means for Solving the Problems] The configuration of the present invention includes a central processing unit, a cache memory, a common data transfer path, a
In a DMA transfer control method for an information processing device that includes an MA transfer device, a main storage device, and a secondary storage device and uses a demand paging virtual storage method, the central processing unit transfers the data to the secondary storage device when a page fault occurs. Issues an instruction to read the corresponding page to the device, issues an instruction to the DMA transfer device to transfer the read page to the main storage device, and further issues the transfer destination address, the page fault address, and the cache. writing the block size, the secondary storage device reads the page according to the read instruction and outputs it to the common data transfer path;
The DMA transfer device transfers the data output to the common data transfer path and the transfer destination address to the main storage device in accordance with the transfer command, and at the same time transfers the data and transfer destination address to the memory currently being transferred.
The address and the page fault address are compared, and if they match, a cache write signal is activated for the cache memory, and when the transfer of one block size of this cache memory is completed, the cache write signal is A write signal is made inactive, and when the cache write signal becomes active, the cache memory takes in the transfer destination address and data output to the common data transfer path and writes them into the cache memory. shall be.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a DMA transfer device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a system using this embodiment. This system uses CPU
1. Cache memory 2. Secondary storage device (IOC, D
ISK) 3, 4, a main memory (MS) 5, a DMA transfer device 6, and a system bus 7.

Normally, the CPU 1 converts an instruction address or an operand address into a real address and outputs it to the cache 2, and if the data at the corresponding address is in the high-speed memory, the cache 2 delivers the data to the CPU 1. C.P.
U1 detects a page fault exception during address translation. At this time, the instruction address, operand address (
The data indicated by the virtual address does not exist in the main storage device 5 but exists in the secondary storage device 4.

[0012] When a page fault occurs, the CPU 1 performs the following operations.

(1) The CPU 1 issues an IO read command to the secondary storage devices 3 and 4, and the DMA transfer device 6
Writes the transfer destination memory address 25 to , writes the number of transfer bytes 27, and issues a transfer command from IO to memory. Furthermore, the page fault address 21 and cache block size 23 are written.

(2) Put the program that caused the page fault into a suspended state.

(3) If there is another executable program, execution is shifted to that program.

(4) Wait for IO end interrupt 15. IO
After the termination interrupt 15 occurs, the above-mentioned suspended program is re-executed. When re-executing, the instruction/address and operand address (virtual address) are converted into real addresses and output to the cache to obtain the data at that address.

The DMA transfer device 6 includes a comparator 22, decrementers 24 and 28, an address INC/DEC 26, a flip-flop F/F 29, and a bus control section 30, and performs the following operations.

(1) Data is transferred from the secondary storage device 4 to the main storage device 5.

When the DMA transfer request 11 of the secondary storage device 3 becomes active, the DMA transfer device 6 activates the acknowledge signal 12 and transfers IO to the secondary storage device 3.
Activate the R signal 13 and write W to the main storage device 5.
The R signal 9 is activated to perform DMA transfer.

(2) Address 31 and DM currently being transferred
The page fault address 21 stored in the A transfer device 6 is compared with the page fault address 21 by the comparator 22, and if they match, the F/F 29 is set and the write signals 34 and 8 are sent to the cache memory 2. .

(3) Count the completion of transfer for the block size. When match signal 33 from comparator 22 becomes active, decrementer 24 is loaded with cache block size 23 and begins counting. When the bus cycle end signal 35 from the bus control unit 30 becomes active, the decrementer 24 counts down. When the transfer for the block size is completed, the decrementer 24 becomes "0", the "0" detection signal 33 becomes active, the F/F 29 is reset, and the write signal 34 for the cache is made inactive.

When the cache memory write signals 34 and 8 become active, the cache memory 2 takes in the address and data output to the system bus 7 and stores them in the corresponding block of high-speed memory within the cache memory 2. Write data. This method makes it possible to transfer the data of the block where the page fault has occurred to the cache as well.

[0023] In this way, when a DMA transfer is performed from the secondary storage device to the memory due to a page fault, data is simultaneously written to the block corresponding to the page fault address of the cache, thereby preventing overflow due to a page fault. It is possible to shorten the head and improve performance.

FIG. 3 shows a DMA system according to a second embodiment of the present invention.
FIG. 2 is a block diagram of a transfer device. In the first embodiment, only one block including the page fault address is IO
In this embodiment, the block containing the page fault address and a plurality of consecutive blocks after it are simultaneously transferred to the cache when transferred from IO to memory. In this example, this is effective when a page fault occurs in an instruction address, because the instruction area has high local referentiality and there is a high possibility that consecutive blocks will be accessed.

The configuration of this embodiment is the same as that of the first embodiment except for the register 51 for storing the cache block size, the register 52 for storing the number of blocks to be successively transferred to the cache, and the decrementer 53. .

When a page fault occurs, the CPU 1 performs the following operations.

(1) The CPU 1 issues an IO read command to the secondary storage devices 3 and 4, and the DMA transfer device 6
The transfer destination memory address 25 is written to the memory address, the number of transfer bytes 27 is written, and a transfer command is issued from IO to the memory. Additionally page fault address 2
1. Write the cache block size 51 and the number of blocks to be written consecutively 52.

(2) Put the program that caused the page fault into a suspended state.

(3) If there is another executable program, execution is shifted to that program.

(4) Wait for IO end interrupt 15. After the IO end interrupt 15 occurs, the suspended program is re-executed. At the time of re-execution, the instruction/address and operand address (virtual address) are converted into real addresses and output to the cache 2 to obtain data at the addresses.

Further, the DMA transfer device 6 performs the following operations.

(1) Data is transferred from the secondary storage device 4 to the main storage device 5. DMA transfer request 1 for secondary storage device 3
1 becomes active, the DMA transfer device 6 activates the acknowledge signal 12, activates the IOR signal 13 for the secondary storage device 3, and activates the WR signal 9 for the main storage device 5 to perform the DMA transfer. conduct.

(2) Address 31 and DM currently being transferred
The comparator 22 compares the page fault address 21 stored in the A transfer device 6, and if they match, sets the F/F 29 and sends write signals 34 and 8 to the cache memory 2. send.

(3) Count the completion of transfer for the number of blocks x block size. When the match signal 33 from the comparator 22 becomes active, numbers are synthesized with the cache block size 51 as the lower and the block number 52 as the upper, and the synthesized value is loaded into the decrementer 53 to start counting. When the bus cycle end signal 35 from the bus control unit 30 becomes active, the decrementer 53 counts down. When the transfer for the block size is completed, the decrementer 53 becomes "0", the "0" detection signal 33 becomes active, the F/F 29 is reset, and the write signal 34 for the cache is made inactive.

When the cache memory write signals 34 and 8 become active, the cache memory 2 takes in the address data output to the system bus 7 and stores the data in the corresponding block of high-speed memory in the cache memory. Write.

With this method, it is possible to simultaneously transfer the data of the block in which a page fault has occurred and the data of a plurality of consecutive blocks subsequent to the cache from the IO to the memory.

[0037]

Effects of the Invention As explained above, according to the present invention, DM from the secondary storage device to the memory due to a page fault can be prevented.
By simultaneously writing data to the block corresponding to the page fault address of the cache during the A transfer, it is possible to reduce the overhead caused by page faults and improve performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a DMA transfer device in a first embodiment of the present invention.

FIG. 2 is a system configuration diagram using the embodiment of FIG. 1;

FIG. 3 is a block diagram of a DMA transfer device in a second embodiment of the present invention.

[Explanation of symbols] 1 CPU 2 Cache memory 3 IOC 4 Disk 5 MS 6 DMAC 7 System bus 21 Page fault address 22 Match circuit 23, 51 Cache block size 24
, 28, 53 Decrementer 25 Transfer destination/source memory address 26 Incrementer/decrementer 27 Number of transferred bytes 29 Flip-flop 30 Bus control unit 52 Number of blocks

Claims (1)

[Claims] [Claim 1] Central processing unit, cache memory,
Common data transfer path, DMA transfer device, main storage device, 2
In a DMA transfer control method for an information processing device equipped with a storage device and using a demand paging virtual storage method,
When a page fault occurs, the central processing unit issues an instruction to the secondary storage device to read the corresponding page, and issues an instruction to the DMA transfer device to transfer the read page to the main storage device. issue, further write the transfer destination address, the page fault address, and the cache block size, and the secondary storage device reads the page according to the read instruction and outputs it to the common data transfer path, and performs the DMA transfer. The device transfers the data output to the common data transfer path and the transfer destination address to the main storage device in accordance with the transfer command, and at the same time compares the memory address currently being transferred with the page fault address, and determines whether these are the same. If they match, a cache write signal is activated for the cache memory, and one block of this cache memory is written.
When the transfer for the size is completed, the cache write signal is made inactive, and when the cache write signal becomes active, the cache memory takes in the transfer destination address and data output to the common data transfer path and writes the data to the cache memory. - A DMA transfer control method characterized by writing into memory.