JPH04296913A - Phase control circuit - Google Patents

Abstract

PURPOSE:To realize the servo stability by multiplying a phase control signal by a specific coefficient to generate a correction value and adding this correction value to the phase control signal to reduce the variation. CONSTITUTION:A phase error signal generating means 10 which generates a phase error signal with a prescribed period, a multiplying means 11 which multiplies the generated phase error signal by a prescribed coefficient alpha smaller than one and outputs the result, and a storage means 12 where the output of the multiplying means 11 is successively stored at intervals of a time shorter than the prescribed period are provided, and the output of this means 12 is used as the phase control signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit used for controlling the rotation of a motor.

0002

2. Description of the Related Art When controlling the rotation of a motor or the like, speed control and phase control are usually performed. For example, video tape recorders use a capstan motor that feeds the tape and a head motor that drives a rotating head.The rotation of these motors must be precisely controlled, so speed and phase control are required. Control takes place.

[0003] Speed control is performed using so-called FG signals, which are generated multiple times during one revolution of the motor. Further, phase control is usually performed by comparing the phases of a so-called PG signal and a reference signal, which are generated once per rotation of the motor. In other words, the interval between generation of the phase control signal is longer than that of the speed control signal.

By the way, in the conventional example as described above, when the motor starts up, the interval between the creation of the phase control signal is long, so the previously created phase control signal and the currently created phase control signal are , and the phase control signal with this large change is added to the speed control signal and output until the next phase control signal is created. For this reason, there is a problem that the retracting position goes too far from the normal retracted position, and it takes time for the phase to lock. Furthermore, if the change in the phase control signal is large, there is also the problem that rotation control is unstable.

In order to eliminate such drawbacks, a configuration has been considered in which a phase control signal is created at the timing of the FG signal (Japanese Patent Laid-Open No. 63-208107, G05D13/
62). However, if such a configuration is adopted,
Since the speed error signal and phase error signal must be created at the timing of the FG signal, if the servo device is configured with a microcomputer, the processing time will increase, and the
A problem arises in that the G period cannot be made faster.

[0006]

[Problems to be Solved by the Invention] As described above, in the configuration of a control system that performs speed control and phase control, the problem with phase control is that the created period is large, which impairs the stability of the servo. be. Further, if the generation period of the phase control signal is shortened, processing time increases when a servo device is configured with a microcomputer, and the interval between generation of speed control signals cannot be made faster, resulting in a problem that servo performance deteriorates.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to realize means for generating a phase control signal that does not impair servo stability. Another aspect of the present invention is to achieve servo stability without shortening the interval between generation of phase control signals, and therefore to eliminate problems in configuring a servo device using a macrocomputer. do.

[0008]

[Means for Solving the Problem] In the present invention, a correction value is created by multiplying a phase error signal created at a relatively long creation time interval by a coefficient α of 1 or less, and this correction is performed at an interval shorter than the creation time interval. By adding the values, the range of change in the phase error signal is suppressed.

In yet another configuration, the difference between the previous phase error signal and the current phase error signal is calculated, and a predetermined coefficient determined by the ratio of the generation time interval of the phase error signal to the output cycle of the new phase error signal is calculated. A correction value is obtained by multiplying the difference value, and the correction value is sequentially added to the previous phase error signal at intervals of the output cycle of the new phase error signal.

0010

[Operation] In the present invention, the phase error signal itself is created at the same intervals as in the prior art. However, the variation width of the output phase error signal is suppressed, the output interval is shortened, and the output phase error signal changes smoothly.

[0011]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment. This embodiment is configured to utilize the difference between the phase error signal created last time and the phase error signal created this time.

In FIG. 1, 1 is a phase error signal generating means, 2 is a first holding means, 3 is a second holding means, and 4 is a difference calculating means for calculating the difference between the outputs of the first holding means 2 and the second holding means 3. Calculating means; 5 is a dividing means for dividing this difference value by a predetermined coefficient n; 6 is a calculating means for sequentially adding the output of this dividing means 5 to the previous phase error signal and outputting the result; 7 is an operation timing of this calculating means. and timing means for controlling the operation timing of the first and second holding means.

A PG signal from a motor, for example, a cylinder motor in a VTR, and a reference signal (a 30 Hz signal in the case of a cylinder motor) are input to the phase error signal generating means 1, and a phase error signal is generated based on the phase difference between the two. is created and output. Here, the phase error signal is 1/30
Created every second. Then, the created phase error signal is stored in the first holding means 2 according to an instruction from the timing means 7. At this time, the value previously stored in the first holding circuit 2, that is, the previous phase error signal, becomes the second
It is transferred to the holding means 3 and stored.

The difference calculating means 4 calculates the difference between the values stored in the first holding means 2 and the second holding means 3. Therefore, the value of the difference between the previous phase error signal and the current phase error signal is determined by the difference calculation means 4 and output. The output from the difference calculation means 4 is divided by a predetermined coefficient n by the division means 5. n is determined as follows. Let Ta be the creation interval of the phase error signal in the phase error signal creation means 1, and let Tn be the output cycle of the newly outputted phase error signal, where n is equal to Ta/Tn. Typically, Ta is 1/30th of a second and the new output period Tn is shorter than this, so n will be greater than 1. Therefore, the output of the dividing means 5 is always a smaller value than the original difference value.

According to instructions from the timing means 7, the calculation means 6 adds the output of the division means 5 to the output of the second holding means 3, and stores the calculation result. Therefore, the output of the arithmetic means is the result of sequentially adding difference values to the previous phase error signal, and increases by the difference value at each output timing.

The timing means 7 is reset by the reference signal, and then outputs a timing signal having a period of Tn to the calculation means 7. The calculation means 6 then repeats the operation of adding the output of the division means 5 to the value held by the calculation means and holding the result every time this timing signal is input. Further, the timing means 7 generates control signals to the first and second holding means based on the reference signal. With this control signal, the second holding means 3 holds the previous phase error signal held by the first holding means 2, and the first holding means 2 holds the phase error signal created this time. .

The operation at this time can be clearly understood by referring to FIG. As shown in Figure 2, the change in the phase error signal does not occur all at once;
By dividing the change width into equal parts during the generation period of the phase error signal, the change width when changing is reduced to 1/n.

FIG. 3 is a block diagram showing another embodiment. In the embodiment shown in FIG. 3, the procedure for creating the phase error signal to be output from the actually obtained phase error signal is simplified.

In FIG. 3, 10 is a phase error signal detection means, 11 is a multiplication means for multiplying the output of the phase error signal detection means by a coefficient α, 12 is an addition data storage register, and 13 is a predetermined constant k2 for the output of the register 12. 13 is a speed error detection means, 14 is a first constant means that multiplies the speed error signal by a constant k1, 15 is a gain-adjusted speed error signal and a processed, gain-adjusted phase. Adding means for adding error signals; reference numeral 16 is a buffer amplifier; and reference numeral 17 is a cylinder motor.

The speed error signal is obtained by measuring the cycle of the FG signal from the cylinder motor 17, detecting its rotational speed, obtaining a speed error, and outputting the speed error signal. In a normal configuration, this speed signal and the phase error signal as created are added together and supplied to the motor, but here, as in the first embodiment, the phase error signal is processed and then the speed error signal is It is added to the signal.

That is, the phase error signal generated at 1/30 second intervals is multiplied by a predetermined coefficient α. Here, α is a coefficient smaller than 1, and how to determine its value will be described later. The phase error signal multiplied by the coefficient α is
The FG of the cylinder motor is added to the addition data accumulation register 12.
Every time a signal is obtained, it is taken in and added up and stored. As a result, each time the FG signal is generated, the value obtained by multiplying the most recently created phase error signal by the coefficient α is stored in the register 12.
will be added to. In other words, the newly created phase error signal is corrected so that it changes by a factor α times the most recently created phase error signal. As a result, the variation width of the phase error signal can be suppressed compared to the conventional method.

The coefficient α is determined, for example, as follows. If the generation time interval of the phase error signal, that is, the reference signal period is Tr, and the generation period of the FG signal in a steady state is Tf, α is set equal to Tf/Tr. For example, if the steady state frequency of the FG signal is 720 hertz, α is 24. By increasing α to a certain extent in this way, it is possible to transmit almost the amount of change in the phase error signal until the next phase error signal is generated, although this is not strictly necessary. Note that since the phase error signal is a signal that takes positive and negative values, the output value of the addition data storage register may gradually decrease. In addition, since the phase error amount does not change suddenly but gradually changes stepwise, smooth phase pull-in without damping can be achieved. Further, the sequentially added values become zero when the phase error signal becomes zero even if they are sequentially added.

FIG. 4 is a waveform diagram showing the operation of this embodiment, and FIG. 5 is a flowchart of the gist when this second embodiment is implemented by a microcomputer. In the case of FIG. 4, for the sake of explanation, the frequency of the FG signal from the cylinder motor is divided by half, and the phase error signal is changed at this cycle. The period of the FG signal is also the reference signal period (RFSW pulse, signal indicating the rotational phase of the rotating head,
is set to 1/29th of the period (equal to the period of ). This is also a matter of convenience for drawing.

[0024] With microcomputer software,
When implementing a servo device such as a cylinder motor, interrupts are used as shown in FIG. That is, the program is created so as to execute operations such as creating a speed error signal at the timing of the FG signal of the cylinder motor. When the FG signal is input to the microcomputer, the cycle of the FG signal is measured at that timing, a speed error signal is calculated, gain correction is performed, and the value is held as the speed error signal. They are created and maintained at different times. A value PH0 obtained by multiplying the phase error signal by a coefficient α is added to the phase error accumulation value PHE to obtain a new phase error accumulation value PHE. Then, the newly created phase error accumulation value PHE is subjected to gain correction and held. Add with speed error signal. PWM data for an analog signal is created from the microcomputer based on the result after the addition, and the interrupt processing ends. Note that the phase error signal is created, for example, at the timing of the rise of the RFSW pulse, and the created value is held in a predetermined register.

In this way, with this method, the range of change in the phase error signal can be suppressed without complicating the configuration or program.

[0026]

[Effects of the Invention] As described above, according to the present invention, although the phase error signal itself is created at the same time intervals as in the past, the width of its change is suppressed, so there is a risk that the stability of the servo will be impaired. There is no. In addition, since it is created at the same time intervals as in the past, there is no problem in using it in a servo circuit using a microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment.

FIG. 2 is a waveform diagram showing the operation.

FIG. 3 is a block diagram of a second embodiment.

FIG. 4 is a waveform diagram showing the operation.

FIG. 5 is a flowchart when implemented by a microcomputer.

[Explanation of symbols]

1 Phase error signal creation means 2 First holding means 3 Second holding means 4 Difference calculation means 5. Division means 6 Timing means 10 Phase error signal detection means 11 Multiplication means 12 Addition data accumulation register 13 Speed error detection means 13 Second constant means 14 First constant means 15 Addition means 16 Buffer amplifier 17 Cylinder motor

Claims (2)

[Claims] Claim 1: A phase control circuit that performs phase control, comprising: a phase error signal generating means for generating a phase error signal at a predetermined period; and a phase error signal generating means for multiplying the generated phase error signal by a predetermined coefficient α of 1 or less and outputting the result. A phase control circuit comprising a multiplication means and an accumulation means for sequentially accumulating the output of the multiplication means at time intervals shorter than the predetermined period, the output of the accumulation means being used as a phase control signal. 2. A phase control circuit that performs phase control, comprising: phase error signal creation means for creating a phase error signal at a predetermined cycle; and difference calculation means for calculating the difference between the current phase error signal and the previous phase error signal. and dividing means for dividing the output of the difference calculation means by a predetermined count, and addition means for sequentially adding the output of the division means to the previous phase error signal at intervals shorter than the previous predetermined period, and the output of the addition means is A phase control circuit characterized in that it is used as a phase control signal.