JPH04296095A - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JPH04296095A
JPH04296095A JP6030591A JP6030591A JPH04296095A JP H04296095 A JPH04296095 A JP H04296095A JP 6030591 A JP6030591 A JP 6030591A JP 6030591 A JP6030591 A JP 6030591A JP H04296095 A JPH04296095 A JP H04296095A
Authority
JP
Japan
Prior art keywords
board
coaxial line
coaxial
pattern
line pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6030591A
Other languages
Japanese (ja)
Other versions
JP2500155B2 (en
Inventor
Kazuo Sato
和雄 佐藤
Katsuya Iguchi
井口 勝也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Telecom Networks Ltd
Original Assignee
Fujitsu Telecom Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Telecom Networks Ltd filed Critical Fujitsu Telecom Networks Ltd
Priority to JP3060305A priority Critical patent/JP2500155B2/en
Publication of JPH04296095A publication Critical patent/JPH04296095A/en
Application granted granted Critical
Publication of JP2500155B2 publication Critical patent/JP2500155B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To enable a coaxial circuit to be surely formed inside a circuit board at a low cost by a method wherein a first coaxial pattern and a second coaxial pattern are shielded by surrounding them with earth patterns of boards. CONSTITUTION:A first coaxial line pattern 33 is formed in line on a first coaxial board 31. An earth pattern 35 is formed on all both the sides of the first coaxial line pattern 33. A second coaxial line pattern 41 is formed in a second coaxial board 39 the same as the first coaxial line pattern 33, and an earth the pattern 35 is formed on both the sides of the first coaxial line pattern 41. An intermediate earth board 43 where the earth pattern 35 is formed is arranged between the first and the second coaxial board, 31 and 39. Outer earth boards 45 and 47 where an earth pattern is provided respectively are arranged outside the first and the second coaxial board, 31 and 39. The earth patterns 35 of the boards 31, 39, 45, and 47 are electrically connected together with a through- hole 37.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、多層回路基板に係わり
、特に、基板内に同軸回路を形成する同軸線パターンを
形成した多層回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board, and more particularly to a multilayer circuit board in which a coaxial line pattern forming a coaxial circuit is formed within the board.

【0002】0002

【従来の技術】従来、例えば、周波数帯域がGHz以上
の高周波帯域を扱う伝送機器では、例えば、図5に示す
ように、同軸線材を使用した同軸回路により、2つの入
力信号を、1つの出力信号に合体することが行われてい
る。すなわち、図5において、符号11はプリント基板
を示しており、このプリント基板11には、信号aを入
力する回路Aと、信号bを入力する回路Bとが形成され
ている。
2. Description of the Related Art Conventionally, in transmission equipment that handles high frequency bands of GHz or higher, for example, as shown in FIG. It is being combined into a signal. That is, in FIG. 5, reference numeral 11 indicates a printed circuit board, and this printed circuit board 11 is formed with a circuit A for inputting a signal a and a circuit B for inputting a signal b.

【0003】回路AとBとは、それぞれ、プリント基板
11に配置される入力端子13,接続端子15および同
軸線材17とを有しており、信号aおよびbは、プリン
ト基板11に配置される接続端子15および同軸線材1
7を介して出力端子19に伝送され、この出力端子19
において、図6に示すように、一つの出力信号に合体さ
れる。
Circuits A and B each have an input terminal 13, a connection terminal 15, and a coaxial wire 17 arranged on a printed circuit board 11, and signals a and b are arranged on the printed circuit board 11. Connection terminal 15 and coaxial wire 1
7 to the output terminal 19, and this output terminal 19
In the step shown in FIG. 6, the signals are combined into one output signal.

【0004】そして、このような同軸回路では、ノイズ
,漏話,損失等を考慮した場合には、回路Aと回路Bと
が、全くバランスの取れた実装配置であり、かつバラン
スの取れたパターンルートであることが要望される。
[0004] In such a coaxial circuit, when considering noise, crosstalk, loss, etc., circuit A and circuit B have a completely balanced mounting arrangement and a balanced pattern route. It is desired that

【0005】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の同軸回路では、高価な同軸線材17を使用し
ているため、製造コストが増大し、また、同軸線材17
の実装に比較的大きなスペースを必要とするため、高密
度実装には適していないという問題があった。本発明は
、かかる従来の問題を解決すべくなされたもので、同軸
回路を基板内に、安価,確実に形成することのできる多
層回路基板を提供することを目的とする。
[Problems to be Solved by the Invention] However, in such a conventional coaxial circuit, an expensive coaxial wire 17 is used, which increases manufacturing costs.
Since it requires a relatively large space for mounting, it is not suitable for high-density mounting. The present invention has been made to solve these conventional problems, and an object of the present invention is to provide a multilayer circuit board in which a coaxial circuit can be formed within the board at low cost and reliably.

【0006】[0006]

【課題を解決するための手段】本発明の多層回路基板は
、第1同軸線パターンの両側にアースパターンの形成さ
れる第1同軸線基板と、第2同軸線パターンの両側にア
ースパターンの形成される第2同軸線基板との間に、ア
ースパターンの形成される中間アース基板を配置すると
もに、前記第1同軸線基板および第2同軸線基板の外側
に、外側アース基板を配置し、さらに、前記各基板のア
ースパターンを、ビアホールにより電気的に導通してな
るものである。
[Means for Solving the Problems] The multilayer circuit board of the present invention includes a first coaxial line board on which ground patterns are formed on both sides of a first coaxial line pattern, and a ground pattern formed on both sides of a second coaxial line pattern. an intermediate grounding board on which a grounding pattern is formed is placed between the second coaxial line board and the second coaxial line board, and an outer grounding board is placed outside the first coaxial line board and the second coaxial line board; , the ground patterns of each of the substrates are electrically connected through via holes.

【0007】[0007]

【作用】本発明の多層回路基板では、第1同軸線パター
ンおよび第2同軸線パターンが、各基板のアースパター
ンにより囲繞され、シールドされる。
In the multilayer circuit board of the present invention, the first coaxial line pattern and the second coaxial line pattern are surrounded and shielded by the ground pattern of each board.

【0008】[0008]

【実施例】以下、本発明の詳細を図面に示す実施例につ
いて説明する。図1ないし図3は、本発明の多層回路基
板の一実施例を示しており、図において符号31は、第
1同軸線基板を示しており、この第1同軸線基板31に
は、直線状に第1同軸線パターン33が形成されている
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, details of the present invention will be explained with reference to embodiments shown in the drawings. 1 to 3 show an embodiment of the multilayer circuit board of the present invention. In the figures, reference numeral 31 indicates a first coaxial line board, and this first coaxial line board 31 includes a linear A first coaxial line pattern 33 is formed on.

【0009】この第1同軸線パターン33の両側には、
全面にアースパターン35が形成され、このアースパタ
ーン35の第1同軸線パターン33の両側となる位置に
は、第1同軸線パターン33に沿って、所定間隔を置い
て多数のビアホール37が形成されている。符号39は
、第2同軸線基板を示しており、この第2同軸線基板3
9は、第1同軸線基板31と全く同様に形成されている
On both sides of this first coaxial line pattern 33,
A ground pattern 35 is formed on the entire surface, and a large number of via holes 37 are formed at predetermined intervals along the first coaxial line pattern 33 at positions on both sides of the first coaxial line pattern 33 of this ground pattern 35. ing. Reference numeral 39 indicates a second coaxial line board, and this second coaxial line board 3
9 is formed in exactly the same way as the first coaxial line board 31.

【0010】すなわち、第2同軸線基板39には、第1
同軸線パターン33と全く同一に第2同軸線パターン4
1が形成され、この第2同軸線パターン41の両側にア
ースパターン35が形成され、さらに、第2同軸線パタ
ーン41の両側には、第1同軸線基板31と全く同様に
、ビアホール37が形成されている。第1同軸線基板3
1と第2同軸線基板39との間には、アースパターン3
5の形成される中間アース基板43が配置され、この中
間アース基板43には、第1同軸線基板31のビアホー
ル37に対応する位置に、ビアホール37が形成されて
いる。
That is, the second coaxial line board 39 has a first
The second coaxial line pattern 4 is exactly the same as the coaxial line pattern 33.
1 is formed, ground patterns 35 are formed on both sides of this second coaxial line pattern 41, and via holes 37 are formed on both sides of the second coaxial line pattern 41, just like the first coaxial line board 31. has been done. First coaxial line board 3
1 and the second coaxial line board 39, there is a ground pattern 3
A via hole 37 is formed in the intermediate ground substrate 43 at a position corresponding to the via hole 37 of the first coaxial line substrate 31.

【0011】第1同軸線基板31および第2同軸線基板
39の外側には、アースパターン35の形成される外側
アース基板45,47が配置され、これ等の外側アース
基板45,47には、第1同軸線基板31のビアホール
37に対応する位置に、ビアホール37が形成されてい
る。そして、各基板31,39,43,45,47のア
ースパターン35が、図2に示すように、ビアホール3
7により電気的に導通されている。
Outside the first coaxial line board 31 and the second coaxial line board 39, outer grounding boards 45 and 47 on which the grounding pattern 35 is formed are disposed, and these outer grounding boards 45 and 47 have the following features: A via hole 37 is formed at a position corresponding to the via hole 37 of the first coaxial line board 31. Then, as shown in FIG.
It is electrically connected by 7.

【0012】すなわち、各基板31,39,43,45
,47の両面には、アースパターン35が、図2に示す
ように形成され、各アースパターン35が、ビアホール
37内に形成される環状銅箔パターン49により連結さ
れている。なお、図3は、多層回路基板を上面から見た
概略を示すもので、図3において符号51は多層回路基
板を、符号53はコネクタを示しており、第1同軸線パ
ターン33および第2同軸線パターン41は、多層回路
基板51内において所定の入力部および出力部に内層結
線されている。
That is, each substrate 31, 39, 43, 45
, 47 are formed with ground patterns 35 as shown in FIG. In addition, FIG. 3 shows an outline of the multilayer circuit board viewed from the top. In FIG. The line pattern 41 is internally connected to predetermined input and output sections within the multilayer circuit board 51 .

【0013】図4は、第1同軸線パターン33,第2同
軸線パターン41等により形成される同軸回路の詳細を
示すもので、外側アース基板45の上面から中間アース
基板43の中央までの間隔、および、外側アース基板4
7の下面から中間アース基板43の中央までの間隔が、
それぞれLとされている。また、第1同軸線パターン3
3および第2同軸線パターン41の肉厚が、それぞれd
とされ、さらに、外側アース基板45の下面と第1同軸
線基板31の上面との間隔、および、中間アース基板4
3の下面と第2同軸線基板39の上面との間隔が、それ
ぞれDとされている。
FIG. 4 shows details of the coaxial circuit formed by the first coaxial line pattern 33, the second coaxial line pattern 41, etc., and shows the distance from the top surface of the outer ground board 45 to the center of the intermediate ground board 43. , and outer ground board 4
The distance from the bottom surface of 7 to the center of the intermediate ground board 43 is
Each is rated L. In addition, the first coaxial line pattern 3
3 and the second coaxial line pattern 41 are respectively d.
Furthermore, the distance between the lower surface of the outer ground board 45 and the upper surface of the first coaxial line board 31, and the interval between the lower surface of the outer ground board 45 and the upper surface of the first coaxial line board 31,
The distance between the lower surface of 3 and the upper surface of the second coaxial line board 39 is D, respectively.

【0014】このような同軸回路では、インピーダンス
Z0 (オーム)は、以下の近似式により求めることが
できる。 Z0 =〔138/(εr )1/2 〕・log 1
0・{(D+1.5d)/K1 d} ここで、εrは比誘電率、K1 は内部導体実効径係数
、dおよびDは図4に示した寸法である。
In such a coaxial circuit, the impedance Z0 (ohm) can be determined by the following approximate equation. Z0 = [138/(εr)1/2]・log 1
0.{(D+1.5d)/K1 d} Here, εr is the relative dielectric constant, K1 is the internal conductor effective diameter coefficient, and d and D are the dimensions shown in FIG. 4.

【0015】しかして、以上のように構成された多層回
路基板では、第1同軸線パターン33の両側にアースパ
ターン35の形成される第1同軸線基板31と、第2同
軸線パターン41の両側にアースパターン35の形成さ
れる第2同軸線基板39との間に、アースパターン35
の形成される中間アース基板43を配置するともに、第
1同軸線基板31および第2同軸線基板39の外側に、
外側アース基板45,47を配置し、さらに、各基板3
1,39,43,45,47のアースパターン35を、
ビアホール37により電気的に導通したので、同軸回路
を基板内に、安価,確実に形成することができる。
In the multilayer circuit board configured as described above, the first coaxial line board 31 has the ground patterns 35 formed on both sides of the first coaxial line pattern 33, and the ground patterns 35 are formed on both sides of the second coaxial line pattern 41. The ground pattern 35 is connected between the ground pattern 35 and the second coaxial line board 39 on which the ground pattern 35 is formed.
An intermediate grounding board 43 is disposed on the outside of the first coaxial line board 31 and the second coaxial line board 39,
The outer ground boards 45 and 47 are arranged, and each board 3
1, 39, 43, 45, 47 earth patterns 35,
Since electrical continuity is achieved through the via hole 37, a coaxial circuit can be formed within the substrate at low cost and reliably.

【0016】すなわち、以上のように構成された多層回
路基板では、同軸回路を、従来のように高価な同軸線材
を使用することなく、第1同軸線パターン33および第
2同軸線パターン41により形成したので、非常に安価
なものとなる。また、第1同軸線パターン33および第
2同軸線パターン41が、各基板31,39,43,4
5,47のアースパターン35により囲繞され、確実に
シールドされるため、ノイズ,漏話,損失等の安定した
同軸回路となる。
That is, in the multilayer circuit board configured as described above, the coaxial circuit is formed by the first coaxial line pattern 33 and the second coaxial line pattern 41 without using expensive coaxial wires as in the conventional case. Therefore, it is very cheap. Further, the first coaxial line pattern 33 and the second coaxial line pattern 41 are arranged on each substrate 31, 39, 43, 4.
Since it is surrounded by the ground patterns 35 of No. 5 and 47 and is reliably shielded, it becomes a stable coaxial circuit with no noise, crosstalk, loss, etc.

【0017】さらに、第1同軸線パターン33により形
成される回路と、第2同軸線パターン41により形成さ
れる回路とを、全くバランスの取れた実装配置とし、か
つバランスの取れたパターンルートにすることが容易に
可能となる。さらに、また、同軸回路が多層回路基板内
に形成されるため、特別な実装スペースが不要となり、
高密度実装に非常に適したものとなる。
Furthermore, the circuit formed by the first coaxial line pattern 33 and the circuit formed by the second coaxial line pattern 41 are arranged in a completely balanced manner, and the pattern route is also balanced. This becomes possible easily. Furthermore, since the coaxial circuit is formed within the multilayer circuit board, no special mounting space is required.
This makes it extremely suitable for high-density packaging.

【0018】また、以上のように構成された多層回路基
板では、第1同軸線パターン33および第2同軸線パタ
ーン41の肉厚d、および、前述した間隔Dを変化する
ことにより、前述した式に基づいてインピーダンスを容
易に決定することが可能となる。
Furthermore, in the multilayer circuit board constructed as described above, by changing the thickness d of the first coaxial line pattern 33 and the second coaxial line pattern 41 and the above-mentioned interval D, the above-mentioned formula can be satisfied. It becomes possible to easily determine impedance based on .

【0019】[0019]

【発明の効果】以上述べたように、本発明の多層回路基
板では、第1同軸線パターンの両側にアースパターンの
形成される第1同軸線基板と、第2同軸線パターンの両
側にアースパターンの形成される第2同軸線基板との間
に、アースパターンの形成される中間アース基板を配置
するともに、第1同軸線基板および第2同軸線基板の外
側に、外側アース基板を配置し、さらに、各基板のアー
スパターンを、ビアホールにより電気的に導通したので
、同軸回路を基板内に、安価,確実に形成することがで
きるという利点がある。
As described above, in the multilayer circuit board of the present invention, the first coaxial line board has the ground pattern formed on both sides of the first coaxial line pattern, and the ground pattern is formed on both sides of the second coaxial line pattern. An intermediate grounding board on which a grounding pattern is formed is placed between a second coaxial line board on which a ground pattern is formed, and an outer grounding board is placed on the outside of the first coaxial line board and the second coaxial line board, Furthermore, since the ground patterns of each board are electrically connected through the via holes, there is an advantage that a coaxial circuit can be formed within the board at low cost and reliably.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の多層回路基板の一実施例を示す分解斜
視図である。
FIG. 1 is an exploded perspective view showing an embodiment of a multilayer circuit board of the present invention.

【図2】図1のII−II線に沿う断面図である。FIG. 2 is a sectional view taken along line II-II in FIG. 1;

【図3】図1の多層回路基板を概略的に示す上面図であ
る。
FIG. 3 is a top view schematically showing the multilayer circuit board of FIG. 1;

【図4】図2の同軸回路の詳細を示す断面図である。FIG. 4 is a cross-sectional view showing details of the coaxial circuit of FIG. 2;

【図5】従来の同軸回路の形成されるプリント基板を示
す斜視図である。
FIG. 5 is a perspective view showing a printed circuit board on which a conventional coaxial circuit is formed.

【図6】図5の同軸回路による信号の合成を示す説明図
である。
FIG. 6 is an explanatory diagram showing signal synthesis by the coaxial circuit of FIG. 5;

【符号の説明】[Explanation of symbols]

31  第1同軸線基板 33  第1同軸線パターン 35  アースパターン 37  ビアホール 39  第2同軸線基板 41  第2同軸線パターン 43  中間アース基板 45,47  外側アース基板 31 First coaxial line board 33 First coaxial line pattern 35 Earth pattern 37 Beer hall 39 Second coaxial line board 41 Second coaxial line pattern 43 Intermediate ground board 45, 47 Outer ground board

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  第1同軸線パターンの両側にアースパ
ターンの形成される第1同軸線基板と、第2同軸線パタ
ーンの両側にアースパターンの形成される第2同軸線基
板との間に、アースパターンの形成される中間アース基
板を配置するともに、前記第1同軸線基板および第2同
軸線基板の外側に、外側アース基板を配置し、さらに、
前記各基板のアースパターンを、ビアホールにより電気
的に導通してなることを特徴とする多層回路基板。
Claim: 1. Between a first coaxial line substrate in which ground patterns are formed on both sides of a first coaxial line pattern, and a second coaxial line board in which ground patterns are formed on both sides of a second coaxial line pattern, An intermediate grounding board on which a grounding pattern is formed is arranged, and an outer grounding board is arranged outside the first coaxial line board and the second coaxial line board, and further,
A multilayer circuit board characterized in that the ground patterns of each board are electrically connected through via holes.
JP3060305A 1991-03-25 1991-03-25 Multilayer circuit board Expired - Fee Related JP2500155B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3060305A JP2500155B2 (en) 1991-03-25 1991-03-25 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3060305A JP2500155B2 (en) 1991-03-25 1991-03-25 Multilayer circuit board

Publications (2)

Publication Number Publication Date
JPH04296095A true JPH04296095A (en) 1992-10-20
JP2500155B2 JP2500155B2 (en) 1996-05-29

Family

ID=13138318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3060305A Expired - Fee Related JP2500155B2 (en) 1991-03-25 1991-03-25 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JP2500155B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013175774A (en) * 2007-03-23 2013-09-05 Huawei Technologies Co Ltd Printed circuit board, formation method thereof, and mainboard of terminal product
US8723047B2 (en) 2007-03-23 2014-05-13 Huawei Technologies Co., Ltd. Printed circuit board, design method thereof and mainboard of terminal product
CN108093558A (en) * 2017-12-14 2018-05-29 郑州云海信息技术有限公司 A kind of motherboard design method for reducing radiation effect

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01143403A (en) * 1987-11-30 1989-06-06 Nec Corp Delay line
JPH04246901A (en) * 1991-01-31 1992-09-02 Tdk Corp High frequency filter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01143403A (en) * 1987-11-30 1989-06-06 Nec Corp Delay line
JPH04246901A (en) * 1991-01-31 1992-09-02 Tdk Corp High frequency filter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013175774A (en) * 2007-03-23 2013-09-05 Huawei Technologies Co Ltd Printed circuit board, formation method thereof, and mainboard of terminal product
US8723047B2 (en) 2007-03-23 2014-05-13 Huawei Technologies Co., Ltd. Printed circuit board, design method thereof and mainboard of terminal product
US9519308B2 (en) 2007-03-23 2016-12-13 Huawei Technologies Co., Ltd. Printed circuit board, design method thereof and mainboard of terminal product
CN108093558A (en) * 2017-12-14 2018-05-29 郑州云海信息技术有限公司 A kind of motherboard design method for reducing radiation effect

Also Published As

Publication number Publication date
JP2500155B2 (en) 1996-05-29

Similar Documents

Publication Publication Date Title
US4673904A (en) Micro-coaxial substrate
US6294965B1 (en) Stripline balun
EP0069102B1 (en) Impedance matching stripline transition for microwave signals
US4739453A (en) Shielding apparatus for a printed circuit board
US7518884B2 (en) Tailoring impedances of conductive traces in a circuit board
US5552752A (en) Microwave vertical interconnect through circuit with compressible conductor
US20100182105A1 (en) Impedance-controlled coplanar waveguide system for the three-dimensional distribution of high-bandwidth signals
US4891616A (en) Parallel planar signal transmission system
US6949992B2 (en) System and method of providing highly isolated radio frequency interconnections
US6165018A (en) Connector having internal crosstalk compensation
US5083236A (en) Inductor structure with integral components
US6674645B2 (en) High frequency signal switching unit
JP2000512110A (en) Printed circuit board with integrated lateral microwave coupler
JPH09199818A (en) Inter-ground connection structure
JPH0294693A (en) Printed wiring board having coaxial through-hole
US4672312A (en) Giga-hertz test jig
JPH08242078A (en) Printed board
US4825155A (en) X-band logic test jig
US4906957A (en) Electrical circuit interconnect system
JPH04296095A (en) Multilayer circuit board
US5309121A (en) Signal transfer line having a din connector
CN112770493B (en) Flexible circuit board and electronic equipment
CN211702518U (en) Circuit board structure
KR100852003B1 (en) Ground structure using via-holes on pcb and circuit device having the ground structure
JP2004259959A (en) Wiring board

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090301

Year of fee payment: 13

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090301

Year of fee payment: 13

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100301

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110301

Year of fee payment: 15

LAPS Cancellation because of no payment of annual fees