JPH0429413A - A/d converter - Google Patents

Abstract

PURPOSE:To dispense with an additional circuit such as a conventional subtracter or amplifier, etc., and to reduce a storage error by directly obtaining the reference potential of a second A/D converter from the output of a sample holding circuit, and setting the output potential of the sample holding circuit at the upper limiting value of the reference potential. CONSTITUTION:To directly obtain the reference potential of the second A/D converter 7 from the output of the sample holding circuit 2, a node N24 is connected to the output terminal of the sample holding circuit 2, and the potential of the node N24 that is the upper limiting value of the reference potential is set as the output potential Va, and a current source 8 is connected to a node N20, and the current value of the power source 8 is set so as to set potential difference between the nodes N24 and N20 equal to the minimum bit unit of a first A/D converter 3, and the output potential Vb of an A/D converter 4 is compared with the potential of nodes N21, N22, and N23, that is the reference potential, respectively. In such a way, it is possible to dispense with the additional circuit such as the conventional subtracter or amplifier, etc., and to reduce the storage error.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides an A converter for converting an analog signal into a digital signal.
/D conversion device.

[Conventional technology]

FIG. 4 shows a wiring diagram of a serial-parallel type A/D converter, for example, IEEE Journal or Solid-8ta.
te C1rcuits, vol, 24. No, 1.
pp13-20. Feb, 1989 or Japanese Patent Application Publication No. 1986-
This is described in Japanese Patent No. 57824.

The apparatus shown in FIG. 4 will be explained below, but for simplicity, the apparatus shown in FIG. The following explanation assumes that the second A/D converter forms upper 2 bits and lower 2 bits, respectively, and converts an analog signal into a 4-bit digital signal.

As shown in FIG. 4, when an analog signal is input to the sample and hold circuit 2 via the node 1, the analog signal is sampled and held by the sample and hold circuit 2, and the output potential V of the sample and hold circuit 2 becomes the first
The first A/D converter 3 compares the output potential of the sample and hold circuit 2 with the reference potential, and the comparison result is input to the first A/D converter 3. The encoder 30 converts it into 2-bit digital data D1.

Then, the output data D1 of the encoder 30 is converted into an analog signal by the D/A converter 4, and the output potential V of the sample hold circuit 2 and the output potential V of the D/A converter 4 are
, the conversion error v8 is derived by the subtracter 5, and the derived conversion error V is amplified by the amplifier 6 so as to match the input range (dynamic range) of the second A/D converter 7. .

Next, the output potential ■ of the amplifier 6 is input to the second A/D converter 7, and the second A/D converter 7 converts the output potential
The output transition V and the reference potential are compared, and the comparison result is converted into 2-bit digital data D2 by the encoder 70 of the second A/D converter 7, and the input analog signal to the node 1 is converted into 2-bit digital data D2. It is converted into a 4-bit digital signal consisting of the digital data D1 and the lower 2 bits of digital data D2.

By the way, No. 1. To explain the configuration of the second A/D converters 3, 7, first, the first A/D converter 3 includes the aforementioned encoder 30 and three comparators 31, 32 .
33, and when the upper limit potential of the dynamic range of the first A/D converter 3 is VR" and the lower limit potential is VR,
By a series circuit of four voltage dividing resistors 34, 35, 36, and 37, the potential VlO of the node NN at both ends of this series circuit
° 14 The difference between R and VR+ is equally divided, and the nodes N and NN, which are the connection points of each resistor 34 to 37, are respectively 1112° 13 11 12” 13, and the potentials V and V 32.33 of each comparator 31° are Each comparator 31 to 33 compares the output potential V of the sample and hold circuit 2 with each reference potential VVV a 11° 12' 13, and the reference potential becomes the output potential V.

If the reference potential is lower than the output potential V, the output of each comparator 31-33 will be a high potential (logic 1), and if the reference potential is lower than the output potential V, the output of each comparator 31-33 will be a low potential (logic 0).

On the other hand, like the first A/D converter 3, the second A/D converter 7 also has three comparators 71, 72, and 73 in addition to the encoder 70 described above, and has four partial voltages. Resistance 74,7
By the series circuit of 5, 76, and 77, the difference between the potentials VR and VR+ of the nodes N and N at both ends of this series circuit is divided equally, and the difference between the potentials VR and VR+ of the nodes N and N at both ends of this series circuit is divided equally, and
, N2■22 23 are given to each comparator 71.7273 as a reference potential V, V, V, and each comparator 71 to 73 determines the output potential V of the amplifier 6.
and each reference potential V , V , V respectively c
21, 22, and 23 are compared, and if the reference potential is higher than the output potential V, each comparator 71~
The output of the comparator 73 becomes a high potential (logic 1), and if the reference type level is lower than the output potential V 1 , the output potential of each of the comparators 71 to 73 becomes a low potential (logic 0).

Thus, both A/D converters in the conventional device 3.7
The dynamic ranges of both are set to be equal, and both reference potentials are applied externally regardless of the input analog signal.

By the way, the output data D1 of the encoder 30 of the first A/D converter 3 is determined by the output of each comparator 31 to 33, and when VR≦v<V■1, each comparator 3
All the outputs of 1 to 33 become logic 1, and the bit content of data D1 becomes "00". When V11≦V and <V12, only the output of comparator 31 becomes logic 0, and the bit content of data D1 becomes "00". 01°, v12≦V, <
■At 13, the outputs of comparators 31 and 32 are logic 0, and the output of comparator 33 is logic 1, and data D1
The bit content becomes “10”, and v13≦V.

<VR+, the outputs of the comparators 31 to 33 all become logic 0, and the bit content of data D1 becomes “11°”.
becomes.

Furthermore, the output data D2 of the encoder 70 of the second A/D converter 7 is determined in the same manner, and the bit contents of the data D2 are -oo'', v,, l≦ when VR≦V<■21.
"01" when Vo<V22;"10' when V22≦Vo<v23; ■23≦V.

<When VR+, it becomes 11°.

Next, the operation of the apparatus shown in FIG. 4 will be explained using specific numerical values.

Now, set the dynamic range of both A/D converters 3.7 to 0.
~2V, the potential of each node N-N, N20=N24, which is the reference potential in both A/D converters 3.7, is shown on the vernier in FIG.
N, N N N10' 11 12'
Potential of 13'14 v10"11"12"13"1
4" OV, 0.5V, 1.5V, respectively as shown in FIG.
OV, 1.5V, 2. OV, nodes N, N2
1・N22・N23・N24 ′l potential” ・ゞ
・ゞ ・V and V are also false tLOV, 0.
5V, 1°0V, 1.5V, 2. OV and Tiru.

Then, if the output potential V, of the sample and hold circuit 2 is, for example, 1.4V, each comparator 31 to 33 of the first A/D converter 3 outputs the output potential V, (-1
, 4V) and each reference potential of nodes N1, -N13 are compared, and as shown in FIG.
potential V1, (-a 11'
120°5V), V12 (-1,0V) (7)L
' Since this is higher than the deviation, only the output of the comparator 33 becomes logic 1, and the bit content of the output data D1 of the encoder 4 becomes "10".

At this time, the D/A converter 4 outputs an analog value according to the bit content of the output data D1 of the encoder 30, and the bit content of the output data D1 is "00° "01" 10
When "11", the output potential Vb of the D/A converter 4 is Ov.

0.5V, 1. OV becomes 1.5V.

Therefore, as mentioned above, the bit content of the output data D1 is “
10'', the output potential V of the encoder 30 is 1.
It becomes Ov.

Next, the subtracter 5 calculates a conversion error Ve (-0,4V) between the output potential V (-1,4V) of the sample and hold circuit 2 and the output potential V, (-1,0V) of the D/A converter 4. )
is derived, the conversion error V is multiplied by a predetermined value by the amplifier 6, and the output potential V becomes the e-th
C2
The signal is input to the A/D converter 7 of.

By the way, No. 1. Since the second A/D converters 3.7 each form the upper 2 bits and lower 2 bits of 4-bit digital data, the minimum bit unit of the first A/D converter 3, that is, the first 1 of the dynamic range of the A/D converter 3. /4 corresponds to the full dynamic range of the second A/D converter 7, and the conversion error ■, which is a value within 1/4 of the dynamic range of the first A/D converter 3, is In order to match the full dynamic range of the A/D converter 7, the conversion error (2) is multiplied by 4 by the amplifier 6.

Therefore, the output potential V of 1.6v is obtained by multiplying the conversion error of 0.14v by 4 by the amplifier 6. is input to the second A/D converter 7, and the comparators 71 to 71 of the second A/D converter 7
73, the output potential Vc (-1, 6V) and the node N2
, ~N23 are compared with each other, and as shown in FIG. 5, an output potential V is obtained. is the potential v2 of node N −N, (
-0,5V)v (II-1,OV),v23(-1,
5v), each comparator 71~
All the outputs of 73 become logic 0, and the bit content of the output data D2 of the encoder 70 becomes "111." In this way, the analog signal with an input potential of 1.4 V is divided into the upper two bits of "10'" and "11". "1" consisting of the lower 2 bits
It is converted into a 4-bit digital signal with bit content of 011''.

[Problem to be solved by the invention]

In the conventional case, 1. In addition to the second A/D converter 3.7, a D/A converter 4. Subtractor 5. Since a large number of additional circuits such as the amplifier 6 are required, operational errors due to variations in the characteristics of the transistors that make up these circuits, variations in resistance, etc. are accumulated, and this accumulated error causes a decrease in the accuracy of digital conversion. Invitation, especially the first one. Second A/D converter 3
．． There is a problem in that when the resolution of 7 is increased, the accumulation of operational errors of the additional circuit increases, and the accuracy of digital conversion becomes noticeably lowered.

This invention was made in order to solve the above-mentioned problems. It is an object of the present invention to reduce the number of additional circuits other than the second A/D converter compared to conventional ones, and to prevent a decrease in accuracy of digital conversion.

[Means to solve the problem]

The A/D converter of the present invention uses the first and second A/D converters to convert the analog signal into an A/D converter based on a comparison result between an output potential of a sample and hold circuit that samples and holds the analog signal and a reference potential. /D conversion, the first A/D converter forms upper bits of the digital converted value, and the second A/D converter forms lower bits of the digital converted value. , said second
The reference potential of the A/D converter is obtained directly from the output of the sample and hold circuit, and the output potential of the sample and hold circuit is set to the upper limit value of the reference potential.

[Effect]

In this invention, the reference potential of the second A/D converter is obtained directly from the output of the sample-and-hold circuit, and the output potential of the sample-and-hold circuit is set to the upper limit of the reference potential. Additional circuits such as amplifiers are not required, cumulative errors can be reduced, and deterioration in digital conversion accuracy can be prevented.

〔Example〕

FIG. 1 shows a wiring diagram of an embodiment of an A/D converter according to the present invention.

1 differs from FIG. 4 in that the subtracter 5 and amplifier 6 in FIG. 4 are deleted, and the reference potential of the second A/D converter 7 is obtained directly from the output of the sample-and-hold circuit 2. In order to
4 is the output potential V, and a current source 8 is connected to node N2o.
are connected, and the potential difference between nodes N and N is the first A
/D converter 3 minimum bit unit, that is, equal to 1/4 of the dynamic range of the first A/D converter 3,
The current value of the current source 8 is set, and the output potential V of the D/A converter 4 and each node N, which is a reference potential, is set.
The potentials of 21, 22, and 23 are compared by each of the comparators 71 to 73.

Therefore, each node N24°N of the second A/D converter 7
, N, N, and N are respectively V.

23 22 21 20
aV, -0,125V, V, -0,25V, V.

0.375V, V -0.5V.

Next, the operation will be explained.

Now, as in the case of FIG.
The operation of the D converter 3 is the same as that shown in FIG.
．． It is converted to an analog value of Ov.

On the other hand, each node N24N of the second A/D converter 7,
The potentials of N, N, and N are 1°4V, respectively.
The voltage becomes 1.275V, 1.15V, 1.025VO09V, and this is shown on the vernier in Figure 2.
As shown in FIG. 2, the output potential Vb of the D/A converter 4
(-1, OV) is lower than the potential of node N21,
The outputs of comparators 71-73 are all logic 1.

By the way, as can be seen by comparing FIG. 2 and FIG. 5, the relationship between each reference potential and the potential to be compared with these in the case of FIG. 2 is different from that in FIG. Due to the internal configuration of , the relationships between each reference potential and the potential to be compared with these are substantially the same as in the case of FIG. 5, and as a result, the logic 1 of each comparator 71 to 73 The output is encoded by the encoder 70, and data D2 with bit content “11°” is output from the encoder 70.

Therefore, the analog signal with an input potential of 1.4V or “10”
The signal is converted into a 4-bit digital signal with a bit content of 1011 degrees, consisting of the upper 2 bits of 11 degrees and the lower 2 bits of 11 degrees, and the same result as before is obtained. This eliminates the need for additional circuits such as amplifiers, reduces cumulative errors, prevents deterioration in digital conversion accuracy, and enables higher-speed operation than in the past.

FIG. 3 shows a wiring diagram of another embodiment of the present invention. In the diagram, the difference from FIG. 1 is that the D/A in FIG.
Converter 4 is deleted and each node N of the first A/D converter 3
Connect one end of the switches 90, 91, 92, and 93 to N, N, and N, respectively.
The other ends of these switches 90 to 93 are connected to the input terminals of each of the comparators 70 to 73 of the second A/D converter 7,
Among the switches 90 to 93, the switch corresponding to the output data D1 of the encoder 30 is turned on by a control unit not shown, and the node N1o=N13 is transmitted through the turned-on switch.
One of these potentials is input to the second A/D converter 7.

At this time, when the bit contents of the output data D1 of the encoder 30 are "00", "01", "10#"11",
Switches 90, 91, 92 and 93 are each set to be turned on.

As in the case of FIG. 1, if the dynamic range of the first A/D converter 3 is O~2V and the output potential V of the sample and hold circuit 2 is 1.4V, then the output data D1 of the encoder 30 is The bit content becomes "10", and only the switch 92 is turned on, and the potential of the node N12 (-
1, OV) is input to the second A/D converter 7 as a potential to be compared, and the encoder 70 of the second A/D converter 7
, output data D2 with bit content of "11" is output, and the same effect as in the case of FIG. 1 can be obtained.

In the above embodiment, the width of the reference potential of the second A/D converter 7 is set to 1/4 of the dynamic range of the first A/D converter 3, but in particular, the width of the reference potential of the second A/D converter 7 is Needless to say, it is not limited to.

Furthermore, the method of inputting the potential to be compared with the reference potential in the second A/D converter 7 is as described above.
The method is not limited to the method of inputting the information from the input terminal or the method of inputting the information via the switches 90 to 93.

〔Effect of the invention〕

As described above, according to the A/D converter of the present invention, the reference potential of the second A/D converter is obtained directly from the output of the sample and hold circuit, and the output potential of the sample and hold circuit is obtained from the reference potential of the second A/D converter. By setting the upper limit value, additional circuits such as conventional subtracters and amplifiers are no longer required, making it possible to reduce cumulative errors and preventing a decline in digital conversion accuracy, resulting in faster operation than before. This makes it possible to provide an A/D conversion device with excellent operating characteristics.

[Brief explanation of the drawing]

Fig. 1 is a wiring diagram of one embodiment of the A/D conversion device of the present invention, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a wiring diagram of another embodiment of the invention, and Fig. 4. 5 is a wiring diagram of a conventional A/D converter, and FIG. 5 is an explanatory diagram of the operation of FIG. 4. In the figure, 2 is the sample hold circuit, 3 is the ml A
/D converter 7 is a second A/D converter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) The analog signal is A/D converted by the first and second A/D converters based on the comparison result between the output potential of the sample and hold circuit that samples and holds the analog signal and the reference potential, and The first A/D converter forms the upper bits of the digital conversion value, and the second A/D converter forms the lower bits of the digital conversion value.
In the D conversion device, the reference potential of the second A/D converter is obtained directly from the output of the sample and hold circuit, and the output potential of the sample and hold circuit is set to an upper limit value of the reference potential. A/D conversion device.