JPH0429250B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to level shifting circuits, and particularly to high voltage level shifting circuits.

[Conventional technology]

High-voltage integrated circuits that control high-voltage output using low-voltage control circuits are important for driving displays and printers. Among them, those whose output circuit is in CMOS format are high-speed and
It is expected to have low power consumption and is particularly promising.

FIG. 3 shows an example in which a high voltage CMOS flip-flop level shift circuit controls a high voltage CMOS output circuit. This high voltage
The CMOS circuit consists of a high voltage level shift circuit 15 and a high voltage CMOS output circuit 2, and is provided with a control signal input terminal 3 and an inverted control signal input terminal 4.
Further, 11 is a positive high voltage application terminal, and 12 is a reference potential application terminal. High voltage level shift circuit 15
are high voltage PMOS transistors 5 and 6 and high voltage
Consisting of NMOS transistors 7 and 8, the third
As shown in the figure, a high voltage CMOS flip-flop is formed. High voltage CMOS output circuit 2
is a high-voltage PMOS transistor 9 and a high-voltage
This is a high voltage inverter composed of an NMOS transistor 10. The control signal is applied to the gates of the high voltage NMOS transistor 8 and the high voltage NMOS transistor 10 via the control signal input terminal 3. The inverted control signal is applied to the gate of the high voltage NMOS transistor 7 via the inverted control signal input terminal 4. The level-shifted control signal is taken out from the drain of the high voltage PMOS transistor 5 and applied to the gate of the high voltage PMOS transistor 9.

[Problem that the invention seeks to solve]

However, in the case of the above-mentioned level shift circuit using the conventional MOS transistor, there is a disadvantage that the MOS transistor characteristics deteriorate due to the injection effect of hot carriers, and this problem is particularly serious in a high voltage level shift circuit.

That is, the high voltage level shift circuit 1 in FIG.
5, high voltage PMOS transistor 5,
A signal that swings between a reference potential and a high voltage is applied to gates 6 and 9. For example, if 200V is applied to the high voltage application terminal and the reference potential is 0V, the gates of the high voltage PMOS transistors 5, 6, and 9 will be
A signal with an amplitude of 200V will be added. Therefore,
The gate oxide film thicknesses of the high voltage PMOS transistors 5, 6, and 9 are designed to withstand high amplitude voltages, compared to the gate oxide film thicknesses of the high voltage NMOS transistors 7, 8, and 10 to which low voltage control signals are applied. It is necessary to make it thicker. However, increasing the thickness of the gate oxide film not only complicates the manufacturing process of the transistor but also increases the threshold voltage. Furthermore, the transition region where the transistor changes from off to on increases, and the on/off characteristics deteriorate. Therefore, the thickness of the gate oxide film cannot be increased unnecessarily.
Therefore, the electric field induced by the gate of the transistor is larger than the electric field induced by the gate of a transistor used in a low voltage circuit. It is known that when a MOS transistor is operated for a long time under a high gate electric field, hot carriers are injected into the gate oxide film, causing a change in threshold voltage and a decrease in carrier mobility. Third
In the high voltage level shift circuit 15 shown in the figure, the deterioration of the MOS transistor characteristics due to the hot carrier injection effect is caused by the high voltage PMOS transistors 5, 6,
Occurs at 9.

The present invention solves the above-mentioned problems, makes it possible to arbitrarily select the signal level after level shift, eliminates deterioration of transistor characteristics due to hot carrier injection effect, and has a high breakdown voltage with a thin gate oxide film thickness.
The present invention aims to provide a level shift circuit that can use MOS transistors.

[Means for solving problems]

The level shift circuit of the first invention includes a first PMOS transistor, a second NMOS transistor whose own drain is connected to the drain of the first PMOS transistor, and a second NMOS transistor whose own drain is connected to the drain of the first PMOS transistor. A third PMOS transistor is connected to the source of the third PMOS transistor to which a positive power supply voltage is applied, and the drain of the third PMOS transistor is connected to the drain of the third PMOS transistor,
a fourth NMOS transistor to which the source of the transistor and its source are connected and a reference potential is applied; the anode is connected to the drain of the third PMOS transistor, and the cathode is connected to the gate of the first PMOS transistor. a first resistor having one end connected to the cathode of the first Zener diode and the other end connected to the source of the first PMOS transistor; an anode connected to the first PMOS transistor; a second Zener diode whose cathode is connected to the drain of the transistor and the gate of the third PMOS transistor; one end is connected to the cathode of the second Zener diode and the other end is connected to the source of the third PMOS transistor. a second resistor connected to each of the transistors, a signal is input to the gate of the second NMOS transistor, an inverted signal is input to the gate of the fourth NMOS transistor, and a second resistor is connected to the first Zener diode. A signal is output from at least one of the cathode of the second Zener diode and the second Zener diode.

The level shift circuit of the second invention includes a first PMOS transistor, a second NMOS transistor whose own drain is connected to the drain of the first PMOS transistor, and a second NMOS transistor whose own drain is connected to the drain of the first PMOS transistor. A third PMOS transistor is connected to the source of the third PMOS transistor and a reference potential is applied thereto, and the drain of the third PMOS transistor is connected to the drain of the third PMOS transistor,
a fourth NMOS transistor to which the source of the transistor and its own source are connected and a negative power supply voltage is applied; a cathode is connected to the drain of the fourth NMOS transistor, and an anode is connected to the gate of the second PMOS transistor. a first Zener diode connected to each other; a first resistor having one end connected to the anode of the first Zener diode and the other end connected to the source of the second NMOS transistor; and a cathode connected to the second NMOS transistor. a second Zener diode whose anode is connected to the drain of the NMOS transistor, and whose anode is connected to the gate of the fourth NMOS transistor; one end is connected to the anode of the second Zener diode, and the other end is connected to the fourth NMOS transistor. and a second resistor connected to the sources of the first Zener transistor, inputs a signal to the gate of the first PMOS transistor, inputs an inverted signal to the gate of the third PMOS transistor, and inputs a signal to the gate of the first Zener transistor. It is characterized in that a signal is output from at least one of the anode of the diode and the second Zener diode.

[Effect]

The first invention is a level shift circuit that includes first and second Zener diodes and first and second resistors. In the first invention, the second Zener diode has its anode connected to the first
The cathode of the drain of the PMOS transistor is connected to one end of a second resistor, and the other end of the second resistor is connected to the source of the first PMOS transistor.
The first Zener diode has its anode connected to the drain of the third PMOS transistor, its cathode connected to one end of the first resistor, and the other end of the first resistor connected to the source of the third PMOS transistor.

This level shift circuit basically performs a flip-flop operation. In flip-flop operation, the voltage at the cathode of each Zener diode is clamped to its breakdown voltage, and the gate voltage of the transistor to which these cathodes are connected does not fall below the breakdown voltage of the Zener diode. Therefore, only a signal with a small amplitude compared to the power supply voltage value is applied to the gate of the transistor described above, and no hot carrier injection effect occurs. Therefore, even in the case of a high voltage level shift circuit, the characteristics due to hot carriers No deterioration occurs.

Furthermore, it is also possible to set the voltage applied to the gate independently of the power supply voltage.

In the above, the operation of the first invention has been explained, but the second invention is a circuit that shifts a negative voltage level, and its operation is the same as the above explanation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the first invention.
As in Fig. 3, 1 is a high voltage level shift circuit, 2
1 is a high voltage CMOS output circuit, 3 is a control signal input terminal, 4 is an inverted control signal input terminal, 11 is a positive high voltage application terminal, and 12 is a reference potential application terminal.

The high voltage CMOS output circuit 2 includes a high voltage PMOS transistor 9 and a high voltage NMOS transistor 10.
This is a high voltage inverter consisting of

High voltage level shift circuit 1 is a high voltage PMOS
It is composed of transistors 5 and 6, high voltage NMOS transistors 7 and 8, Zener diodes 13 and 14, and resistors 16 and 17, forming a high voltage CMOS flip-flop as shown in FIG.

That is, the drain of the first high voltage PMOS transistor 6 and the drain of the second high voltage NMOS transistor 8 are connected, and the third high voltage
The drain of the PMOS transistor 5 and the drain of the fourth high voltage NMOS transistor 7 are connected, the source of the first high voltage PMOS transistor 6 and the source of the third high voltage PMOS transistor 5 are connected, and the positive A power supply voltage of
the source of the second high voltage NMOS transistor 8;
The source of the fourth high-voltage NMOS transistor 7 is connected to apply a reference potential, and the anode of the first Zener diode 14 is connected to the source of the third high-voltage NMOS transistor 7.
The drain and cathode of the PMOS transistor 5 are connected to the negative end of the first resistor 17, and the first
The other end of the resistor 17 is connected to the source of the first high voltage PMOS transistor 6, and the anode of the second Zener diode 13 is connected to the first high voltage PMOS transistor 6.
The drain of the PMOS transistor 6 and its cathode are connected to one end of the second resistor 16, and the second
The other end of the resistor 16 is connected to the source of the third high voltage PMOS transistor 5, and the other end of the resistor 16 is connected to the source of the third high voltage PMOS transistor 5.
The gate of the PMOS transistor 6 is connected to the cathode of the first Zener diode 14, the gate of the third high voltage PMOS transistor 5 is connected to the cathode of the second Zener diode 13, and the second high voltage NMOS transistor A signal is input to the gate of the fourth high-voltage NMOS transistor 7, and an inverted signal is input to the gate of the fourth high-voltage NMOS transistor 7. That is, the control signal is applied to the gates of the high voltage NMOS transistor 8 and the high voltage NMOS transistor 10. Inversion control signal has high voltage resistance
Applied to the gate of NMOS transistor 7.
The level-shifted control signal is taken out from the cathode of the Zener diode 14 and
Applied to the gate of PMOS transistor 9.

The Zener diodes 13 and 14 of the high voltage level shift circuit 1 shown in FIG. 1 are those whose withstand voltage is lower than the high voltage applied. Then, as mentioned above, the level-shifted signal is taken out from the cathode of the Zener diode 14, and the high-voltage
It is applied to the gate of PMOS transistor 9. The high voltage level shift circuit 1 shown in FIG. 1 basically has the following features:
Performs high voltage flip-flop operation. For example, high voltage PMOS transistor 5 is off, high voltage
When the NMOS transistor 7 is on, the voltage at the cathode of the Zener diode 14 is clamped to its breakdown voltage. Further, in this case, the value of current flowing through the high voltage NMOS transistor 7 is determined by the resistance value of the resistor 17. That is,
The gate voltage of the high voltage PMOS transistors 5 and 6 does not drop below the breakdown voltage of the Zener diodes 13 and 14. Therefore, if the breakdown voltage of the Zener diodes 13 and 14 is set to a voltage that does not cause the hot carrier injection effect, high voltage
The characteristics of the PMOS transistors 5, 6, and 9 do not deteriorate due to hot carriers. Furthermore, it becomes possible to set the voltage applied to the gates of the high voltage PMOS transistors 5, 6, and 9 independently of the power supply voltage.

More specifically, for example, 200V is applied to the positive high voltage application terminal 11, 0V is applied to the reference potential application terminal 12, and the Zener diode 1
Consider the case where the breakdown voltage of 3 and 14 is set to 180V. In that case, high voltage PMOS transistor 5,
A signal having an amplitude between 200V and 180V is applied to gates 6 and 9. Since the source potential of high voltage PMOS transistors 5, 6, and 9 is 200V,
Effectively, only a signal with an amplitude of 20V is applied to the gate. Therefore, no hot carrier injection effect occurs in the high voltage PMOS transistors 5, 6, and 9. Further, the gate oxide film thickness can be made thin regardless of the high voltage applied.

In the embodiment shown in FIG. 1, it has been explained that the level-shifted signal is extracted only from the cathode of the Zener diode 14, but depending on the format of the output circuit, if a level-shifted inverted signal is required. is taken out from the cathode of the Zener diode 13. That is, the configuration may be such that a signal is output from at least one of the cathode of the first Zener diode 14 and the cathode of the second Zener diode 13.

Furthermore, if both a level-shifted signal and a level-shifted inverted signal are required, the signals can be taken out from both cathodes of the Zener diodes 13 and 14.

FIG. 2 shows an embodiment of the second invention.
In the case of the configuration shown in FIG. 2, a high voltage level shift circuit 1, a high voltage CMOS output circuit 2, a control signal input terminal 3, an inverted control signal input terminal 4, a negative high voltage application terminal 18, and a reference potential application electron 12 are connected. We are prepared.

The high voltage level shift circuit 1 includes high voltage PMOS transistors 5 and 6 connected to a reference potential application terminal 12, high voltage NMOS transistors 7 and 8 connected to a negative high voltage application terminal 18, Zener diodes 13 and 14, and resistors 16 and 17, and as shown in FIG.
It forms a CMOS flip-flop.

That is, the drain of the first high voltage PMOS transistor 6 and the drain of the second high voltage NMOS transistor 8 are connected, and the third high voltage
The drain of the PMOS transistor 5 and the drain of the fourth high voltage NMOS transistor 7 are connected, the source of the first high voltage PMOS transistor 6 and the source of the third PMOS transistor 5 are connected, and the reference potential is is applied to the source of the second high voltage NMOS transistor 8 and the fourth
A negative power supply voltage is applied to the source of the high voltage NMOS transistor 7, and the cathode of the first Zener diode 14 is connected to the source of the fourth high voltage NMOS transistor 7.
The drain of the NMOS transistor 7 and its anode are connected to one end of the first resistor 17.
The other end of the resistor 17 is connected to the source of the second high voltage NMOS transistor 8, and the cathode of the second Zener diode 13 is connected to the second high voltage NMOS transistor 8.
The drain of the NMOS transistor 8 and its anode are connected to one end of the second resistor 16, and the second
The other end of the resistor 16 is connected to the source of the fourth high-voltage NMOS transistor 7, and the second high-voltage
The gate of the NMOS transistor 8 is connected to the anode of the first Zener diode 14, the gate of the fourth high voltage NMOS transistor 7 is connected to the anode of the second Zener diode 13, and the gate of the first high voltage PMOS transistor is connected to the anode of the second Zener diode 13. A signal is input to the gate of the third high-voltage PMOS transistor 5, and an inverted signal is input to the gate of the third high-voltage PMOS transistor 5. In other words, the control signal is the high withstand voltage of the high withstand voltage PMOS transistor 6 and the high withstand voltage CMOS output circuit 2.
The inverted control signal is applied to the gate of PMOS transistor 9, and the inverted control signal is applied to the gate of high voltage PMOS transistor 5. The level-shifted control signal is taken out from the anode of the Zener diode 14 and output to the high voltage CMOS output circuit 2.
It is applied to the gate of the NMOS transistor 10.

The high voltage CMOS output circuit 2 consists of a high voltage PMOS transistor 9 and a high voltage
This is a high voltage inverter composed of an NMOS transistor 10.

The configuration of FIG. 2 is a negative high voltage level shifting circuit. In this embodiment, consider the case where, for example, -200V is applied to the negative high voltage application terminal 18, 0V is applied to the reference potential application terminal 12, and the breakdown voltage of the Zener diodes 13 and 14 is set to -180V. . In that case, -200V and -
A signal swinging between 180V is applied. High pressure
Since the source potential of NMOS transistors 7, 8, and 10 is -200V, the gates are effectively
Only 20V amplitude signals are applied. Therefore, no hot carrier injection effect occurs in the high voltage NMOS transistors 7, 8, and 10. Further, the gate oxide film thickness can be made thin regardless of the high voltage applied.

In the embodiment shown in FIG. 2, it has been explained that the level-shifted signal is extracted only from the anode of the Zener diode 14, but depending on the format of the output circuit, if a level-shifted inverted signal is required. is extracted from the anode of the Zener diode 13. That is, the configuration may be such that a signal is output from at least one of the anode 14 of the first Zener diode and the anode 13 of the second Zener diode. Furthermore, if both a level-shifted signal and a level-shifted inverted signal are required, a Zener diode 1
It is sufficient to extract signals from both anodes 3 and 14.

〔Effect of the invention〕

According to each of the present inventions, since the signal level after level shift is determined by the power supply voltage and the breakdown voltage of the Zener diode, even in high voltage CMOS circuits,
A level shift circuit without the hot carrier injection effect is obtained, and in the first invention, the voltage is shifted to a positive voltage.
In the second invention, a level shift circuit that shifts the level to a negative voltage is obtained.

[Brief explanation of drawings]

FIG. 1 is a high voltage CMOS circuit diagram including a level shift circuit according to an embodiment of the first invention, FIG. 2 is a high voltage CMOS circuit diagram including a level shift circuit according to an embodiment of the second invention, FIG. 3 is a high voltage CMOS circuit diagram showing a conventional example. 1...High voltage level shift circuit, 2...High voltage
CMOS output circuit, 3...control signal input terminal, 4...
Inversion control signal input terminal, 5, 6, 9...High voltage resistance
PMOS transistor, 7, 8, 10...high voltage resistance
NMOS transistor, 11... Positive high voltage application terminal, 12... Reference potential application terminal, 13, 14... Zener diode, 15... High voltage level shift circuit, 16, 17... Resistor, 18... Negative high voltage application terminal.

Claims (1)

[Claims] 1. A first PMOS transistor, a second NMOS transistor whose own drain is connected to the drain of the first PMOS transistor, and a source of the first PMOS transistor and its own source. A third PMOS transistor is connected to the third PMOS transistor to which a positive power supply voltage is applied, and the drain of the third PMOS transistor is connected to the drain of the second NMOS
a fourth NMOS transistor to which the source of the transistor and its source are connected and a reference potential is applied; the anode is connected to the drain of the third PMOS transistor, and the cathode is connected to the gate of the first PMOS transistor. a first resistor having one end connected to the cathode of the first Zener diode and the other end connected to the source of the first PMOS transistor; an anode connected to the first PMOS transistor; a second Zener diode whose cathode is connected to the drain of the transistor and the gate of the third PMOS transistor; one end is connected to the cathode of the second Zener diode and the other end is connected to the source of the third PMOS transistor. a second resistor connected to each of the transistors, a signal is input to the gate of the second NMOS transistor, an inverted signal is input to the gate of the fourth NMOS transistor, and a signal is input to the gate of the first Zener diode. A level shift circuit characterized in that a signal is output from at least one of a cathode and a second Zener diode. 2 A first PMOS transistor, a second NMOS transistor whose own drain is connected to the drain of the first PMOS transistor, and a reference potential in which the source of the first PMOS transistor and its own source are connected. is applied to a third PMOS transistor, and its own drain is connected to the drain of this third PMOS transistor, and the second NMOS transistor
a fourth NMOS transistor to which the source of the transistor and its own source are connected and a negative power supply voltage is applied; a cathode is connected to the drain of the fourth NMOS transistor, and an anode is connected to the gate of the second PMOS transistor. a first Zener diode connected to each other; a first resistor having one end connected to the anode of the first Zener diode and the other end connected to the source of the second NMOS transistor; and a cathode connected to the second NMOS transistor. a second Zener diode whose anode is connected to the drain of the NMOS transistor, and whose anode is connected to the gate of the fourth NMOS transistor; one end is connected to the anode of the second Zener diode, and the other end is connected to the fourth NMOS transistor. and a second resistor connected to the sources of the first Zener transistor, inputs a signal to the gate of the first PMOS transistor, inputs an inverted signal to the gate of the third PMOS transistor, and inputs a signal to the gate of the first Zener transistor. A level shift circuit characterized in that a signal is output from at least one of a diode anode and a second Zener diode.