JPH04290168A - Simulation device and display method for its simulation result - Google Patents

Abstract

PURPOSE:To improve the visibility and save the labor for visual interface developing operation and operation analyzing operation when a block diagram for displaying the simulation result is automatically generated and displayed. CONSTITUTION:An automatic block diagram rearrangement processing part 3 which minimizes the drawing area of the block diagram and the number of intersections and the number of bends according to block-to-block connection information 1 puts plural blocks having the same function and blocks having the same input and output into one block and displays it together with an added attribute. Consequently, the visibility is improved.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a simulation device for simulating the progress of operations in a data processing device such as a microprocessor, and in particular to a simulation device suitable for displaying simulation results in an easy-to-read format, and a simulation device thereof. Regarding the method of displaying results.

0002

2. Description of the Related Art When simulating a microprocessor or the like, it is first necessary to display the microprocessor on a screen as a combination of functional blocks, and then to display the process of operation of each functional block. Similar to the technology of displaying a microprocessor by combining functional blocks, there is a technology that automatically generates a logic circuit that executes logic between input and output (for example, Japanese Patent Laid-Open No. 61-196
No. 374). Further, as a conventional technique similar to the technique of displaying the process of operation, there is a technique described in Japanese Patent Laid-Open No. 177637/1983. In this conventional technology, when displaying the output level of each logic circuit as a result of a logic circuit simulation, instead of displaying the characters "H" and "L", the output line of the logic circuit is displayed when the output level is "H". ” is displayed as a “bold line” and “L” is displayed as a “broken line” so that the simulation results can be understood at a glance when the logic circuit diagram is displayed on the screen.

0003

[Problems to be Solved by the Invention] The above-mentioned prior art is
Both are related to automatic circuit generation at the logic circuit level and display of simulation results. Even if it is attempted to represent a microprocessor consisting of a combination of logic circuits at the logic circuit level, it is difficult because the number of circuits is enormous and complex. Therefore, the configuration will be displayed in a functional block diagram. Since the input/output signals of a functional block are different from the logic circuit level, the above-mentioned conventional technology cannot be directly applied to this functional block. Furthermore, even if the display is performed using functional blocks, there are a large number of blocks, so if the display is automatically wired between these blocks, the entire screen will be filled with blocks, making it difficult to see.

SUMMARY OF THE INVENTION An object of the present invention is to provide a simulation device and a simulation result display method that can display the configuration in an easy-to-read manner when automatically wiring functional blocks.

Another object of the present invention is to provide a simulation device and simulation device that can grasp the progress status of operation commands at a glance when displaying a data processing device to be simulated using functional blocks and displaying the simulation results of the operation process. The objective is to provide a method for displaying results.

[0006]

[Means for Solving the Problem] The above object is to provide an electronic computer that automatically generates a block wiring diagram to be displayed on a screen from connection information between blocks of a system consisting of a large number of blocks and operation information for each block. , when analyzing the operation information and connection information and confirming that multiple blocks with the same function are connected in parallel, or when confirming that multiple blocks have the same input/output, or when multiple blocks are connected to one block. This is achieved by integrating these multiple blocks into one block and adding and displaying information indicating how the blocks were integrated as attached information when it is confirmed that the blocks are connected.

[0007] Another object of the present invention is to provide a simulation device that simulates the operation when a system is given operation information in which macro instructions are configured as a hierarchy of micro operation instructions.
In addition to displaying a shape representing the
By moving and displaying the "instruction" figure along the time axis and visualizing the execution process of the "instruction" on a time chart,
achieved.

[0008]

[Effect] By integrating and displaying multiple blocks as one, the drawing area, number of wiring intersections, and number of bends are minimized and displayed, making the screen easier to see and making it easier to create visual interfaces. Labor saving and simulation
You will be able to easily understand the results of your application.

Furthermore, by looking at the time chart, it is possible to grasp at a glance which command has progressed to what point in the process of operation.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a simulation apparatus according to an embodiment of the present invention that automatically generates a visual interface in simulation of a microprogram-controlled microprocessor. This simulation device includes an input device 1 for inputting block diagram connection information of a microprocessor to be simulated, a block diagram automatic placement processing section 2 for analyzing the input connection information and grouping a plurality of identical functional blocks, and A block diagram relocation processing unit 3 that rearranges the block diagram based on the decision of the processing unit 2; a block diagram automatic wiring processing unit 4 that performs wiring between the rearranged block diagrams; and a block diagram automatic wiring processing unit 4 that performs wiring between the rearranged block diagrams; A drawing data storage memory 5 that stores data, a simulation execution processing section 6, a storage memory 7 that stores simulation results, a display control processing section 8 that performs control when displaying simulation results on the screen, and a CR
It consists of a graphic display 9 such as a CRT screen, and a pointing device 10 for pointing to icons etc. displayed on a CRT screen. The block diagram automatic arrangement processing unit 2 is comprised of a relocation block description conversion processing means 21 and a block diagram automatic arrangement processing means 22, which perform processing to be described in detail later. The block diagram relocation processing unit 3 includes the same functional block relocation processing means 31 which also executes processing which will be described in detail later.
It consists of a same input/output block relocation processing means 32 and a multiple input block relocation processing means 33. Display control processing section 8
consists of a drawing data display attribute change processing means 81 and a simulation data input/output processing means 82.

FIGS. 4 to 6 are diagrams for explaining the outline of the processing of the above-mentioned simulation apparatus. This simulation device displays the block diagram on the screen according to the connection information of the input block diagram. However, if the connection information is directly replaced with the wiring diagram of the block diagram and displayed, many wiring intersections may occur. In addition, the screen is filled with blocks, making the display difficult to see. Therefore, in this embodiment, when blocks with the same function are connected in parallel as shown in FIG. 4(a), they are displayed together as shown in FIG. 4(b), and the display area is We aim to reduce the size of the Similarly, if there are a plurality of blocks with the same input/output as shown in FIG. 5(a), they are also displayed together as shown in FIG. 5(b). Furthermore, as shown in Fig. 6(a), if the wiring is input to one block by two blocks and the wiring is bent many times, the wiring shown in Fig. 6(b)
), change the display so that it is a simple wiring.

FIG. 3 is an example of a block diagram and connection information of the hardware configuration of a microprocessor to be simulated. The connection information of FIG. 4(a) is written in the 301 part, the connection information of FIG. 5(a) is written in the 302 part, and the connection information of FIG. 6(a) is written in the 303 part. Are listed. The description format of the connection information is as follows.

``net (output destination block name (block number, terminal name, [hit length]) = input destination block name (block number, terminal name, [hit length]))
．． net (output destination block name (terminal name, [hit length]
) = input destination block name (terminal name, [hit length]))
．． group ([Flock name 1, Block 2, Block 3,---, Block n]). ” In this example, the connection relationship between input and output between two blocks is described centering on the net. "Bit length" represents the number of signal lines, and descriptions with the same "block name" and "block number" as an argument indicate blocks with the same function. The "group" statement is a definition of blocks having the same input/output destination, and specifies the arrangement order of blocks when rearranged after equivalent conversion. Actually, they are arranged according to the order of description from the left.

Hereinafter, a method of generating drawing data using the block diagram connection information shown in FIG. 3 and a visual interface function using the drawing data will be explained.

FIG. 2 is a flowchart showing the processing procedure of the drawing data generation method. First, the given block diagram connection information (FIG. 3) is fetched in the process of step 201. The block diagram connection according to the description at 301 in FIG. 3 is a configuration in which blocks r0 to r7 having the same data processing function are connected in parallel (FIG. 4(a)). Therefore, this portion becomes a target of equivalent conversion same functional block relocation processing. In relocation block description conversion processing step 202 following step 201, these blocks r0, r1, r
For 2, r3, r4, r5, r6, and r7, the placement target block name "r" is used as a representative name, and the drawing area is minimized as shown in FIG. 4(b).

According to the description at 302 in FIG. 3, the input terminals of blocks fsr, pc, and c are all lbus
(Figure 5(a)). Further, the output terminal is similarly connected to the rbus. Furthermore, g
A roup statement is also defined. Therefore, the data device is
Recognizing that this part is subject to the same input/output block omission placement process, we set the placement target block name fsr as the representative name for blocks fsr, pc, and c, and set the placement area to 3.
Allocate blocks for each block (FIG. 5(b)).

According to the description at 303 in FIG. 3, two blocks, latch1 and latch2, are connected to block alu1 (FIG. 6(a)). Therefore, recognizing that the block will be subject to multi-input block relocation processing, we set the placement target block name latch2 as a representative name and secure one block as the placement area (Figure 6(b)), thereby increasing the drawing area. and minimize the number of bends during wiring. A portion 304 in FIG. 3 is other connection information necessary for creating a block diagram.

Next, the automatic block diagram arrangement process in step 203 of FIG. 2 will be explained. The detailed procedure of this automatic block diagram arrangement process is shown in FIG. Here, since buses are also treated as blocks, first, the arrangement order of the buses is determined. The arrangement order of this bus is determined according to the total number of blocks connected to the bus. To do this, display the total number of blocks connected to each bus. For example, lbus has blocks mm, mar, ir, la.
This indicates that six blocks, tch2, fsr, and r, are connected. Similar processing is performed for the remaining buses to obtain the bus connection list 901 shown in FIG. At this time, the connection list bloc between blocks that are not connected to the bus
k_connect (fifth line of list 901) is also determined. When arranging buses, as shown in Figure 8,
In order to reduce the number of wiring crossings, the buses are placed on both sides of the blocks starting from the inside, starting from the bus connected to the largest number of blocks.

In the next step 702 in FIG. 7, the previously determined block to be rearranged is omitted from the bus connection list. Then, in the connection list 901 of each bus, the list is read in order based on the bus with the largest number of connected blocks, and duplicate blocks are eliminated. At this time, non-overlapping blocks are added to the top of the list to obtain the bus arrangement list 902 of FIG. 9 (step 703). after that,
Based on the bus arrangement list 902 and the fifth line in the block connection list 901, blocks that are connected between blocks are put together in the same list, sorted in descending order of the number of connections between blocks, and a block connection relationship list 903 is created. Extract (step 704). In this example, [latch3, sh
ift1, alu1, latch2] means that these four blocks are arranged next to each other because they have a connection relationship with each other. Then, by reversing the list, an initial block arrangement list 904 is obtained (step 705).

FIG. 10 is a display example of an initial arrangement block diagram arranged based on this initial arrangement list 904. Blocks indicated by reference numerals 1001, 1002, and 1003 are the results of automatic arrangement by the block diagram automatic arrangement processing section. Next, block relocation processing is performed on the generated automatic placement results.

First, the same functional block relocation process (FIG. 2
In step 204), the drawing attribute of the composite block shown as 1101 in FIG. 11 is given to the same functional block r shown as 1001 in FIG.

In the same input/output block relocation processing performed in the next step 205, gr
According to the definition order of the oup statement, fsr (1102 in Figure 11)
, pc (1103 in Figure 11), c (1104 in Figure 11)
Divide vertically into three parts.

In the multi-input block rearrangement process in the next step 206, the multi-input block latch1 indicated by reference numeral 1003 in FIG.
), latch2 (1106 in FIG. 11).

The block diagram automatic wiring process (step 207) is performed on the block diagram rearrangement result obtained in this way.
) performs a known automatic wiring process. The block diagram drawing data generated as a result is stored in the drawing data storage memory 5 shown in FIG. 1 through a drawing data storage process (step 208). Further, in the drawing data display process of step 209, drawing data is displayed on the screen as shown in FIG.

After displaying the drawing data shown in FIG. 12 on the screen, the work proceeds through interactive operations in the form of a menu. In the transfer route display process (step 210), as shown at 1202 in FIG. 12, the data transfer position on the block diagram is indicated by displaying diagonal lines or changing colors, for example. In the parameter input process (step 211), as shown by reference numeral 1203 in FIG.
204 and 1205. ) and enter the parameters here. This is then stored in the simulation result storage memory 7 of FIG. In the result display process of step 212, as shown at 1204 in FIG. 12, a block whose execution result is to be displayed is selected with a pointing device, a display screen for displaying the execution result is opened on the block diagram to be displayed, and the simulation is started. - The execution result is retrieved from the execution result storage memory 7 and displayed on this screen 1204. For the same functional block, as shown by reference numeral 1205 in Fig. 12, screens corresponding to each block within the same functional block are displayed all at once as a screen for inputting parameters and displaying execution results. do.

According to the embodiment described above, in the method of simulating the progress of the operation of a data processing device that performs a series of data processing based on the connection information representing the flow between blocks. In particular, it automatically creates a visual interface that has the ability to display the progress of operations on a block diagram based on the connection information between blocks, and to input the parameters necessary for simulation directly from specific blocks on the screen. can be generated. For this reason, it is expected that the work period for visual interface development will be shortened, and when automatically generating a block diagram, the drawing area of the block diagram and the number of wiring intersections/bends can be minimized, making it easier to simulate - This has the effect of making it easier to see the results of the analysis.

Next, an embodiment of the present invention will be described in which a time chart in a simulation of a microprogram-controlled microprocessor is displayed on a screen. FIG. 13 is a configuration diagram of a simulation apparatus according to this embodiment. This simulation device includes an input unit 1301 for inputting block connection information, an input unit 1302 for inputting hierarchical operation information, a processing unit 1303 for processing the hierarchical operation information, and the expanded operation information and block diagram connection information. A simulation execution processing unit 1304 that executes simulation, and a processing unit 1305 that synthesizes motion information.
, a memory 1306 for storing simulation results, a display control processing unit 1307, a graphic display 1308, and a pointing device 1309. The display control processing unit 1307 includes an icon display processing unit 13071, a display switching processing unit 13072, and , a scroll display processing means 13073, and a parameter input processing means 13074.

FIG. 15 is an example of inputting operation information of a hierarchical microprogram. The micro program is
As shown in the figure, the instructions are divided into three layers: microinstructions 1501, mnemonics 1502, and operations 1503, starting from the highest layer. The simulation is executed using information at the lowest hierarchical behavioral level.

Hereinafter, a method for realizing the input/output function of operation information shown in FIG. 15 on a time chart will be explained using a flowchart showing the processing procedure shown in FIG. First, a microinstruction 1501 is fetched (step 1401). In the operation information development process in the next step 1402 (processing in the processing unit 1303 in FIG. 13), this microinstruction 15
01 into three mnemonics 1502, and further 4
The process is expanded into two operations 1503. In step 1403 performed by the simulation execution processing unit 1304, a simulation is executed using the block diagram connection information 1301 and the previously determined operation 1503. Here, the previously expanded microinstructions 1501 are added to the output simulation execution results in the motion information synthesis processing step 1404.
, mnemonic 1502, action 1503 information is added,
The results are stored in the simulation result storage memory (1306) (step 1405).

FIG. 16 is a diagram showing the data structure within this memory 1306. 1601, 1602, and 1603 are data indicating where to display on the time chart;
1604 is a mnemonic, 1605 is an operation, 1606 is a register value, and 1607 is a microinstruction.

In the display control processing unit 1307, as shown in FIG.
03,1704 and the screen opened in the icon
Using the button 1702, information is displayed on a time chart with the horizontal axis of the screen as the time axis. The icon shape is made to correspond to the type of display information. For example, a microinstruction is displayed as an icon 1703 with a shadow on the top, a mnemonic is displayed as an icon 1704 with a shadow on the bottom, and an action is displayed as an icon 1701 without a shadow. .

As for display processing, specified information is sequentially retrieved from the simulation result storage memory (1306) and displayed by the icon display processing means 13071 (step 1406). Alternatively, when the display switching processing means 13072 instructs to switch display information for the entire time chart or individual icons, the specified information is transferred to the simulation result storage memory (
1306) and replaces it with the information currently displayed on the icon and displays it (step 1407).

Information 1503 in operation 1503 in FIG.
1, the screen 1801 in FIG.
As shown in FIG. 2, the information 15031 does not fit within the screen 1801 and is not displayed in its entirety at once. Therefore, in this case, the scroll display processing means 13073 first
The information 15031 is displayed by scrolling left and right as shown on the screen 1802 (step 1408). In addition, a function to display the information 15032 by scrolling the screen 1803 up and down is also provided. Furthermore, the parameter input processing means 13074 inputs information necessary for the simulation from the screen inside the icon, and stores it in the simulation result storage memory, thereby forcibly changing the intermediate results. A re-execution function is also provided (step 1409).

FIG. 19 shows a display example of a time chart. Using the menu 1901, changes in display information can be specified for all displayed icons, and changes in display information can also be specified for each icon individually. 1902 indicates a microinstruction, 1903 indicates a mnemonic, and 19
04 represents the operation, 1905 represents the register value,
Icons are displayed in shapes corresponding to each piece of information.

According to the embodiment described above, the type of information displayed by the icons can be easily grasped, and in addition to the time relationship between executed operations, various types of information such as execution results and hierarchically structured operation information can be understood. The input/output function of time chart
It can be realized on This can save labor in motion analysis work.

Embodiment 1 explained in FIGS. 1 to 12 and FIG.
Combining Example 2 explained in FIGS. 3 to 19, a simulation
As shown in Figure 20, the execution results of the
01, a block diagram display screen 2002 automatically generated according to the first embodiment and a time chart display screen 2003 realized according to the second embodiment are displayed. Conventionally, the content of the execution operation was displayed in text, so a screen 2004 dedicated to history display was required, but in this embodiment, history information is also synthesized and displayed on the time chart display screen 2003. Therefore, this history display screen 2004 can be omitted. By reducing the number of screens by one, it is expected that visibility during motion analysis will improve. In this embodiment, the display 2001 is displayed using the multi-window function, but the block diagram display screen 2002 and the time chart are
It goes without saying that the target display screen 2003 may be displayed on a separate display.

[0037]

[Effects of the Invention] According to the present invention, when visualizing simulation results, blocks with the same function or blocks with the same input/output are displayed together, and a time chart of the operation is automatically generated, thereby improving visibility. It is possible to display a high level of information, and it is possible to save labor in visual interface development work and motion analysis work.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a simulation apparatus according to a first embodiment of the present invention.

[Fig. 2] PAD showing a processing procedure according to an embodiment of the present invention
It is a diagram.

FIG. 3 is a diagram showing block diagram connection information that is an input specification of the microprogram-controlled microprocessor used in the embodiment of the present invention.

FIG. 4 is a schematic explanatory diagram of identical functional block relocation processing.

FIG. 5 is a schematic explanatory diagram of same input/output block relocation processing.

FIG. 6 is a schematic explanatory diagram of multi-input block rearrangement processing.

FIG. 7 is a PAD diagram showing a block diagram automatic arrangement processing procedure.

FIG. 8 is a diagram showing the arrangement order of buses.

FIG. 9 is a diagram showing intermediate information required for automatic block diagram arrangement.

FIG. 10 is a diagram showing placement results automatically placed by a block diagram automatic placement processing unit.

FIG. 11 is a diagram showing the result of rearrangement by a block diagram rearrangement processing unit.

12 is a diagram showing a display example of drawing data generated from the block diagram connection information of FIG. 3; FIG.

FIG. 13 is an overall configuration diagram of a simulation device according to a second embodiment of the present invention.

FIG. 14 is a PAD diagram showing the processing procedure of this embodiment.

FIG. 15 is a diagram showing operation information of a microprogram-controlled microprocessor used in this embodiment.

FIG. 16 is a data configuration diagram in a simulation result storage memory.

FIG. 17 is an explanatory diagram of icons.

FIG. 18 is an explanatory diagram of scroll control.

FIG. 19 is a diagram showing a display example of a time chart that supports the input/output function of simulation information.

FIG. 20 is a diagram showing the effect of simulation using a block diagram according to the first embodiment and a time chart according to the second embodiment, and also shows a conventional history screen displayed at the same time.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Block diagram connection information input device, 2... Block diagram automatic placement processing section, 3... Block diagram relocation processing section, 4... Block diagram automatic wiring processing section, 5... Drawing data storage memory, 6...
Simulation execution processing section, 7... Simulation result storage memory, 8... Display control processing section, 9... Graphic display.

Claims (11)

[Claims] Claim 1: A general-purpose visual interface is automatically generated and drawn blocks based on operation information for each block and connection information representing connection relationships between blocks that are constituent elements of the system. In a simulation device that displays simulation results on a diagram, there is an automatic block diagram generation means that automatically generates a block diagram from connection information between blocks, and coordinate information specified from an input device for the automatically generated block diagram. Recognizes which block on the block diagram has been selected, opens a screen on the block diagram for displaying simulation execution results and inputting/outputting initial values or parameters for the corresponding block, and starts the simulation. - The simulation data input/output means that controls the input/output of data necessary for the simulation and the data transfer route are displayed as animations by changing the display colors of blocks and wiring on the block diagram. drawing data display attribute changing means, and the block diagram automatic generation means generates blocks having the same function name in connection information of the block diagram, and/or blocks having the same input/output, and/or A simulation device comprising means for performing equivalent conversion processing on a block having a plurality of input blocks, reducing the drawing area of a block diagram displayed on a display, and reducing the number of intersections and bends during wiring. . [Claim 2] A general-purpose visual interface is automatically generated and drawn blocks based on operation information for each block and connection information representing connection relationships between blocks that are constituent elements of the system. In a simulation device that displays simulation results on a diagram, there is an automatic block diagram generation means that automatically generates a block diagram from connection information between blocks, and coordinate information specified from an input device for the automatically generated block diagram. Recognizes which block on the block diagram has been selected, opens a screen on the block diagram for displaying simulation execution results and inputting/outputting initial values or parameters for the corresponding block, and starts the simulation. - The simulation data input/output means that controls the input/output of data necessary for the simulation and the data transfer route are displayed as animations by changing the display colors of blocks and wiring on the block diagram. drawing data display attribute changing means is provided, and the block diagram automatic generation means determines the number of connections of blocks connected to each bus from the connection information of the block diagram having a bus structure, and determines the number of connections of blocks connected to each bus. A simulation device characterized by comprising a means for displaying an easy-to-read block diagram by arranging buses in order of proximity to the block arrangement area, reducing the number of intersections during automatic wiring of the entire block diagram. 3. A general-purpose visual interface is automatically generated based on operation information for each block and connection information representing connection relationships between blocks that are constituent elements of the system, and drawn blocks. In a simulation device that displays simulation results on a diagram, there is an automatic block diagram generation means that automatically generates a block diagram from connection information between blocks, and coordinate information specified from an input device for the automatically generated block diagram. Recognizes which block on the block diagram has been selected, opens a screen on the block diagram for displaying simulation execution results and inputting/outputting initial values or parameters for the corresponding block, and starts the simulation. - The simulation data input/output means that controls the input/output of data necessary for the simulation and the data transfer route are displayed as animations by changing the display colors of blocks and wiring on the block diagram. drawing data display attribute changing means is provided, and the block diagram automatic generation means determines the number of connections of blocks connected to each bus from the connection information of the block diagram having a bus structure, and determines the number of connections of blocks connected to each bus. A simulation device characterized by having means for displaying an easy-to-read block diagram by arranging buses sequentially from the inside while sandwiching the block arrangement area from the bus, reducing the number of intersections during automatic wiring of the entire block diagram. 4. Connection information representing connection relationships between blocks that are constituent elements of the system, and operation information having a hierarchical structure in which each sequentially executed macro operation is composed of a series of micro operations. In a simulation device that displays the temporal relationship of executed motions in a time chart based on Time chart display that draws icon shapes on the time chart and displays specified operation display information or execution results on the display screen above the icon, and inputs parameters necessary for simulation. A simulation device characterized by being provided with a control means. 5. The time chart according to claim 4,
The chart display control means includes a display switching processing means for switching and displaying a plurality of pieces of related information on the same screen on a screen opened on an icon drawn on the time chart, and display switching processing means for switching and displaying a plurality of pieces of related information on the same screen. 1. A simulation device characterized by comprising a scroll display control means for checking information while scrolling information that seems to protrude. 6. Connection information representing connection relationships between blocks that are constituent elements of the system, and macro operations to be executed sequentially are each composed of a series of micro operations (operations for each block). 2. The simulation device according to claim 1, wherein the simulation device simulates the operation of a system based on operation information having a hierarchical structure, and displays execution processes and results of macro operations automatically generated from connection information between blocks. Claim 4: Supports automatic block diagram generation means and a history display function for displaying execution results and contents of execution operations.
A simulation device comprising the time chart display control means described above. 7. An electronic computer that automatically generates a block wiring diagram to be displayed on a screen from connection information between blocks of a system composed of a large number of blocks and operation information for each block, wherein the operation information and connection information are When it is analyzed and it is confirmed that multiple blocks with the same function are connected in parallel, there is a means for integrating these multiple blocks into one block and adding and displaying information indicating how the blocks were integrated as attached information. An electronic computer characterized by comprising: 8. An electronic computer that automatically generates a block wiring diagram to be displayed on a screen from connection information between blocks of a system composed of a large number of blocks and operation information for each block, wherein the operation information and connection information are When it is analyzed and it is confirmed that there are multiple blocks with the same input and output, there is a means to integrate these multiple blocks into one block and add and display information indicating how they were integrated as attached information. An electronic computer characterized by comprising: 9. An electronic computer that automatically generates a block wiring diagram to be displayed on a screen from connection information between blocks of a system composed of a large number of blocks and operation information for each block, wherein the operation information and connection information are Provided with means for integrating the blocks into one block when analyzing and confirming that multiple blocks are connected to one block, and adding and displaying information indicating how the blocks were integrated as attached information. An electronic computer featuring: 10. A simulation device comprising an electronic computer according to claim 7 and simulating the operation of the system by displaying the block configuration of the system on a screen, wherein: A method for displaying simulation results characterized in that when simulating data transfer, data existing blocks or data transfer wiring are displayed in a manner that distinguishes them from other blocks and wiring for each data transfer. 11. In a simulation device that simulates an operation when a system is given operation information in which macro instructions are configured as a hierarchy of micro operation instructions, graphics representing each "instruction" from macro to micro are displayed. At the same time, a simulation result display method is characterized in that the figure of the "instruction" executed by the system is moved and displayed along the time axis, and the execution process of the "instruction" is visualized.