JPH04289947A - Load equilibrium control system - Google Patents

Abstract

PURPOSE:To independently equalize the load of an input and an output from each host device in each external storage controller. CONSTITUTION:In a semiconductor storage controller 9 which is interposed between plural channels 2, 3 of a central processor 1, and a semiconductor storage device 10, and processes an input/output request issued to the semiconductor storage device 10 from the channels 2, 3, the input/output request can be equalized by providing block switches 4 and 5 in a signal cable (route A) 11 and a signal cable (route B) 12 through which the input/output request from the channels 2, 3 is issued, respectively, and masking the input/output request from plural channels 2, 3 as required.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load balancing control technique, and more particularly to a load balancing control technique that is effective when applied to equalize input/output loads in an external storage device shared by a plurality of host devices.

0002

2. Description of the Related Art In recent years, with the increase in the performance and scale of computer systems, there has been a demand for higher performance in external storage devices. External storage devices are often connected to multiple computer systems, and must efficiently process input/output requests from each computer system. For this reason, various load balancing control methods have been devised to equalize the load from each computer system in an external storage control device. For example, there is an input/output load monitoring method that counts the number of input/output operations performed by the external storage device itself, such as the technology disclosed in Japanese Patent Application Laid-Open No. 63-146147, in which the true load status is known. A method of displaying the input/output load status on the input/output control device and equalizing the load in the host system as in the technique disclosed in Japanese Patent Laid-Open No. 62-6357, Japanese Patent Laid-Open No. 2-81
A method of prioritizing and processing requests from connected computer systems to equalize the load, such as the technique disclosed in Publication No. 154, and a technique disclosed in Japanese Patent Application Laid-Open No. 1-229351. There are methods to balance the load based on information that predicts average waiting time.

0003

[Problems to be Solved by the Invention] The above conventional technology has the disadvantage that the external storage device cannot prioritize arbitrary input/output requests from the computer system side, or cannot perform communication between two external storage control devices. There was a problem in that the input/output load from each computer system could not be equalized independently by one external storage control device.

An object of the present invention is to provide a load balancing control technique that can independently equalize the load of input/output operations from each host device in each external storage control device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

That is, the load balance control method of the present invention is as follows:
An external storage device equipped with a volatile or nonvolatile storage medium, an external storage control device that controls this external storage device, and an external storage device that is shared via this external storage control device, and data stored in the external storage device is shared. An information processing system consisting of a plurality of host devices that perform input/output such as writing and reading, in which an external storage control device handles input/output requests that temporarily wait for input/output requests from the host device to the external storage device. It has a reservation means and equalizes the input/output load from each host device in the external storage control device.

[0008] Furthermore, the load balance control method according to the present invention is as follows:
An input/output request holding means is provided in an information transmission path for transmitting input/output requests from each higher-level device to the external storage control device, and determines whether or not the input/output request can be connected from each higher-level device to the external storage control device. It consists of block switches to control.

[0009] Furthermore, the load balance control method according to the present invention is as follows:
A part of the external storage control device is provided with a storage means for retaining historical information regarding input/output status from the host device in the past, and the operation of the input/output request suspension means is controlled based on this historical information. It is something.

0010

[Operation] According to the load balance control method of the present invention described above,
By providing the external storage control device with an input/output request holding means that makes the input/output requests from each higher-level device wait, the external storage control device can independently prioritize input/output requests from each higher-level device to a certain degree. , it is possible to equalize the input/output load from each host device to the external storage device. In addition, by controlling the operation of the input/output request holding means based on the history information of input/output requests from the higher-level devices stored in the storage means provided in the external storage control device, each higher-level device can be efficiently Since it is possible to give a certain degree of priority to input/output requests, it is possible to further equalize the load.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below with reference to the drawings. In this embodiment, a semiconductor storage device subsystem is used as an example of an external storage device to which the load balancing control method is applied.

FIG. 1 is a block diagram showing an example of the hardware configuration of a semiconductor storage device subsystem in which the load balancing control method of this embodiment is performed.

The semiconductor storage device subsystem of this embodiment is composed of a semiconductor storage control device 9 and a semiconductor storage device 10 using a semiconductor memory or the like as a storage medium, both of which are connected via an interface cable 13. . On the other hand, the semiconductor storage control device 9 is connected to the central processing unit 1 via a signal cable (route A) 11 and channel 2, and to the central processing unit 1 via a signal cable (route B) 12 and channel 3. There is.

The semiconductor storage control device 9 includes a microprocessor 7 that performs overall control operations, and a memory 8 in which programs and data for the operation of the microprocessor 7 are set, as well as several tables as described below. are provided, and both are connected via a bus line 14.

[0015] Also, signal cables 11 and 12 are connected to upper channels 2 and 3, respectively.
is connected to the microprocessor 7 via a competition circuit 6. Input/output requests to the semiconductor memory device 10 generated from channels 2 and 3 from time to time are accepted by a predetermined arbitration logic (for example, first-come-first-served basis) in the competition circuit 6, and are input to the microprocessor 7, whereby the input/output requests are The execution of the request is configured.

In this case, each of the signal cables 11 and 12 connecting the plurality of channels 2 and 3 and the competition circuit 6 is connected to the semiconductor storage control device 9 from each channel 2 and 3 via the signal cable 11 and 12. A block switch 4 and a block switch 5 are interposed to control whether or not to transmit the above-mentioned input/output request issued to the competition circuit 6 to the competition circuit 6. The operation is configured to be controlled.

An example of the operation of the load balancing control method in the semiconductor memory device subsystem of this embodiment will be explained below.

First, the principle of the load balancing control method in this embodiment will be explained using FIG.

The central processing unit 1 connects the semiconductor storage control device 9 to the signal cable (route A) using channels 2 and 3.
) 11, signal cable (route B) 12, block switch 4, and block switch 5 to issue input/output requests.

Normally, when an input/output request is issued from channel 2 and channel 3, the request is transmitted via the signal cable (route A) 11, signal cable (route B) 12, block switch 4, and block switch 5, and circuit 6
, and notifies the microprocessor 7 of the route that issued the input/output request earlier from channel 2 or channel 3. The microprocessor 7 that received the notification,
Channel input/output requests are received according to instructions from a microprogram stored in memory 8.

In the load balancing control method of this embodiment,
Load balance control is realized by using block switches 4 and 5 located between channels 2 and 3 and the competition circuit 6.

As mentioned above, the block switch 4 and the block switch 5 exist for each connected channel, and have the role of gates for starting channels 2 and 3, for example, by controlling each control signal. When 4a and 5a are set to "1", block switch 4 and block switch 5 are turned on, and an operation is performed to mask input/output requests from channels 2 and 3.

Further, when the control signals 4a and 5a of the block switches 4 and 5 are set to "0", the block switches 4 and 5 are disconnected, and input/output requests from the channels enter the competition circuit 6.

As described above, by using the block switch 4 and the block switch 5, it is possible to balance input and output loads for channels 2 and 3.

FIG. 4 shows a channel route display table 40.
1 shows the configuration of 1. The channel route indicates a route through which an input/output request from a channel arrives at the semiconductor storage control device 9 via the signal cable (route A) 11 and the signal cable (route B) 12.

When expanded, the channel route display table 401 consists of a route A 402 and a route B 403. Route A 402 and route B 403 are in units of bits or bytes. Route A402, Route B403
corresponds to each channel route, and route A402
connect signal cable (route A) 11 to route B403.
corresponds to the signal cable (route B) 12. By using the channel route display table 401, it is possible to determine which route was used for input/output in the past.

FIG. 5 is a startup count display table 501 used to count the number of inputs and outputs. One activation count display table 501 exists in the semiconductor storage control device 9, and is counted up by one every time there is an input/output request.

In this embodiment, as the load balancing control method by the semiconductor storage control device 9, there is a method of simply controlling the block switch 4 and the block switch 5, and a method of controlling the load by simply using the block switch 4 and the block switch 5. There is a method of controlling the operations of the block switches 4 and 5 using stored startup history information from each computer system.

First, a method of controlling load balance by a semiconductor storage control device will be explained using FIGS. 1 and 2. FIG. 2 is an overview of the processing of the microprogram stored in the memory 8. The process in FIG. 2 is located at the point where one input/output operation has already been completed and it is determined which input/output request should be accepted next. First, in step 201, it is checked whether the input/output request from channel 2 or channel 3 has been reported as being in use. If channel 2 or channel 3 is reported to be in use, the process branches to step 203. In step 202, it is checked whether the input/output request just serviced has ended normally. If the process has not ended normally, the process branches to step 204. In step 203, a block switch 4 and a block switch 5 are set up on the channel route for which input/output service has just been performed. In other words, if the channel route for which input/output service has just been performed is channel 2 (signal cable (route A) 11),
Turn on the block switch 4 (set the control signal 4a to "1"), and if the channel route for input/output service is channel 3 (signal cable (route B) 12), turn on the block switch 5 (set the control signal 5a to "1"). (set to “1”). In step 204, activation reception service is performed. The service here accepts input/output requests from unmasked channels 2 and 3 of block switches 4 and 5. If there is an input/output request from channels 2 and 3, the activation count display table 501 is counted up by "1". If there is no input/output request for a certain period of time where the block switch 4 or block switch 5 is not engaged, or if the startup reception service is completed, all block switches 4 and 5 are released in step 205 ( Control signals 4a and 5a are set to “0”), and channel 2
and receive input/output requests from channel 3.

In the embodiment described above, when the number of channels connected to the semiconductor storage control device 9 is small, the load is equalized, but when the number of channels is large, input/output requests from the central processing unit 1 compete. For this reason, there is a concern that input/output services of the semiconductor storage control device 9 may be biased toward a specific channel route.

[0031] Next, using FIGS. 3, 4, and 5,
A load balance control method according to another embodiment of the present invention will be described, which eliminates the above concerns by using the block switch 4, block switch 5, and startup history information from each computer system stored in a table. Figure 3
is an outline of the processing of the microprogram stored in the memory 8.

The process shown in FIG. 3 is performed after input/output has already been completed.
Next, it is positioned to decide which input/output will be accepted.

First, in step 301, it is checked whether an input/output request from channel 2 or channel 3 has been reported as being in use. If channel 2 or channel 3 is reported to be in use, the process branches to step 303. In step 302, it is checked whether the input/output request just serviced has ended normally. If the process has not ended normally, the process branches to step 309.

In step 303, the channel routes of channels 2 and 3 for which input/output request processing was performed immediately before are stored in the channel route display table 401. That is, route A 402 and route B 403 are turned on corresponding to the channel route for which input/output request processing has been performed.

[0035] The channel route display table 401 is “0”.
0'' unless cleared, the state will remain and multiple bits may be turned on.

Next, in step 304, it is determined whether the route displayed in the channel route display table 401 is one route. If there is only one, step 3
At 06, all block switches 4 and 5 are cleared (control signals 4a and 5a are set to "0"). As a result, if only one route is connected,
Masks input/output requests from only one route so that input/output is not obstructed.

If there are multiple routes in step 304, step 305 selects the next route that has been activated in the past in addition to the route for which the input/output request was processed immediately before (in the case of FIG. If the processed route is block switch 4, all routes other than the block switch 5 route are turned on (control signal 4).
a, 5a are set to "0") to give priority service to activation for that route (the route of the block switch 5).

Next, in step 307, it is determined whether the value of the startup count display table 501 has reached 256.
If so, in step 308 channel route display table 4
01 is cleared to "00" and step 309 is executed.

[0039] This makes it possible to memorize the latest channel activation and to always balance the input/output load in accordance with the movement of the channel. Furthermore, when input/output requests from the central processing unit 1 conflict, the channel route serviced by the microprocessor 7 of the semiconductor storage control device 9 is prevented from being biased toward a specific channel route.

Further, if the value of the startup count display table 501 is less than 256 in step 307, step 3
Branch to 09.

Next, in step 309, activation reception service is performed. The service here accepts input/output from unmasked channels 2 and 3 of block switch 4 and block switch 5. If there is an input/output request from channels 2 and 3, the activation count display table 501 is counted up by "1". If no input/output request is issued from channels 2 and 3 for a certain period of time to the unmasked block switches 4 and 5, and if the startup reception service is completed, step 310
The process proceeds to release block switch 4 and block switch 5, allowing input/output requests from channel 2 and channel 3 to be received.

According to this embodiment, even when shared by a plurality of computer systems, the load from each computer system can be equalized.

In this embodiment, there are two channel routes, but it goes without saying that the present invention can also be applied to a case where there are three or more channel routes. In addition, in this embodiment, the activation count display table 501 is cleared by the activation count display table 5.
Although this is done when the value of 01 reaches 256, the trigger for clearing the activation count display table 501 is not limited to the case where the value of the activation count display table 501 is 256.

Although the embodiments described above apply the present invention to a semiconductor storage device subsystem, it can also be applied to semiconductor storage control devices such as a magnetic disk device subsystem and a magnetic tape device subsystem.

Furthermore, in the above embodiment, the channel route display table 401 and the activation count display table 501 can be used without displaying the input/output load status on the input/output control device as in Japanese Patent Application Laid-Open No. 63-223939. , it is possible to equalize the load from each computer system.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

[0047]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.

That is, according to the load balancing control method of the present invention, it is possible to equalize the input/output loads from each host device independently in each semiconductor storage control device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the hardware configuration of a semiconductor storage device subsystem in which a load balancing control method according to an embodiment of the present invention is performed.

FIG. 2 is a flowchart showing an example of the operation of a load balancing control method according to an embodiment of the present invention.

FIG. 3 is a flowchart showing an example of the operation of a load balancing control method according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram showing an example of the configuration of a channel route display table in a load balancing control method according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram showing an example of a start-up count display table in a load balancing control method according to an embodiment of the present invention.

[Explanation of symbols]

1 Central processing unit 2 Channel 3 Channel 4 Block switch 4a Control signal 5 Block switch 5a Control signal 6 Competitive circuit 7 Microprocessor 8 Memory 9 Semiconductor storage control device 10 Semiconductor storage device 11 Signal cable (Route A) 12 Signal cable (Route B ) 13 Interface cable 14 Bus line 401 Channel route display table 401 Startup display table 501 Startup count display table

Claims (3)

[Claims] 1. An external storage device including a volatile or non-volatile storage medium, an external storage control device that controls the external storage device, and the external storage device shared through the external storage control device, An information processing system comprising a plurality of host devices that perform input/output such as writing and reading data to and from the external storage device, wherein the external storage control device handles input/output requests from the host device to the external storage device. 1. A load balancing control method, comprising: an input/output request holding means for temporarily waiting for input/output requests, and equalizing input/output loads from individual host devices in the external storage control device. 2. The input/output request holding means is interposed in an information transmission path for transmitting input/output requests from each of the higher-level devices to the external storage control device, and 2. The load balancing control system according to claim 1, further comprising a block switch for controlling whether or not the input/output request can be connected to the load balancing control system. 3. A part of the external storage control device is provided with a storage means for holding history information regarding input/output status from the host device in the past, and based on the history information,
3. The load balancing control system according to claim 1, further comprising controlling the operation of said input/output request holding means.