JP2003196222A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage controller for controlling coexisting interface protocols of different kinds. <P>SOLUTION: This information processor is constituted of central processing units 1 to 4, electric channels 5 and 7, optical channels 6 and 8, electric cables 9 and 11, optical cables 10, 12, and 14, a relay unit 13, a semiconductor storage controller 15, a semiconductor storage device 16, channel interface control parts 17 to 20, a microprocessor 21, a memory 22, a selecting circuit 23, data transfer control circuits 24 and 25, a drive interface control part 25, control lines 26 to 31, and data transfer paths 32 to 35. Thus, it is possible to connect an external storage controller and an external storage device to an information transmission paths of various information transmission methods (interface protocols). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to different I / O interface protocol control techniques, and more particularly to a technique for connecting a storage device shared by a plurality of host devices to different I / O interface protocols. The present invention also relates to a technique for performing mixed control of different I / O interface protocols and load balancing control in a storage controller.

[0002]

2. Description of the Related Art In recent years, with the increase in performance and scale of computer systems, which are information processing devices, there is a demand for higher performance in storage devices, such as external storage devices. Recently, for the purpose of extending the maximum connection distance, improving the data transfer rate, and reducing the diameter and weight of the connection cable, the connection cable between the channel and the peripheral device is being changed from an electric cable to an optical cable (optical fiber). . There are the following methods for forming an optical fiber in a transmission path connecting a computer and peripheral devices.

(A) Partial replacement of a channel path that employs an optical fiber for a part of the transmission path of the electric channel.

(B) Complete replacement of the channel path that employs optical fiber entirely while maintaining the electrical channel protocol.

(C) ESCON (Enter) whose architecture is expanded by introducing a director capable of dynamic exchange.
Abbreviation of rprise System Connection, ESCON is a trademark of IBM Corporation.

(D) FDDI (Fiber) for connecting a host and peripheral devices to a high-speed local area network
Distributed Data Interfa
abbreviation of ce).

(E) HIPPI (High) for optical communication
Performance Parallel Int
abbreviation of erface).

Regarding the above-mentioned prior art, the Nikkei Computer, January 28, 1991, pages 95 to 104 (NIKKEI COMPUTER, 1991.1.2).
8PP95-104). In an external storage control device and an external storage device, various types of control of different interfaces have been devised. For example,
By providing the control device with a parallel interface (reception of image data) and a serial interface (transmission / reception of command data, status information, etc.) as in the technique disclosed in JP-A-62-286152, I
System for high-speed transmission of large amounts of data and bidirectional communication of various information between the I / O and host machine, Japanese Patent Laid-Open No. 63-22
External interface for performing data transfer under program control and D as in the technique disclosed in Japanese Patent No. 8250
There is a method of providing an interface selecting means for selecting a desired interface from among data transfer under MA control and connecting with an input / output device.

Regarding the load balancing control method, the number of input / outputs executed by the external storage device itself is counted so that the true load status can be known as in the technique disclosed in Japanese Patent Laid-Open No. 63-146147. A load monitoring method for input / output, a method for displaying the input / output load status on an input / output device as in the technique disclosed in Japanese Patent Laid-Open No. 63-223939, and making the load uniform in the host system. No. 6357 and JP-A No. 2-81154, a method for equalizing the load by prioritizing the requests from the connected computer systems and processing them.
A method for balancing the load based on the information for predicting the average waiting time as in the technology disclosed in Japanese Patent No. 29351.
There is a load balancing control system using a block switch as in the technique disclosed in Japanese Patent Application No. 3-54232.

[0010]

The above-mentioned prior art relating to heterogeneous interface control is such that command data, status information, data, etc. are transmitted and received by the same interface protocol, and a plurality of information transmission paths which are heterogeneous interface protocols are externally stored. There is a problem in that the external storage control device cannot be connected to the information transmission paths of various different interface protocols because no consideration is given to the connection to the control device.

Japanese Patent Application No. 3-5423 concerning load balancing control
The above-mentioned prior arts other than Japanese Patent Laid-Open No. 2 consider the point that the external storage device side cannot perform arbitrary input / output priority processing from the host device side, or that communication cannot be performed between the two external storage control devices. Therefore, there is a problem that one external storage control device cannot independently equalize the input / output load from the host device. Further, in the above-described conventional technique as disclosed in Japanese Patent Application No. 3-54232, a host device that is connected but stopped is also subject to load balancing control.
When there are many host devices that are stopped, there is a problem that the load balancing control is inefficient.

It is an object of the present invention to provide an information processing apparatus capable of controlling the mixture of information transmission paths of various different interface protocols.

[0013]

In order to solve the above-mentioned problems, an information processing apparatus of the present application having a storage control device having a plurality of information transmission paths and a storage device controlled by the storage control device is A plurality of information transmission routes are connected to a host device that inputs and outputs information to and from the storage device via at least two different interface protocols, and the storage control device is connected to the information transmission path, A plurality of channel interface control units for inputting and outputting information corresponding to the interface protocol of the information transmission path, and detection means for detecting the interface protocols of the plurality of channel interface control units,
It is configured to include a storage unit that holds history information regarding input / output with the host device, and a load balance control unit that performs load balance control between information transmission paths based on the history information.

Further, when the channel interface control unit receives a request for input / output processing from the host device, the load balance control means receives the service for the previous request for input / output processing. Channel interface control unit, and if the result of this determination is not the channel interface control unit that received the service for the previous I / O processing request, the channel interface control unit that received the I / O processing request Load balancing means for selecting, wherein the storage control device executes a request for input / output processing of the channel interface control unit selected by the load balancing means.

A storage device, a storage control device that controls the storage device, at least one host device that inputs and outputs information to and from the storage device via the storage controller, the host device, and the storage control device. In an information processing device having a plurality of information transmission paths having different interface protocols for transmitting information between them, the channel interface control unit inputs and outputs information corresponding to the different interface protocols.

[0015]

In this embodiment, in order to achieve the purpose of performing the above-mentioned heterogeneous interface control, hardware information, hardware registers, control lines, etc. in the external storage controller are used in advance to work on hardware information. It is stored in a table or the like used by the microprogram, and the hardware information stored in the table or the like is referred every time an input / output request is executed.

Further, in order to achieve the purpose of performing the load balancing control, means for notifying the microprocessor of all host devices having an input / output request to the external storage controller, and storing the host device having the input / output request. Control is performed by combining a boot history table and a unit for selecting one input / output request from a plurality of input / output requests.

As a result, by having the hardware information of the information transmission method (interface protocol) in the external storage control device, the interface protocol for each information transmission path connected to the external storage control device becomes clear. It becomes possible to connect the information transmission paths having different information transmission methods to the external storage control device and the external storage device.

Further, by providing the above means, it becomes possible to carry out fine load balancing control according to the operating condition of the host device with a small amount of information.

The present invention will be described in detail below with reference to the drawings. In this embodiment, a semiconductor memory device subsystem is used as an example of an external memory device to which the heterogeneous interface control method is applied.

FIG. 1 is a block diagram showing an example of the hardware configuration of an information processing apparatus having a semiconductor memory device subsystem in which the heterogeneous interface control method of this embodiment is performed.

The information processing apparatus of this embodiment comprises a semiconductor memory device subsystem, an electric cable 9 and an electric channel 5.
, Central processing unit 1, optical cable 10 and optical channel 6
It has a central processing unit 2, an electric cable 11, an electric channel 7, a central processing unit 3, optical cables 12, 14, a repeater 13, an optical channel 8, and a central processing unit 4. The semiconductor memory device subsystem is composed of a semiconductor memory control device 15 and a semiconductor memory device 16 having a semiconductor memory as a storage medium, both of which are connected via a control line 29 and a data transfer path 35. On the other hand, the semiconductor memory controller 15 is connected to the central processing unit 1 via the electric cable 9 and the electric channel 5, to the central processing unit 2 via the optical cable 10 and the optical channel 6, and to the central processing unit 2 via the electric cable 11 and the electric channel 7. Central processing 3, optical fiber 1
2, 14 and the repeater 13 and the optical channel 8 are connected to the central processing unit 4.

The semiconductor memory controller 15 includes channel interface controllers 17 to 20 and a data transfer path 32.
A selection circuit 23, a data transfer path 33, a data transfer control circuit 24, a data transfer path 34, a drive interface control section 25, a data transfer path 35, and control lines 26, 27, 28, 29, 31. And a microprocessor 21 that performs the overall control operation, and a microprogram and data for the operation of this microprocessor 21,
Further, a memory (a storage unit for holding history information and a load balance control unit) in which a table as described below is set 2
2 and a control line 30 connecting the microprocessor 21 and the memory 22. The control line 31, the microprocessor 21, and the memory 22 are detecting means for detecting the interface protocol.

The exchange of read / write data between the central processing units 1 to 4 and the semiconductor memory device 16 is performed by the channel interface control units 17 to 20 and the data transfer path 3.
2, the selection circuit 23, the data transfer path 33, the data transfer control circuit 24, the data transfer path 34, the drive interface control unit 25, the data transfer path 35,
Using the data and the microprogram in the memory 22, the microprocessor 21 uses the control lines 26 to 31 to control the execution of commands from the host device, including the exchange of read / write data.

The repeater 13 is a simple signal amplifier or signal converter, a switch such as a director, or the like.

Channel interface control units 17-20
Of the electric channel 5 and the electric cable 9, the electric channel 7 and the electric cable 11, the optical channel 6 and the optical cable 10, the optical channel 8 and the repeater 13 and the optical cables 12 and 14 which are connected to the respective channel interface control units. There is information indicating the information transmission method (interface protocol).

The selection circuit 23 includes an input / output request display register 601 as shown in FIG. 6 and an input / output request selection register 701 as shown in FIG.

2 and 3 are schematic flow charts of the processing of the microprogram stored in the memory 22. Figure 2
3 is a schematic flow of processing of an input / output request from a host device executed by the microprocessor 21, and FIG. 3 is a schematic flow of processing of load balancing executed by the microprocessor 21 (details of step 202 in FIG. 2). Is. Details of the schematic flows of FIGS. 2 and 3 will be described later.

FIG. 4 shows a connection channel judgment table 401.
Is the structure of. The connection channel determination table 401 exists in the memory 22, collects the hardware information of each channel interface control unit 17 to 20 using the control line 31 immediately after the end of the IMPL of the microprogram, and the connection channel determination table 401 is obtained. Stored in. The hardware information is mainly information on the interface protocol (type of connection channel, interface protocol, etc.) of the host device connected to each of the channel interface control units 17 to 20. When the connection channel determination table 401 is expanded, the channel interface control unit 402-402 to the channel interface control unit 20-4
In the semiconductor memory control device 15, there are as many channel interface control units as there are. Each channel interface control unit (channel interface control unit 402 to 40 for channel interface control unit 20)
The hardware information 5) is in bit units or byte units. In this embodiment, it is simply used for determining the electric / optical channel connection.

FIG. 5 shows the structure of the boot history table 501. The activation history table 501 exists in the memory 22 and indicates in bits the channel interface control unit that processed the input / output request immediately before. When the activation history table 501 is expanded, the channel interface controller 17 for 502-
There are as many channel interface control units 505 as there are channel interface control units of the semiconductor memory control device 15. The channel interface control unit 17 502 to the channel interface control unit 20 505 are configured in bit units. By using the boot history table 501, it is possible to determine which channel interface control unit processed the input / output performed immediately before. For example, if the immediately preceding input / output request is made by the channel interface control 17, the channel interface control unit 502 of the activation history table 501 becomes "1".

FIG. 6 shows the structure of the input / output request display register 601. The input / output request display register 601 exists in the selection circuit 23, and the microprocessor 21 controls the control line 26.
Can be used for reference. For details of the input / output request display register 601, the start history table 501
It has the same structure as the above, and is composed of 602 for channel interface control unit 17 to 605 for channel interface control unit 20, and there are as many channel interface control units as the semiconductor memory control device 15. The channel interface control unit 17 602 to the channel interface control unit 20 605 are configured in bit units. The input / output request display register 601 indicates that the input / output request is received by each of the channel interface control units 17 to 20, and there is an input / output request to be processed from the host device. For example, when there is an input / output request from the central processing unit 2 via the optical channel 6 and the optical cable 10, the channel interface controller 18 of the input / output request display register 601.
The application 603 becomes "1". Entry / Exit request display register 601
When there are input / output requests from a plurality of host devices, a plurality of bits of the corresponding channel interface control unit that has an input / output request indicates "1".

FIG. 7 shows the structure of the input / output request selection register 701. The input / output request selection register 701 exists in the selection circuit 23, and the microprocessor 21 controls the control line 26.
It is possible to connect / disconnect to / from the channel interface control unit in which an input / output request exists by writing using the. The details of the input / output request display register 701 have the same structure as the startup history table 501,
It is composed of 702 for channel interface control unit 17 to 705 for channel interface control unit 20, and there are as many as the number of channel interface control units of the semiconductor memory control device 15. 7 for channel interface controller 17
02 to channel interface control unit 705 are configured in bit units. The input / output request selection register 701 is
It shows the connection to the channel interface controller that is currently processing the I / O request. For example, the central processing unit 3
When there is an input / output request via the electric channel 7 and the electric cable 11, the channel interface controller 19 604 of the input / output request register 601 becomes “1”. After that, when processing an input / output request (when connecting to the channel interface controller 19), the input / output request selection register 701 for the channel interface controller 19 is used.
Set 4 to '1'. When the input / output ends and the channel interface control unit 19 is disconnected, the channel interface control unit 19 of the input / output request selection register 701 is used.
04 is set to '0'.

Next, with reference to FIGS. 4 to 7, FIGS.
The process of the general flow of the microprogram will be described.

First, FIG. 2 will be described. Figure 2
6 is a schematic flow chart for processing an input / output request executed by the microprocessor 21. Steps 201 to 2 in FIG.
03, 207 to 208 are parts relating to load balance control,
Steps 204 to 206 are related to heterogeneous interface control. At step 201, the control line 26 is used to fetch the input / output request display register 601 and whether or not there is an input / output request from the host device (the input / output request display register 6
No. 01 for channel interface control unit 17 to 605 for channel interface control unit 20 is “1”). If there is no input / output request from the host device (if the channel interface control unit 17 602 to the channel interface control unit 20 605 of the input / output request display register 601 are all “0”), the input / output from the host device Wait at step 201 until requested. If there is an input / output request from the host device (602-channel interface control 20 for channel interface controller 17 of input / output request display register 601)
If any of the application 605 is "1"), step 2
The process proceeds to 02. In step 202, the channel interface control unit that executes the input / output request is determined from the activation history table 501. Details of this will be described later with reference to FIG.

Next, in step 203, step 202
The information of the channel interface control unit determined in step 1 is set in the input / output request selection register 701 in the selection circuit 23 through the control line 26. That is, step 2
Corresponding to the channel interface control unit determined in 02, any one of the channel interface control unit 17 702 to the channel interface control unit 20 705 in the input / output selection register 701 is set to “1”. In step 204, it is determined using the connection channel determination table 401 whether the channel interface control unit determined in step 202 is connected to the optical channel. If the channel interface controller determined in step 202 is connected to the optical channel, the process proceeds to step 205, and if the channel interface controller determined in step 202 is connected to the electrical channel, the process proceeds to step 206. move on. In step 205, processing for the optical channels 6 and 8 is performed, and an input / output request including read / write data exchange is executed. In step 206, processing for the electric channels 5 and 7 is performed, and an input / output request including read / write data exchange is executed. Step 207
Then, information on the channel interface control unit that has performed the input / output request service is stored in the activation history table 501. That is, among the channel interface control unit 17 502 to the channel interface control unit 20 505 in the boot history table 501, the location corresponding to the channel interface control unit that has performed the input / output service is now set to "
Set to 1 '. In step 207, only the information of the currently serviced channel interface control unit is stored, and the information of the channel interface control unit of the previous input / output request disappears. In step 208, the input / output request selection register 701 is cleared (all '0') to complete the input / output request processing (separate from the channel interface control unit). Then, the process returns to step 201.

Next, FIG. 3 will be described. FIG. 3 is a schematic flow of load balancing processing executed by the microprocessor 21. In step 301, the logical product of the input / output request display register 601 fetched in step 201 and the activation history table 501 is calculated, and it is checked whether or not there is an input / output request in the same channel interface control unit as the channel interface control unit that performed the previous input / output service. To do. if,
If there is an input / output request to the same channel interface control unit as the channel interface control unit that performed the previous input / output service, go to step 303. If there is no input / output request to the same channel interface control unit as the channel interface control unit that performed the previous input / output service, Go to step 302. In step 302, a channel interface control unit having an input / output request other than the channel interface control unit that has just performed the input / output request processing is selected. If there are input / output requests to a plurality of channel interface control units other than the channel interface control unit that has just performed the input / output request processing immediately before, the activation history table 501
Select the channel interface control unit adjacent to the contents of. In this case, the channel interface control unit 17 →
Channel interface control unit 18 → Channel interface control unit 19 → Channel interface 20 → Channel interface 17 is selected (hereinafter abbreviated as selection method 1) and a method reverse to the above (hereinafter abbreviated as selection method 2). .) In the case of the present embodiment, either selection method may be used. For example, if there is an input / output request with the channel interface control units 17, 19 and 20 and the channel interface control unit that performed the previous input / output service is the channel interface control unit 18, the interface control unit 1 in the selection method 1
9 is selected, and in the selection method 2, the channel interface control unit 17 is selected. Further, if there is an input / output request only to the channel interface control unit 20 and the channel interface control unit that performed the previous input / output service is the channel interface control unit 18, the selection method 1
Then, the channel interface control unit 19 should be selected originally, but since the channel interface control unit 19 has no input / output request, the channel interface control unit 20 is selected. The same applies to the selection method 2, and in the above case, since the channel interface control unit 17 has no input / output request, the channel interface control unit 20 is selected.

In step 303, the start history table 5
The channel interface control unit stored in 01 is selected.

In the load balancing process of FIG. 3, it seems that the input / output service of the semiconductor memory control device 15 is deviated to a specific central processing unit at first glance, but if the input / output service ends once, the same central processing is performed. The time until the next I / O request is issued from the processing device is between several tens of microseconds and several milliseconds. Therefore, when the I / O requests from the plurality of central processing units compete with each other, the step 303 is rarely executed, and the step 302 is mostly executed. For this reason, the load can be made uniform even if there are input / output requests (shared) from a plurality of central processing units.

Although the present embodiment is applied to the case where the number of central processing units is four, it is needless to say that the present invention can be applied to the case where the number of central processing units is 4 or more or 4 or less. In addition, in this embodiment, the control line 31 is used to create the connection channel determination table 401.
Although the hardware information was collected by using the above, the semiconductor memory control device 15 is provided with a service processor for controlling various services / initial setting / diagnosis, and the hardware processor is used for the hardware processor. It is also possible to perform mixed control of heterogeneous interface protocols by giving information.

In this embodiment, the channel interface control units 17 to 20 have no local processor.
The present invention can be applied even if the channel interface control units 17 to 20 have a local processor.

Although the present embodiment is an example in which the external storage control device and the external storage device are separated, the present invention is applicable even when the external storage control device and the external storage device are integrated.

Although the present invention is applied to the semiconductor memory device subsystem in the above-described embodiment, it is also applicable to an external memory control device such as a magnetic disk device subsystem and a magnetic tape device subsystem. Applicable.

Although the present invention is applied to the storage control device in the above-mentioned embodiment, it may be applied to information processing devices other than the storage control device, such as a communication control device and a central processing unit. Applicable.

Further, it is possible to apply a load balancing control system as disclosed in Japanese Patent Application No. 3-54232 to the heterogeneous interface control system of the present invention.

As described above, according to this embodiment, the external storage control device has the hardware information indicating the information transmission method (interface protocol) for each information transmission path connected to the external storage control device. As a result, information transmission paths having different information transmission methods (interface protocols) can be connected to the external storage control device and the external storage device.

Further, it becomes possible to carry out detailed load balancing control according to the operating condition of the host device with a small amount of information.

[0046]

According to the present invention, it is possible to provide an information processing apparatus capable of controlling the mixed transmission of information transmission paths of various different interface protocols.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention.

FIG. 2 is a flowchart showing an example of processing of an input / output request according to the present invention.

FIG. 3 is a flowchart showing an example of load balancing processing according to the present invention.

FIG. 4 is an explanatory diagram showing an example of a structure of a connection channel determination table according to the present invention.

FIG. 5 is an explanatory diagram showing an example of a structure of a boot history table according to the present invention.

FIG. 6 is an explanatory diagram showing an example of a structure of an input / output request display register according to the present invention.

FIG. 7 is an explanatory diagram showing an example of a structure of an input / output request selection register according to the present invention.

[Explanation of symbols]

1-4: Central processing unit 5,7: Electric channel 6, 8: Optical channel 9, 11: Electric cable 10, 12, 14: Optical cable 13: Repeater 15: Semiconductor memory control device 16: Semiconductor memory device 17 to 20: Channel interface control unit 21: Microprocessor 22: Memory 23: Selection circuit 24: Data transfer control circuit 25: Drive interface control unit 26-31: Control line 32-35: Data transfer path 401: Connection channel determination table 501: Startup history table 601: Input / output request display register 701: Input / output request selection register

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5B014 GA05 GA15 GA37                 5B061 BA01 BB08 GG13 RR07                 5B065 BA05 CA15 CA19 CC08

Claims (2)

[Claims] 1. A storage control device having a plurality of information transmission paths, and a storage device controlled by the storage control device,
An information processing device having: a plurality of information transmission paths are connected to a host device that inputs and outputs information to and from the storage device via at least two types of different interface protocols, and the storage control device, A plurality of channel interface control units that are connected to the information transmission path and that input and output information corresponding to the interface protocol of the information transmission path; and a detection unit that detects the interface protocol of the plurality of channel interface control units. A load balance control means for performing load balance control between information transmission paths based on the history information; When the channel interface control unit receives a request for input / output processing from the host device, Channel interface control unit determines whether it is the channel interface control unit that received the service for the previous input / output processing request, and the result of this determination is not the channel interface control unit that received the service for the previous input / output processing request. In this case, the input / output processing request is a load balancing unit that selects the channel interface control unit, and the storage control device requests the input / output processing of the channel interface control unit selected by the load balancing unit. An information processing device, characterized in that 2. The load balance control means according to claim 1, wherein, when the result of the determination is a channel interface control which received a service for a request of the input / output processing last time, the other channel interface other than this channel interface control unit. It is further determined whether the control unit has not received the input / output processing request. As a result of this determination, if the other channel interface control unit has received the input / output processing request, the other An information processing apparatus, characterized in that a channel interface control unit is selected.