JPH04288678A - Lag time calculator - Google Patents

Abstract

PURPOSE:To accurately find lag time without necessitating large memory capacity by extracting the feature data of an abstract circuit element converted from operating function specification description, and calculating the lag time of the abstract circuit element based on the data. CONSTITUTION:A design data conversion part 102 performs the syntax analysis of the register transfer description of a register transfer specification 101, and generates an initial abstract circuit with fidelity to the register transfer description, and stores it in a design data base 103. In a lag time setting part 104, an abstract element data extraction part 106 fetches the types and the number of input of all the abstract function elements of the initial abstract circuit, the bit width of input facility, and the bit width of the element itself from the design data base 103. A lag time calculation part 105 calculates the number of delay stages of a target abstract element based on an extracted data group. A lag time data storage part 107 stores a calculation result by conforming to an abstract element to be data-extracted in the design data base 103.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention calculates the individual signal delay times of hardware elements designed using a hardware description language, and calculates the signal delay times based on this. The present invention relates to a delay time calculation device that generates the delay time of a hardware element that is input to a device that analyzes the delay time of an entire circuit expressed in a hardware description language.

(Prior Art) In recent years, due to the need to develop large-scale logic circuits in a short period of time, a design has been made at the operating function level, and a logic circuit has been generated using a logic synthesis device.

However, logic circuits created by skilled circuit designers are
It has better performance (especially operating speed) than automatically synthesized logic circuits. This is because a skilled designer determines the register clock to meet the operating frequency of the circuit and designs the circuit using a logic structure that requires less signal delay time.

On the other hand, the logic synthesis device has also been improved, simplifying the operational function level circuit by expanding it into AND and OR level circuits, decomposing it by deleting redundant circuits and extracting common terms. Furthermore, the timing and number of elements have been optimized through reconfiguration.

In this logic synthesis device, when converting a functional level circuit to a logic level circuit, it is converted to a circuit with a small signal delay time, but which part of the functional level circuit should be converted using this method? There were no indicators. Therefore,
Although it has been considered to predict critical paths and perform conversion using functional level circuits, it has not been known what kind of delay time should be given to circuit elements at that functional level.

On the other hand, regarding the delay time calculation of the constituent elements of the target circuit in a delay time analyzer, for example, in a gate-level delay time analyzer, AND and OR level circuits are counted as one stage (number of gate stages), and are not compiled into a library. There was no device that could calculate the delay time of a hardware element itself at a functional level. In addition, by using delay time analysis tools that use delay data from library cells, it is now possible to obtain detailed analysis results of signal delay times in logic circuits (for example, which paths have the longest delay or the least). (Is it a delay path?), this could only be used in a logic circuit to which specific hardware elements were allocated.

To perform delay time analysis using functional-level hardware elements, create a library of functional-level hardware elements (the number of inputs is variable or the element itself has a bit width). There is a need. however,
Since it is necessary to prepare a huge number of elements in advance according to the number of allowed inputs and bit width, a huge amount of storage capacity is required. Furthermore, regarding how to provide delay information to hardware elements at the functional level, each time a designer inputs a functional block consisting of an element-specific design or wiring diagram using CAD, or each time a functional element is described, Setting a delay time was inefficient in design. Therefore, a method has been desired that predicts the signal delay time after being converted into a logic circuit and automatically allocates the delay time to the functional element.

(Problems to be Solved by the Invention) As described above, in the conventional delay time calculation device, the number of inputs and outputs and the bit width were originally variable. For this reason, for abstract circuits converted from circuits designed with register transfer specifications, it is necessary to provide a delay time to all abstract circuits that can be used with register transfer specifications, and to create a library for each abstract circuit. This required a storage capacity to store a huge amount of data.

The present invention was made in view of the above-mentioned conventional circumstances, and its purpose is to calculate and allocate delay times of hardware with different logical structures to hardware with the same function. An object of the present invention is to provide a delay time calculation device that can automatically calculate the delay time of an abstract circuit element without requiring a huge storage capacity.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention extracts characteristic data of abstract circuit elements constituting a circuit at the operating function specification level or a circuit in the middle of logic synthesis. The method comprises an extraction means, a calculation means for calculating the delay time of the abstract circuit element based on the characteristic data, and an association means for associating that the abstract circuit element has the delay time. .

(Operation) With the above configuration, the present invention extracts the characteristic data of the abstract circuit element converted from the operational function specification description using the extraction means, and calculates the delay of the abstract circuit element based on the extracted characteristic data. Calculate the time by a calculation means. Then, the calculated delay time is assigned to the abstract circuit element using an association means.

(Embodiment) Before explaining the embodiment, a register transfer description will be explained.

In the specific register transfer description used in this invention, facilities (external terminals,
(internal signals, registers, memory, etc.), operators that express functionality without going into hardware details, built-in functions (addition, subtraction, etc.), and processes that express facility operations (such as asynchronous clearing of registers) It is possible to express state transitions. Hereinafter, facilities, operators, built-in functions, processes, and states will be referred to as abstract functional elements. Note that some abstract functional elements have a bit width or the number of inputs is not constant.

Here, the delay time of the abstract functional element will be explained.

Logic synthesis is a process of finally expanding abstract functional elements into logic elements (gates), optimizing them, and allocating hardware library cells of a desired technology to these.

However, the register transfer level circuit is a functional level circuit, and is not necessarily a circuit that is optimized as hardware, that is, a circuit that is designed with consideration to the number of gates or the number of gate stages. Therefore, it is not a good idea to allocate hardware cells to all abstract functional elements from the beginning. Furthermore, even if cells have the same function, the actual delay time will change by allocating cells with different speeds, so it is not appropriate to allocate real time to each abstract functional element of a circuit at the register transfer level. .

Therefore, instead of the delay time, the number of gate stages in units of basic gates is used. Also, the hardware NOR
For gate cells, etc., the actual delay time varies considerably as the number of inputs increases (for example, when the number of inputs increases
(OR has a delay time four times that of two-input NOR), and in such a gate, the number of stages is given in consideration of the number of inputs.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a delay time calculation device of the present invention.

In the figure, a register transfer specification 101 represents a functional operation specification, and is a functional block diagram showing a register transfer description or a register transfer specification in a schematic manner.

A design data conversion unit (translator) 102 parses the register transfer description of the register transfer specification 101 and generates an initial abstract circuit faithful to this register transfer description.

Alternatively, if the register transfer specification 101 is a functional block diagram, the translator 102 extracts network information and graphic information from the schematic diagram to generate an initial abstract circuit.

The design database 103 includes network information of an initial abstract circuit, for example, circuit model information developed by a logic synthesis device (not shown), or register transfer specifications 101.
This is where the converted information is stored.

The delay time setting unit 104 is the central part of the present invention, and is the part that calculates the delay time and stores it. This delay time setting section 104 includes a delay time calculation section 10
5, an abstract element data extraction section 106, and a delay time data storage section 107.

The delay time calculation unit 105 has a function of calculating the number of delay stages of the target abstract element, and in order to flexibly deal with changes in the delay time model of the target abstract element, the delay time calculation unit 105 incorporates the delay time model definition 108. It is created by the time calculation unit generation unit 109.

The delay time calculation unit generation unit 109 has the role of modifying a program that performs delay time calculation according to the variable number of inputs, bit width, etc. of the abstract functional element.

The abstract element data extraction unit 106 uses the translator 102
The types and number of inputs of all abstract functional elements of the initial abstract circuit, the bit width of the input facility, and the bit width of the element itself are extracted from the design database 103 generated in .

Furthermore, since the input facility may be connected to a constant, the abstract element data extraction unit 106 traces the net on the input side for an arbitrary number of stages to determine the type of constant and its information (
For example, if the constant is a binary number, extract the number '1'.

The delay time data storage unit 107 stores the result calculated by the delay time calculation unit 105 based on the data group extracted by the abstract element data extraction unit 106 in the design database 103 in association with the data extracted abstract element. do. Note that the delay time data storage unit 107 does not necessarily need to store the calculated number of delay stages in the design database 103, or the number of delay stages once calculated by the process of the delay time calculation unit 105 may be stored depending on the type of abstract functional element, It is stored in a storage area together with the number of inputs and bit width, and another device (for example, a delay time analyzer) that uses the stored information
If necessary, it is also possible to perform hashing from the abstract functional element data in the design database 103 and retrieve the delay stage number data from the storage area where the information is stored.

Next, the delay time model definition 108 will be explained using FIGS. 2 to 4.

Figure 2 shows register transfer specifications 101 representing functional operation specifications.
It is.

In this register transfer description, GT means a built-in function that compares the magnitude of input facilities A and B;
It has one input and one output. X is a 1-bit facility, which is 1 when A>B and 0 otherwise.

Input facilities A and B each have a bit width, the most significant bit msb1, the least significant bit lsb1,
It has a range of msb2 and lsb2. Note that the bit width is abs(lsb-msb)+1.

3(a) to 3(d) are circuit model diagrams in which the magnitude comparison function GT shown in FIG. 2 is developed into a logic circuit by a logic synthesis device (not shown).

FIGS. 3(a) and 3(b) show 4-bit magnitude comparators (hereinafter referred to as MAG4) 301, 302.
, 304, 305, and a 2-bit magnitude comparator (hereinafter referred to as MAG2) 303. In addition, FIGS. 3(c) and 3(d) show INVERTER306,
R (exclusive OR) 307, AND308, OR309
The circuit model is shown when it is configured with gate circuits.

Here, the magnitude comparator compares two inputs A and B, and if A is larger than B, then A and B
A specific signal is output for each of three cases: when A is equal to B, and when A is smaller than B.

By connecting multiple stages of magnitude comparators, output X is obtained by comparing multi-bit input signals.

The circuit model when the facility of the first argument A and the facility of the second argument B of the function GT are not binary constants or are not equal to binary constants is shown in Figure 3 (
High-performance hardware cell MAG shown in a) and (b)
4 and MAG2. Note that this circuit model assumes a bit width of 4 bits or more.

The method of conversion to a logic circuit dependent on bit width is (1) (
abs(lsb-msb)+1)%4=0(2)(ab
s(lsb-msb)+1)%4=1(3)(abs(
lsb-msb)+1)%4=2(4)(abs(ls
It is necessary to consider four cases: b-msb)+1)%4=3. Here, % represents remainder calculation.

Cases (2) and (3) are converted to the circuit model shown in FIG. 3(a), and cases (1) and (4) are converted to the circuit model shown in FIG. 3(b).

The circuit model shown in FIG. 3(a) is (abs(lsb
-msb)+1)/4 MAG4 and 1 MAG2
It consists of

In the case of (2) above, 1 bit of the 2-bit inputs A and B of MAG2 (303) is connected to GND (ground).

The circuit model shown in FIG. 3(b) converted by the above (1) consists of (abs(lsb-msb)+1)/4 MAG4s.

Moreover, the circuit model converted by (4) is (ab
It is composed of s(lsb-msb)+1)/4+1 MAG4, and one bit of its 2-bit inputs A and B is connected to GND.

On the other hand, the circuit model shown in FIG. 3(c) is a circuit model in which the facility bit width is smaller than 4 bits.

The circuit model in FIG. 3(d) is a model in which the facility of the second argument B of the function GT is connected to a binary constant. In this case, the gate is simplified and XOR3
07 is deleted. That is, when a certain bit of facility B is '0', only INVERTER 306 remains, and when it is '1', nothing remains.

FIG. 4 is a diagram showing a delay time model definition 108 assuming the circuit model shown in FIG. 3. Note that this embodiment will be described assuming that msb<lsb.

FIG. 4(a) is a table showing each gate circuit and its corresponding number of stages.

As shown in the figure, NULL means 0 stages necessary for the description, AND, OR, AND3, OR3, AND4, O
R4 has one stage. INV (INVERTER) is 1
If there are 2 pieces, it is 0 stages, and if there are 2 pieces, it is 1 stage. Also, XO
R is 2 stages, MAG2 is 3 stages with library cells, MAG4
There are 5 stages. Note that calculation of the number of stages of library cells will be described later.

FIG. 4(b) shows the function GT shown in FIG.
This is a descriptive text that defines the circuit model shown in the figure.

In this description, arg[n] indicates the nth argument,
BNUM indicates a binary constant {0, 1}. Also, Q
NUM is a four-value constant {0, 1, ? (don't car
e), Z (high impedance)}. If statement, comparison statement, conjunction, or disjunction is C
It can be written in a language-like manner. Note that / means division, and % means remainder calculation.

The descriptive text 401 is based on the conditions of the circuit model shown in FIGS. 3(a) and 3(b), and the first argument A and the second argument B of the function GT are BNUM.
However, the case where it is not QNUM is shown.

A descriptive text 402 indicates a case where the bit width is 4 or more, and a descriptive text 403 indicates a case where the remainders when the bit width is divided by 4 are 1 and 2.

The part surrounded by “{}” in the descriptive sentence 404 is
The number of MAG4s located to the left of is shown. Also,"
The part surrounded by "[]" indicates the series combination of gates, that is, the sum of the number of gate stages.In other words, the description 404 is (lsb-msb+2)/4 MAG4 and one M
This shows that it is a circuit model in which AG2 is connected.

The description 405 is for a case where the bit width is divided by 4 and the remainders are 0 and 3, and MAG4 has the number of stages of (lsb-msb+2)/4.

The descriptive text 406 shows the case where the bit width is 3, and the number of stages is INV, XOR, AND, as shown in the descriptive text 407.
4. It is obtained from a circuit model in which OR3 is connected in series.

Below, descriptive sentences 408 to 411 are model definitions when the bit width is 2 and 1.

In the descriptive text 412, the facility of the second argument B is BNU.
This shows the conditions when connected to M or QNUM.

A descriptive text 413 indicates a case where the bit width is 4 or more.

The descriptive text 414 is the circuit model shown in FIG. 3(d).
It shows the maximum number of stages from input A to output
It is composed of 1)/log(4.1)+1 4-input AND and 4-input OR.

The descriptive sentences 415 to 418 have a bit width of 3 bits and 2 bits, and the descriptive sentence 419 has a bit width of 1 bit.

The value of '1' for the facility connected to the second argument B is 1.
If there are more than
When there are 0, it becomes a NULL gate, that is, 0 stage (description 422).

Although the circuit model for the maximum delay stage number has been explained here, the label of the function GT is GT(max), GT
(min), and the number of stages with the minimum delay can also be defined by similarly defining the following.

Further, here, a case is shown in which one representative circuit model is defined for the number of delay stages of an abstract functional element.

However, if the input/output facilities of this abstract functional element are referenced with different range widths, it is also possible to treat each facility as a different terminal. That is, for example, input facility A for descriptive text is
If the range is divided into A<0:3> and A<4:6> and used, the keyword GT is GT::<msb
:msb+3> and GT::<msb+4:msb+6
>, it is also possible to define a circuit model from A<0:3> to output X and a circuit model from A<4:6> to output X.

Furthermore, for library cells such as MAG2 and MAG4, the number of delay stages can be automatically calculated by defining the primitive gates forming the library cells as shown in FIG. 4(b).

Similarly, for abstract functional elements generated during logic synthesis, the number of delay stages can be automatically calculated by defining a model as shown in FIG. 4(b).

A delay time calculation unit generation unit 109 analyzes the model definition and generates a delay time calculation unit 105 that calculates the number of stages of the defined abstract functional element.

Furthermore, the delay time setting section 104 actually calculates the number of delay stages. Now, B<1:8>=8B11000000;X=GT(A<
It is assumed that a register transfer specification 101 such as 0:7>, B<1:8>) is stored in the design database 103.

The abstract element data extraction unit 106 extracts the function type G
It is extracted that T, the bit width of 8, and the connection destination of the second argument are BNUM. Furthermore, the delay time calculation unit 105
In this step, the delay time is calculated according to the model definition of descriptive sentences 412 and 413 in FIG. 4(b).

If log(8)/log(4.1)+1 is rounded down to the nearest decimal point and becomes 2, then 2 digits are required for both AND4 and OR4, but since both AND4 and OR4 are 1 stage, the final result is 4 stages. . The delay time calculated in this manner is stored in the design database 103 in association with the function GT.

In this embodiment, an example of a built-in function is shown, but the present invention is not limited to this, and the present invention can also define a similar delay time model for operators, processes, and states. This makes it possible to calculate the delay times of all abstract functional elements used in the operational functional specifications.

[Effects of the Invention] As described above, according to the delay time calculation device of the present invention, a delay time model is defined separately from the operational function specifications, and a delay time calculation section is automatically generated.

This eliminates the need for designers to consider delay times.
Furthermore, there is no need to modify the equipment due to changes in the delay time model definition, resulting in good design efficiency.

Furthermore, it eliminates the need for storage capacity to store a library of functional elements that take delay times into account, and the delay time model definition allows the simplified circuit model of the logic synthesizer to be described, allowing accurate delay time calculations. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the delay time calculation device of the present invention, FIG. 2 is a descriptive text showing register transfer specifications, and FIGS. The circuit model diagrams shown in FIGS. 4(a) and 4(b) corresponding to the register transfer specification description are descriptions for explaining the delay time model definition. 101...Register transfer specification 102...Design data conversion unit (translator) 103...
Design database 104...delay time setting section 105...delay time calculation section 106...abstract element data extraction section 107...delay time data storage section 108...delay time model definition 109...delay time calculation section generation section 301, 302, 304, 305... MAG4 (4-bit magnitude comparator) 303...MAG2 (2
bit magnitude comparator) 306...INVERTER gate circuit 307...XOR (exclusive OR) gate circuit 308...A
ND gate circuit 309...OR gate circuit attorney Hidekazu Miyoshi

Claims (1)

[Scope of Claims] Extraction means for extracting characteristic data of an abstract circuit element constituting a circuit at the operating function specification level or a circuit in the middle of logic synthesis; and a delay time of the abstract circuit element based on the characteristic data. and an association means for associating that the abstract circuit element has the delay time, and calculating the delay time of the abstract circuit element by incorporating hardware specifications. Delay time calculation device.