JPH04287918A - Etching method of semiconductor multilayer film - Google Patents

Etching method of semiconductor multilayer film

Info

Publication number
JPH04287918A
JPH04287918A JP643791A JP643791A JPH04287918A JP H04287918 A JPH04287918 A JP H04287918A JP 643791 A JP643791 A JP 643791A JP 643791 A JP643791 A JP 643791A JP H04287918 A JPH04287918 A JP H04287918A
Authority
JP
Japan
Prior art keywords
etching
multilayer film
semiconductor multilayer
mixed crystal
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP643791A
Other languages
Japanese (ja)
Inventor
Yuichi Ide
雄一 井手
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP643791A priority Critical patent/JPH04287918A/en
Publication of JPH04287918A publication Critical patent/JPH04287918A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To acquire a processing surface without irregularities in a sidewall by providing both a process for forming a mixed crystal part by inducing mutual diffusion in a part of a semiconductor multilayer film and a process for acquiring a desired mesa structure by etching the mixed crystal part alone. CONSTITUTION:A semiconductor multilayer film structure 2 is formed which consists of a 200A-thick GaAs layer 2a and a 200A-thick AlAs layer 2b laminated alternately on a GaAs substrate 1. Then, an SiO2 film is deposited by CVD method. A 2mum-diameter circular SiO2 mask 3 is formed by selectively etching the SiO2 film by hydrofluoric acid water solution using a photoresist as a mask. Thereafter, Zn is introduced by removing and thermally treating the circular SiO2 mask 3 after ion implantation of Zn and mutual diffusion of GaAs and AlAs is induced to make the region an Al0.5Ga0.5As mixed crystal part 4. Etching is performed vertically to a depth of 2.2mum by RIBE method using Cl<-> to form a cylinder of the semiconductor multilayer film 2.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体基板に成長した半
導体多層膜の選択エッチングに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to selective etching of semiconductor multilayer films grown on semiconductor substrates.

【0002】0002

【従来の技術】半導体基板表面に形成された半導体多層
膜を用いたデバイスとして、基板面に垂直にレーザ光を
発する面発光レーザが知られ、研究開発が盛んに行なわ
れている。
2. Description of the Related Art Surface-emitting lasers, which emit laser light perpendicular to the substrate surface, are known as devices using a semiconductor multilayer film formed on the surface of a semiconductor substrate, and are being actively researched and developed.

【0003】例えばJ.L.Jewel  et  a
lは第7回光集積および光通信国際会議(7th  I
nt.  Conf.  on  IOOC,  Di
gest,  vol.5,  p.8〜9)において
、GaAsおよびAlAs23周期の半導体多層膜から
なるレーザ反射鏡を用いた面発光レーザを紹介している
For example, J. L. Jewel et a
7th International Conference on Optical Integration and Optical Communications (7th I
nt. Conf. on IOOC, Di
gest, vol. 5, p. 8 to 9) introduce a surface-emitting laser using a laser reflecting mirror made of a semiconductor multilayer film of GaAs and AlAs with 23 periods.

【0004】面発光レーザにおいては発信閾値電流を下
げるために、半導体多層膜が直径1〜5μm、高さ数μ
mの円柱状に加工されている。
In surface emitting lasers, in order to lower the emission threshold current, the semiconductor multilayer film has a diameter of 1 to 5 μm and a height of several μm.
It is processed into a cylindrical shape of m.

【0005】[0005]

【発明が解決しようとする課題】半導体多層膜を加工す
るため、通常Cl2などの反応性ガスを用いたドライエ
ッチング、例えば反応性イオンビームエッチング(RI
BE)、ケミカリアシステッドイオンビームエッチング
(CAIBE)などが用いられる。
[Problems to be Solved by the Invention] In order to process semiconductor multilayer films, dry etching using a reactive gas such as Cl2, such as reactive ion beam etching (RI), is usually used.
BE), chemical assisted ion beam etching (CAIBE), etc. are used.

【0006】これら従来のエッチング法では、エッチン
グ速度が半導体の組成に依存する傾向がある。
In these conventional etching methods, the etching rate tends to depend on the composition of the semiconductor.

【0007】浅川らは応用物理vol.54,  no
.11,  1985,  pp.1136〜1153
において、特にGaAsとAlAsとの場合は、エッチ
ング室内の到達真空度が10−7Torrよりも良くな
いと、残留水分が影響してAlAsのエッチング速度が
極度に小さくなることを報告している。
Asakawa et al. Applied Physics vol. 54, no
.. 11, 1985, pp. 1136-1153
reported that, particularly in the case of GaAs and AlAs, if the ultimate vacuum in the etching chamber is not better than 10-7 Torr, the etching rate of AlAs becomes extremely low due to the influence of residual moisture.

【0008】これらの現象のために半導体多層膜をエッ
チングすると側壁が凹凸になって、平滑な加工面が得ら
れないという問題があった。
[0008] Due to these phenomena, when a semiconductor multilayer film is etched, the side wall becomes uneven, and a smooth processed surface cannot be obtained.

【0009】またエッチング室内の残留水分が充分少な
くても、エッチング終了後に加工面上に吸着して残存し
ている塩素成分によって、加工済みウェーハを大気中に
取出したとき、AlAsが選択的に反応して、最終的に
凹凸が形成されてしまうという問題がある。
Furthermore, even if the residual moisture in the etching chamber is sufficiently low, AlAs may selectively react with the chlorine component adsorbed and remaining on the processed surface after etching when the processed wafer is taken out into the atmosphere. As a result, there is a problem in that unevenness is ultimately formed.

【0010】このように従来のエッチング方法では、半
導体多層膜に対して平滑な加工面を得ることは難しく加
工形状の制御が困難で、デバイス性能に悪影響を与えて
いた。
As described above, in the conventional etching method, it is difficult to obtain a smooth processed surface of a semiconductor multilayer film, and it is difficult to control the processed shape, which adversely affects device performance.

【0011】本発明の目的は制御性良く平滑な加工面が
得られる実用化が容易で信頼性の高い半導体多層膜のエ
ッチング方法を堤供することにある。
An object of the present invention is to provide a method for etching a semiconductor multilayer film that is easy to put into practical use and that provides a smooth processed surface with good controllability and is highly reliable.

【0012】0012

【課題を解決するための手段】本発明の半導体多層膜の
エッチング方法は、第1の半導体層と該第1の半導体層
と異なる禁制帯幅を有する第2の半導体層とが交互に積
層された半導体多層膜をエッチングする方法において、
前記半導体多層膜の一部に相互拡散を誘起させて混晶部
を形成させる工程と、該混晶部のみをエッチングして所
望のメサ構造を得る工程とからなるものである。
[Means for Solving the Problems] A method for etching a semiconductor multilayer film of the present invention includes a method in which a first semiconductor layer and a second semiconductor layer having a different forbidden band width from the first semiconductor layer are alternately stacked. In a method of etching a semiconductor multilayer film,
This method consists of a step of inducing interdiffusion in a part of the semiconductor multilayer film to form a mixed crystal part, and a step of etching only the mixed crystal part to obtain a desired mesa structure.

【0013】[0013]

【作用】従来のエッチング方法の問題点は、半導体多層
膜を構成する半導体層の組成の違いによりエッチヤント
との反応速度が異なることによっている。
[Operation] The problem with the conventional etching method is that the reaction rate with the etchant differs depending on the composition of the semiconductor layers constituting the semiconductor multilayer film.

【0014】本発明においては、加工面となる領域に予
め相互拡散を誘起して多層膜構造を崩し、ほぼ単一構成
の混晶にしてしまうことにより、反応速度の組成依存性
を解消している。
In the present invention, the dependence of the reaction rate on the composition is eliminated by inducing interdiffusion in advance in the region to be processed, thereby breaking the multilayer film structure and creating a mixed crystal with an almost single composition. There is.

【0015】[0015]

【実施例】本発明の一実施例について、図1(a)〜(
e)を参照して説明する。
[Example] Regarding an example of the present invention, FIGS. 1(a) to (
This will be explained with reference to e).

【0016】はじめに図1(a)に示すように、GaA
s基板1上に交互に積層した第1の半導体層である厚さ
200AのGaAs層2aと第2の半導体層である厚さ
200AのAlAs層2bとからなる半導体多層膜構造
2が成長されている。
First, as shown in FIG. 1(a), GaA
A semiconductor multilayer film structure 2 consisting of a GaAs layer 2a with a thickness of 200A as a first semiconductor layer and an AlAs layer 2b with a thickness of 200A as a second semiconductor layer is grown on an s-substrate 1. There is.

【0017】つぎに図1(b)に示すように、CVD法
によりSiO2 膜を堆積する。フォトレジスト(図示
せず)をマスクとして弗酸水溶液によりSiO2 膜を
選択エッチングして、直径2μmの円形のSiO2マス
ク3を形成する。
Next, as shown in FIG. 1(b), a SiO2 film is deposited by CVD. Using a photoresist (not shown) as a mask, the SiO2 film is selectively etched with an aqueous hydrofluoric acid solution to form a circular SiO2 mask 3 with a diameter of 2 .mu.m.

【0018】つぎに図1(c)に示すように、Znをイ
オン注入してから円形のSiO2 マスク3を除去して
熱処理することによりZnを導入してGaAsとAlA
sとの相互拡散を誘起し、この領域をAl0.5 Ga
0.5 As混晶部4とする。Znは横方向にも拡散し
て、Al0.5 Ga0.5 As混晶部4は円形マス
ク3の下に少し入り込んでいる。
Next, as shown in FIG. 1(c), after Zn is ion-implanted, the circular SiO2 mask 3 is removed and heat treatment is performed to introduce Zn and form GaAs and AlA.
s and induces mutual diffusion with Al0.5 Ga.
0.5 As mixed crystal part 4. Zn is also diffused in the lateral direction, and the Al0.5 Ga0.5 As mixed crystal portion 4 slightly enters under the circular mask 3.

【0019】つぎに図1(d)に示すように、Cl+ 
を用いたRIBE法により深さ2.2μmまで垂直にエ
ッチングして半導体多層膜2の円柱を形成した。このと
き加工面にAl0.5 Ga0.5 As混晶部4が露
出することになり、従来エッチングのあと大気中でAl
Asが選択的に反応して凹凸が形成されるという問題が
解決した。
Next, as shown in FIG. 1(d), Cl+
A cylinder of the semiconductor multilayer film 2 was formed by vertical etching to a depth of 2.2 μm using the RIBE method. At this time, the Al0.5 Ga0.5 As mixed crystal part 4 is exposed on the processed surface, and conventionally, after etching, Al
The problem of As selectively reacting and forming unevenness has been solved.

【0020】つぎに図1(e)に示すように、弗酸水溶
液で洗浄してSiO2 マスク3を除去することにより
、凹凸のない平滑な側面を有するGaAs/AlAs半
導体多層膜2の円柱が得られる。
Next, as shown in FIG. 1(e), by removing the SiO2 mask 3 by cleaning with an aqueous hydrofluoric acid solution, a cylinder of the GaAs/AlAs semiconductor multilayer film 2 having smooth side surfaces with no unevenness is obtained. It will be done.

【0021】本実施例では混晶化の工程としてZnの熱
酸化を用いたが、相互拡散を引き起すことができる他の
不純物として例えばSiなどを用いることもできる。ま
たイオン注入により不純物を導入したのち熱処理する方
法も有効である。
In this embodiment, thermal oxidation of Zn was used as the mixed crystallization step, but other impurities capable of causing interdiffusion, such as Si, may also be used. Also effective is a method of introducing impurities by ion implantation and then performing heat treatment.

【0022】さらに意図的な不純物導入が好ましくない
場合は、熱処理のみにより相互拡散させることもできる
。これはSiO2 あるいはSi3N4 膜を混晶化さ
せたい領域の上に形成して、800℃程度の熱処理を行
なう。このとき生じるSiおよびGaの拡散に伴なう増
速拡散現象を利用している(キャップアニール混晶化法
)。
Furthermore, if intentional introduction of impurities is not desirable, interdiffusion can be achieved only by heat treatment. This is done by forming a SiO2 or Si3N4 film on the region where mixed crystal formation is desired, and then heat-treating it at about 800°C. The accelerated diffusion phenomenon accompanying the diffusion of Si and Ga that occurs at this time is utilized (cap annealing mixed crystallization method).

【0023】一方エッチング方法としては、本実施例の
RIBE法の代りにRIE法、CAIBE法など他のド
ライエッチング法を用いることもできる。またCl2 
などの反応性ガスを集束イオンビーム、あるいは集束イ
オンビームと組み合わせて用いる直描方式のエッチング
法を適用することもできる。さらに場合によっては、化
学的なガスエッチング法やウェットエッチング法を単独
で、あるいは他のドライエッチングと併用して用いるこ
ともできる。
On the other hand, as an etching method, other dry etching methods such as RIE method and CAIBE method can be used instead of the RIBE method of this embodiment. Also Cl2
It is also possible to apply a direct writing etching method using a focused ion beam or a combination of a focused ion beam and other reactive gases. Further, depending on the case, a chemical gas etching method or a wet etching method may be used alone or in combination with other dry etching methods.

【0024】また本実施例で用いた円形のSiO2 マ
スクの代りに、平面形状を多角形やストライプ状にする
こともできる。マスク材質としてSiO2 の代りに、
Si3 N4 など他の誘電体、絶縁体あるいは金属を
用いても、同様の効果を得ることができる。
Furthermore, instead of the circular SiO2 mask used in this embodiment, the planar shape may be polygonal or striped. Instead of SiO2 as the mask material,
Similar effects can be obtained using other dielectrics, insulators, or metals such as Si3N4.

【0025】[0025]

【発明の効果】半導体基板上に形成された半導体多層膜
構造において、混晶化させた領域のみを選択的にエッチ
ングすることによって、側壁に凹凸のない平滑な加工面
を得ることができた。
Effects of the Invention In a semiconductor multilayer film structure formed on a semiconductor substrate, by selectively etching only the mixed crystal region, it was possible to obtain a smooth processed surface with no unevenness on the sidewalls.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例を工程順に示す断面図である
FIG. 1 is a cross-sectional view showing an embodiment of the present invention in the order of steps.

【符号の説明】[Explanation of symbols]

1    半導体基板 2    半導体多層膜 2a    GaAs層 2b    AlAs層 3    SiO2 マスク 4    混晶部 1 Semiconductor substrate 2 Semiconductor multilayer film 2a GaAs layer 2b AlAs layer 3 SiO2 mask 4 Mixed crystal part

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】  第1の半導体層と該第1の半導体層と
異なる禁制帯幅を有する第2の半導体層とが交互に積層
された半導体多層膜をエッチングする方法において、前
記半導体多層膜の一部に相互拡散を誘起させて混晶部を
形成させる工程と、該混晶部のみをエッチングして所望
のメサ構造を得る工程とからなることを特徴とする半導
体多層膜のエッチング方法。
1. A method for etching a semiconductor multilayer film in which a first semiconductor layer and a second semiconductor layer having a different forbidden band width from the first semiconductor layer are alternately stacked. A method for etching a semiconductor multilayer film, comprising a step of inducing interdiffusion in a part to form a mixed crystal part, and a step of etching only the mixed crystal part to obtain a desired mesa structure.
【請求項2】  混晶部を形成する工程が、不純物元素
の選択的熱拡散、不純物イオンの注入、熱処理のうち1
つ以上からなる請求項1記載の半導体多層膜のエッチン
グ方法。
2. The step of forming the mixed crystal portion includes one of selective thermal diffusion of impurity elements, implantation of impurity ions, and heat treatment.
2. The method of etching a semiconductor multilayer film according to claim 1, comprising at least three steps.
【請求項3】  荷電粒子を用いたドライエッチングに
よって混晶部をエッチングする請求項1記載の半導体多
層膜のエッチング方法。
3. The method of etching a semiconductor multilayer film according to claim 1, wherein the mixed crystal portion is etched by dry etching using charged particles.
【請求項4】  半導体多層膜上に形成した薄膜をマス
クとして不純物をドープする工程と、前記薄膜をマスク
として前記半導体多層膜を選択エッチングする請求項1
記載の半導体多層膜のエッチング方法。
4. The step of doping impurities using a thin film formed on the semiconductor multilayer film as a mask, and selectively etching the semiconductor multilayer film using the thin film as a mask.
The method of etching a semiconductor multilayer film described above.
JP643791A 1991-01-23 1991-01-23 Etching method of semiconductor multilayer film Pending JPH04287918A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP643791A JPH04287918A (en) 1991-01-23 1991-01-23 Etching method of semiconductor multilayer film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP643791A JPH04287918A (en) 1991-01-23 1991-01-23 Etching method of semiconductor multilayer film

Publications (1)

Publication Number Publication Date
JPH04287918A true JPH04287918A (en) 1992-10-13

Family

ID=11638379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP643791A Pending JPH04287918A (en) 1991-01-23 1991-01-23 Etching method of semiconductor multilayer film

Country Status (1)

Country Link
JP (1) JPH04287918A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007078679A (en) * 2005-08-16 2007-03-29 National Institute Of Advanced Industrial & Technology Standard specimen for probe geometry evaluation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007078679A (en) * 2005-08-16 2007-03-29 National Institute Of Advanced Industrial & Technology Standard specimen for probe geometry evaluation

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