JPH04287441A - Follow-up clock generating circuit - Google Patents

Abstract

PURPOSE:To offer the follow-up clock generating circuit at a low manufacture cost for plural TDM equipments or the like whose processing speed is equal to a line speed with respect to the follow-up clock generating circuit having a network port whose line speed is variable. CONSTITUTION:The above circuit is provided with a variable frequency divider section 11 frequency-dividing a line signal by 1/N, a PLL circuit 12 applying phase lock to an output signal of the variable frequency divider section by using a signal of a prescribed lock frequency, a timing generating section 2 generating a phase control signal and a clock generating section 13 generating a tracking clock signal with a width equivalent to the prescribed number of output pulses for each count of an output pulse of the PLL circuit 12 by the prescribed number of counts from a change point of the phase control signal from the timing generating section 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a follow-up clock generation circuit for a network port with variable line speed.

0002

2. Description of the Related Art In recent years, there has been a demand for network ports for time division multiplexing (TDM) devices connected to high-speed digital lines that can support various line speeds. Therefore, it is necessary to extract a follow-up clock that is a follow-up source of the TDM device in order for the TDM device to perform slave synchronization for each line speed at each network port in the TDM device.

As shown in FIG. 4, a conventional follow-up clock generation circuit provided in a TDM device has a line extraction clock frequency of, for example, 64 KHz, 128 KHz, or 256 KHz.
Follow-up clock generation sections 1-1, 1-2, . This prevents data burst errors when switching the follow-up clock due to line failure or the like.

Each follow-up clock generating section 1-i in FIG. 4 shifts the phase control signal of the timing generating section 2 every time a line signal (clock) pulse is input, as shown in FIG.
Bit shift register 11, m-bit shift register 1
1 output change, that is, from “1” (high level) to “0”
A differentiation circuit 12 that detects a change to "low level", a counter 13 that starts counting at the output of the differentiation circuit 12, and a flip-flop 1 that is set by the output of the counter 13.
4, and an n-bit shift register 15 that shifts the output of the counter 13 using a pulse of a line signal (clock).
It becomes more. The flip-flop 14 is reset by the output of the n-bit shift register 15.

That is, as shown in FIG. 6, after the phase control signal (FIG. 6A) from the timing generator 2 becomes "0" (low level), the number of pulses of the line signal (clock) is m. Then (Fig. 6(B)), flip-flop 1
4 is set (FIG. 6(C)), and then, when the number of pulses of the line signal (clock) reaches n (FIG. 6(B)), the flip-flop 14 is reset (FIG. 6(C)). As a result, as shown in FIG. 6(C), a tracking clock signal whose phase is synchronized with the phase control signal shown in FIG. 6(A) is obtained,
It will be sent to the timing generator 2.

Here, FIGS. 6(B) and 6(C) are for a fast line signal (clock) X, for example, 512 KHz, and FIGS. 6(D) and (E) are for a slow line signal (clock) However, there is a large discrepancy between them.

[0007]

[Problems to be Solved by the Invention] However, in the network port of a TDM device with multiple line speeds, as shown in FIG. 6, the width of the line clock changes depending on the line speed. In order to extract a tracking clock at a constant position and a constant width, the m bit and n bit in FIG. 6 must be changed in accordance with each line speed. As a result, it is necessary to provide a number of follow-up clock generation units (hardware) depending on the type of line speed, which poses a problem of increased manufacturing costs.

[0008] Accordingly, an object of the present invention is to provide a follow-up clock generation circuit at low manufacturing cost for TDM devices and the like in which multiple line speeds exist.

[0009]

Means for Solving the Problems A means for solving the above problems is shown in FIG. That is, the variable frequency divider divides the line signal by 1/N, and the PLL circuit synchronizes the phase of the output signal of the variable frequency divider with a signal having a predetermined pull-in frequency, for example, 8 KHz. Further, the timing generator generates a phase control signal. As a result, the clock generation section generates a follow-up clock signal having a width of a predetermined number of output pulses of the PLL circuit every predetermined number of times from the change point of the phase control signal from the timing generation section.

0010

[Operation] According to the above-mentioned means, the output frequency of the PLL section is constant regardless of the frequency of the line clock, so the clock generation section has a fixed position and a fixed width with respect to the phase control signal of the timing generation section. A tracking clock signal is obtained.

[0011]

Embodiment FIG. 2 is a block circuit diagram showing an embodiment of a follow-up clock generation circuit according to the present invention. In FIG. 2, each line speed is, for example, 64 KHz, 128 KHz,
Follow-up clock generation units 1-1, 1-2, . . . are provided for 256 KHz, 512 KHz. In the present invention, each tracking clock generation section 1-1, 1-2, . . . includes a variable frequency division section 11, a PLL section 12, and a clock generation section 13 having the same configuration.

The variable frequency divider 11 has a line speed setting input terminal (for example, for 2 bits), which allows the frequency division ratio to be set to 1/8, 1/16, 1/32, and 1/64. can do. For example, the line clock frequency is 64KHz.
The variable frequency divider 11 of the follow-up clock generator 1-1 has a frequency division ratio of 1/8, and the line clock frequency is 128KH.
Variable frequency dividing unit 11 of follow-up clock generation unit 1-2 for z
is a division ratio of 1/16, and the line clock frequency is 256
The variable frequency divider 11 of the follow-up clock generator 1-3 for KHz has a frequency division ratio of 1/32, and the line clock frequency 5
The variable frequency division section 11 of the follow-up clock generation section 1-4 for 12 KHz has a frequency division ratio of 1/64.

The PLL section 12 has a predetermined pull-in frequency of, for example, 8 KHz, and divides this frequency by a fixed frequency division ratio, for example, 1/193 to output an output signal of 1.544 MHz. The clock generation section 13 has the same configuration as the conventional follow-up clock generation section (FIG. 4), but in this case,
The values of m and n are the same regardless of the frequency of the line clock. In other words, the clock generation section 13 has exactly the same configuration for each line speed.

FIG. 3 is a timing diagram illustrating the operation of the circuit shown in FIG. Each tracking clock generation unit 1-1, 1-2,...
, the fixed clock frequency is 1.5 from the falling edge of the phase control signal from the timing generator 2 shown in FIG. 3(A).
After m (for example 10) pulses of 44 MHz,
A follow-up clock signal for n (for example, 3) pulses is generated (FIGS. 3B and 3C). This is common to all of the follow-up clock generation units 1-1, 1-2, .

In the above embodiment, the pull-in frequency of the PLL section 12 and the phase control signal from the timing generating section 2 are the same, but in the present invention, they do not necessarily have to be the same.

[0016]

As explained above, according to the present invention, even if the types of line clock frequencies increase, the number of hardware of the same configuration can be increased, so manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing the basic configuration of the present invention.

FIG. 2 is a block circuit diagram showing an embodiment of a follow-up clock generation circuit according to the present invention.

FIG. 3 is a timing diagram showing the circuit operation of FIG. 2;

FIG. 4 is a block circuit diagram showing a conventional tracking clock generation circuit.

FIG. 5 is a partial detailed circuit diagram of FIG. 4;

FIG. 6 is a timing diagram showing the circuit operation of FIG. 4;

[Explanation of symbols]

11...Variable frequency dividing section 12...PLL section 13...Clock generation section 2...Timing generation section

Claims (1)

[Claims] 1. A variable frequency divider (11) that divides a line signal by 1/N, a PLL circuit (12) that synchronizes the output signal of the variable frequency divider in phase with a signal of a predetermined pull-in frequency, A timing generator (2) that generates a control signal, and a timing generator (2) that generates a control signal, and
A follow-up clock generation circuit comprising: a clock generation unit (13) that generates a follow-up clock signal having a width of a predetermined number of output pulses of the circuit every predetermined number of times the output pulse is counted.