JPH04286778A - Magnetic recording device - Google Patents

Abstract

PURPOSE:To simplify an entire configuration by converting input data into the input data for plural channels having a prescribed bit length, adding an error detection and correction code for each channel, conducting an interleaving processing and converting the obtained input data into one channel of recording data. CONSTITUTION:A conversion means 22 converting the consecutively inputted input data into the input data for plural channels with the prescribed bit length, plural encoders 32A, 32B, 32C and 32D adding an error detection and correction code C3 to the input data for each of the plural channels, and plural interleaving processing means 33AA, 33AB, 33AC and 33AD conducting the interleaving processing for the input data and the correction code C3 for each of the plural channels are provided, and the outputs of these means are consecutively outputted in a prescribed order. A data conversion means 33C converting the input data for the plural channels and the correction code C3 which are processed by the interleaving processing means 33AA to 33AD into the recording data for one channel, and a magnetic recording means 13 recording the recording data on the magnetic tape, are provided.

Description

[Detailed description of the invention]

0001

[Table of Contents] The present invention will be explained in the following order. Industrial application field Conventional technology (Figs. 21 and 22) Problems to be solved by the invention (Figs. 21 and 22) Means for solving the problems (Fig. 13) Effect (Fig. 13) Example (1) Overall configuration (Figures 1 to 6) (2) Interleave processing (Figures 8 to 12) (3) Parallel processing (Figures 8, 13 to 16) (4) Playback start processing (Figure 8) (5) Buffer memory configuration (Figures 8 and 17) (6)
Test mode (FIGS. 8, 18 and 19) (7) Unload processing (FIGS. 2, 8 and 20) (8) Effects of the embodiments (9) Effects of the invention of other embodiments

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording device, and can be applied to, for example, an external storage device for a computer.

0003

2. Description of the Related Art Conventionally, in this type of magnetic recording device, data is stored in the so-called ID-1 format, in which recording tracks are sequentially formed diagonally on a magnetic tape to enable high-density recording and reproduction of desired data. A recorder has been proposed (ANSI x3.175-1990 19mm
Type ID-1 Recorded Instrument
(entation).

That is, as shown in FIG. 21, in this type of data recorder, a magnetic tape 1 is wound around a rotating drum that rotates at a predetermined speed, and by running the magnetic tape 1 at a predetermined speed, the magnetic tape 1 is moved around the rotating drum. The mounted magnetic head sequentially records recording tracks TR (TR1) diagonally.
, TR2, TR3, TR4, TR1, TR2, . . . ), thereby recording desired data on the recording track TR1. Furthermore, at this time, the data recorder forms recording tracks TA, CTL, and TC extending in the longitudinal direction at the upper and lower ends of the magnetic tape 1, and
The track set ID of the recording track TR is recorded in the track set ID.

[0005] Here, the track set ID is absolute position information starting from the beginning of the magnetic tape 1, and is inserted between predetermined synchronization signals and is recorded on the recording track TR at four track cycles. There is. Furthermore, the recording tracks TA and TC are designed to be able to record user management data, etc.
By reproducing the TL and TC, data recorded at high density on the recording track TR can be easily searched.

Furthermore, in the data recorder, when recording data on the recording track TR, the data is recorded with a parity code for error detection and correction, which is a so-called product code. It is designed to ensure reliable recording and reproduction. That is, Figure 22
As shown in , the data recorder has a predetermined unit (=36,1
08 [BITE]) After importing the data DATA,
The data DATA is divided into 306 blocks, and each block is divided into 306 blocks.
n) error detection and correction code (i.e. C2 code)
Add.

Further, after dividing the block into first and second fields FIELD0 and FIELD1, a Reed-Solomon error detection and correction code (that is, a C1 code) is applied to each field FIELD0 and FIELD1 so as to be orthogonal to the C2 code. ) is added. This allows the data recorder to improve the bit error rate by correcting errors in reproduced data using the C1 and C2 codes during reproduction.

Furthermore, in the data recorder, when recording the data DATA to which the C1 and C2 codes have been added in this way onto the magnetic tape 1, interleaving processing is performed for each recording track TR, and as a result, even if a dropout occurs, the interleaving process is performed. , the data DATA can be reliably reproduced. That is, in the data recorder, arrows a1, a2, ..., an-1, an, a
For the data DATA input in the order shown by n+1, an+2, ... ax-1, ax,
As shown by b2, .

Furthermore, at this time, in the data recorder, a synchronizing signal SYNC and a sync block data ID are added to each predetermined unit (hereinafter referred to as a sync block), and preamble and postamble data are added as a whole to the data DATA. Record. As a result, during playback, the magnetic recording device uses the track sync data included in the preamble as a reference to generate the sync signal SYNC, sync block data ID, and data DATA.
can be reproduced and deinterleaved based on the synchronization signal SYNC and the sync block data ID.

Furthermore, by deinterleaving, even if dropout occurs, C1 and C
This effectively prevents errors exceeding the error correction capability of the two codes from concentrating in one place.

[0011]

[Problems to be Solved by the Invention] However, in the ID-1 format data recorder that records and reproduces desired data in this manner, the recording speed is about 10-10, which is sufficient for practical use mainly as a data recording and reproducing device for measurement. It is designed to guarantee a bit error rate of . If this bit error rate can be improved to about 10-15, it is thought that it can be applied to magnetic tape devices of computer systems such as those used in banks, etc., to store extremely important data. Therefore, the usability of this type of data recorder can be improved accordingly, and the field of application can be expanded. The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a magnetic recording device that can significantly improve the bit error rate compared to the conventional method.

0012

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a magnetic recording device 12 which sequentially forms recording tracks TR obliquely on a magnetic tape 1 and records desired input data WR on the recording tracks TR. , 13,
Input data D0 input sequentially is converted into input data D4A, D4B, D4C, D4D of multiple channels having a predetermined bit length.
and a plurality of encoders 32A, 32B, 3 that add error detection and correction codes C3 to input data D4A, D4B, D4C, and D4D for each of the plurality of channels.
2C, 32D, and input data D4 for each multiple channel.
A, D4B, D4C, D4D and error detection and correction code C
A plurality of interleaving processing means 33AA, 33AB, 33AC, 33AD interleaving processing of 3 and a plurality of interleaving processing means 33AA, 33AB, 33A.
C, 33AD output data D6A, D6B, D6C, D
By sequentially outputting 6D in a predetermined order, a plurality of interleave processing means 33AA, 33AB, 33AC, 3
a data converting means 33C that converts input data D4A, D4B, D4C, D4D of multiple channels interleaved by 3AD and error detection and correction code C3 into one channel of recorded data D6; and records the recorded data D6 on the magnetic tape 1. A magnetic recording means 13 is provided.

[0013]

[Operation] Input data D0 input sequentially is converted into input data D4A, D4B, D4C of multiple channels having a predetermined bit length.
, converting to D4D, adding error detection and correction code C3 to each of multiple channels, interleaving processing, and then converting to one channel of recording data D6, the bit error rate can be reduced with a correspondingly simpler configuration. Can be done.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) Overall configuration (1-1) Computer system configuration In Figure 1, 1
0 generally shows the schematic configuration of a computer system to which the present invention is applied, in which write data WR sent from the host computer 11 together with a write request is transmitted through the data recorder control device 12 as record data REC,
The data is supplied to the data recorder 13 in ID-1 format, thereby writing the write data WR onto the recording track on the magnetic tape.

Furthermore, in response to a read request input from the host computer 11, the magnetic tape of the data recorder 13 is played back, and the resulting playback data PB is transmitted through the data recorder control device 12 to the read data R.
D is input to the host computer 11.

The data recorder control device 12 is composed of a host interface control section 14 and a format control section 15.
controls the channel interface with the host computer 11, and the format control unit 15 controls the memory 1.
6 is used to format the data to be sent to and received from the data recorder 13. Also, the host interface control unit 14
Control information is exchanged between the format controller 15 and the format controller 15 with reference to the control table 17.

As a result, in the computer system 10, since the data recorder control device 12 is provided, the data recorder 13 can be connected to the external storage device of the host computer 11 using an interface similar to a conventional magnetic tape device on the host computer 11 side. It is designed so that it can be used as a

(1-2) Recording area on magnetic tape In this computer system 10, as shown in FIG. The center portion of the tape, where the degree of damage is relatively small, is used as the recording area AREC, thereby improving the bit error rate.

That is, as shown in FIG. 2(A), the position 10 [m] behind the physical end PBOT of the magnetic tape 1 is set as the logical end LBOT, and the physical end PBOT of the magnetic tape 1 is set as the logical end LBOT. For example, 15 m from the terminal PEOT.
] is the logical end LEOT, and the area from the logical end LBOT to the logical end LEOT is the recording area A.
Used as REC.

In this recording area AREC, as shown in FIG.
As shown in B), for example, 1 from the logical tip LBOT.
The area up to the position 0 [m] behind is used as the directory information track area DITA.

[0022] Also, this directory information track area D
Following the ITA, with a non-recording area NRA of a predetermined length in between,
The area between the logical end LEOT and the near end NEOT, which is a position 15 [m] before, for example, is used as the user recording track area UDA, and
The area beyond T to the logical end LEOT is used as the volume end information area VEOVA.

(1-3) Recording track format In this computer system 10, the ID-
The user data area of 36,108 [BYTE] for one recording track specified in one format is
As shown in FIG. 3, the data is formatted and the formatted data is interleaved in units of four tracks, thereby improving the bit error rate.

That is, in the computer system 10,
As shown in FIG. 3(A), the write data WR from the host computer 11 is divided into 32,76 blocks, for example, 1 block per recording track TR, with 4 tracks as one set.
The data is recorded as recording data DATA of 8 [BYTE].

At this time, for one recording track TR, 3
Recorded data DATA less than 2,768 [BYTE]
By adding the first supplementary data PD1, the total number becomes 32,768 [BYTE]. Also, in order to store the attached information of this one recording track TR,
320 [BYTE] worth of subcode data SCD is prepared.

In addition to this, the data recorder control device 12
3 for every 94 [BYTE] of subcode data SCD, recording data DATA, or first supplementary data PD1.
As shown in (A), 8[B
Reed-Solom (YTE)
On) error detection and correction code (hereinafter referred to as C3 code C3 according to the C1 and C2 codes in the ID-1 format) is added, which enables more powerful error correction and reduces the bit error rate. This is done so that it can be further improved.

Furthermore, as shown in FIG.
Regarding subcode data SCD, recording data DATA, first supplementary data PD1 and C3 code C3, which are formatted in units of recording tracks, data for four recording tracks TR1, TR2, TR3, and TR4 are tracked using a predetermined method. interleave processing over a period of time,
This makes it possible to further improve the bit error rate.

[0028] In this way, the four recording tracks TR1, T
204 at the beginning of one recording track worth of interleaved data for R2, TR3, and TR4 minutes.
The second supplementary data PD2 of [BYTE] is added, and as a result, the total amount of data for one recording track TR is 36,108[
BYTE].

Furthermore, by formatting the second supplementary data PD2 at the beginning, the supplementary data PD2 is placed in the part of the recording track where the magnetic head enters, where the degree of damage to the magnetic tape 1 itself is high and the tracking is unstable. This allows recording data DATA
It is possible to further improve the bit error rate.

(1-4) Recording Track Layout In the case of this computer system 10, the attached information of the recording track 1 stored in the subcode data SCD is track type information indicating the type of the corresponding recording track TR. TRID, block number BLNO to which recording track TR belongs, file number FL to which recording track TR belongs
NO, write retry count R for recording track TR
Number of bytes of data included in TCT and recording track B
Consists of YCT, etc.

This track type information TRID includes a volume information table VIT and a file information table FI.
Type information of the update information table UIT, dummy data track information DMY, user data track information UDT, tape mark track information TM, or recording end information EOR is recorded.

Here, as actually shown in FIG. 5, first, the track type information TRID of the recording track TR formed in the directory information track area DITA of the magnetic tape 1 is
As such, the volume information table VIT, file information table FIT, update information table UIT, or dummy data track information DMY is used.

[0033] This directory information track area DIT
A directory information table DIT that manages the files on the magnetic tape 1 as a whole is recorded, and first 1.5 [m] from the logical end LBOT of the magnetic tape 1.
Following the rising area RUA, a recording track consisting of the volume information table VIT is recorded with four tracks consisting of a track set.

The recorded data DATA of the volume information table VIT includes the beginning and end position information of the data block recorded in the user recording track area UDA with the entire magnetic tape 1 as one volume, and the length information and recording of the file information table FIT. The block number of the data block for which the write retry was executed is recorded.

A file information table FIT is also recorded on the 256 recording track following the volume information table VIT. The recording data DATA of this file information table FIT records the head position information and block length of each file recorded in the user recording track area UDA.

Further, following the file information table FIT, dummy data track information DMY is created for a predetermined number of tracks.
is recorded, and the update information table U is updated for the following 4 recording tracks.
Record IT. In the record data DATA of this update information table UIT, information indicating whether or not there is an update is recorded.

[0037]Following this update information table UIT, from the beginning of the directory information track area DITA
Dummy data track information DMY is recorded on the recording track TR up to 2.5 [m], and the remaining 2.5 [m] of directory information track area DITA is used as a spare area M.
Secured as GA.

Next, as the track type information TRID of the recording track TR formed in the user recording track area UDA next to the directory information track area DITA of the magnetic tape 1 and sandwiching the non-recording area NRA, user data track information UDT, tape Mark track information TM
Or use the recording end information EOR.

As the recording track TR of this user recording track area UDA, the user data track information of plural blocks constituting one file is sandwiched between the recording track TR of the tape mark track information TM whose unit is four tracks. Record the UDT recording track TR,
Following the end of the user data track information UDT, a recording track TR of recording end information EOR is recorded.

Note that the recording data DATA of the tape mark track information TM and recording end information EOR includes 32, 7
The first supplementary data PD1 for 68 [BYTE] is recorded, and data corresponding to the write data WA input from the host computer 11 is recorded in the recording data DATA of the recording track TR of the user recording track area UDA.

In this way, this computer system 10
, a directory information track area DITA is provided at the beginning of the magnetic tape 1, and a user recording track area U is provided.
By managing the contents of the DA on a file-by-file basis, data recorded on the data recorder 13 can be accessed from the host computer 11 in the same way as an external recording device.

(1-5) Configuration of the recording format section of the format control section Here, the format control section 15 of the data recorder control device 12 in this computer system 10 has a recording format as shown in FIGS. 6 and 7 together with the memory 16. 20 and a playback format section 40.

That is, in the recording format control section 20, the host interface control section 14, 32
The data for each bit is stored in the memory (i.e., first in first out) as 4-channel 8-bit parallel write data D0.
The write data D0 is synchronized with the internal clock CK by inputting it to the (FIFO) circuit 21 consisting of
2 and sends it to the CRC error detection circuit 23.

Note that the write data D0 is processed for every four channels inside the recording format control section 20, but in the description of the recording format control section 20, data for one channel will be explained.

The CRC error detection circuit 23 receives input data D.
CRC (cyclic redundancy)
y code) and inputs the detection result CRCK to the system control circuit 24, which has a computer configuration including a CPU.

Note that when the system control circuit 24 detects an error in the input data D1 based on the detection result CRCK of the CRC error detection circuit 23, it returns this to the host interface control section 14 as an error detection signal ER. As a result, for example, the host interface control unit 14 executes retransmission processing for the write data D0 in which the error exists.

The buffer memory 22 buffers the input data D1 by one recording track TR as described above with reference to FIG. 3, and stores the resulting recording data DATA.
The first buffer data D2 corresponding to the first buffer data D2 is sent to the first multiplexer 25.

In addition to the first buffer data D2, the first multiplexer 25 receives first supplementary data PD1 for tape mark track information TM sent from the tape mark generation circuit 26 and dummy data generation circuit 27, respectively. Dummy data track information DMY sent from
Dummy data for the first supplementary data PD for the recording data DATA sent from the supplementary data generation circuit 28
1 is input.

As a result, the first multiplexer 25 selects the recording data DATA of the first buffer data D2 according to the control signal CNT inputted from the system control circuit 24.
The second buffer data D3 is generated by adding the first supplementary data PD1 to the second buffer data D3, and is sent to the second multiplexer 29.

In addition to the second buffer data D3, the second multiplexer 29 receives the directory information table DIT sent from the directory information table memory 30, and the subcode generated by the subcode generation circuit 31 based on the contents of the directory information table 30. The subcode data SDC is input.

Practical directory information table memory 3
0 stores the directory information table DIT described above with reference to FIG.
IT length information and the block number of the data block for which write retry was performed during recording are generated.

As a result, the second multiplexer 25 assigns the subcode data S to the second buffer data D3 in accordance with the control signal CNT inputted from the system control circuit 24.
By adding DC, the format described above with reference to FIG. 3 is formed, and this is sent to the C3 code generation circuit 32 as third buffer data D4.

The C3 code generation circuit 32 generates the C3 code C3 of 8 [BYTE] as described above with reference to FIG. Send.

The interleaving circuit 33 executes the interleaving process for the four tracks shown in FIG. 4 by sequentially loading four tracks of recorded track data D5 into the interleaving memory and outputting them in a predetermined order. The second recording track data D6 is sent to the third multiplexer 34.

The third multiplexer 34 receives, in addition to the second recording track data D6, the second supplementary data PD1 sent from the second supplementary data generating circuit 35 and the synchronization code generating circuit 36. Synchronization code data is input.

As a result, the third multiplexer 34 adds the second supplementary data PD2 and the synchronization code data to the second recording track data D6 in accordance with the control signal CNT inputted from the system control circuit 24. The obtained third recording track data D7 is sent to the parallel-to-serial conversion circuit 37.

The parallel-to-serial conversion circuit 37 converts the third recording track data D7 consisting of four channels of 8-bit parallel into 32-bit serial recording data S0, which is sent to the data recorder 13 as recording data REC through the output circuit 38. is input.

In this manner, the recording format control unit 20 of the format control unit 15 processes the write data D0 input from the host interface control unit 14.
The format processing described above in FIGS. 3 to 5 is executed to generate recording data REC, and the data is recorded on the magnetic tape 1 based on the ID-1 format as shown in FIGS.

(1-6) Configuration of the playback format section of the format control section In the playback format section 40 shown in FIG.
Serial playback data P played back by data recorder 13
B is input to the serial-parallel conversion circuit 41, and 32
The first bit consists of 4 channels of 8-bit parallel bits.
is converted into reproduced data D10, which is input to the deinterleaving circuit 42.

Similar to the interleave circuit 33 of the recording format unit 20, the deinterleave circuit 42 performs deinterleaving corresponding to the interleaving process of the interleave circuit 33 by sequentially taking in the first reproduced data D10 and outputting it in a predetermined order. The processing is executed, and the resulting second reproduced data D11 is input to the C3 error correction circuit 43.

The C3 error correction circuit 43 converts the C3 code C added by the C3 code generation circuit 32 of the recording format section 20.
3 is used to perform error correction processing on the second reproduced data D11, and the third reproduced data D1 obtained as a result
Send 2.

In fact, among this third reproduction data D12, as shown in FIG. 5, the data corresponding to the user recorded data track UDT is input to the buffer memory 44, and the data corresponding to the directory information table DIT is input to the subcode memory 45. and input into the directory information table memory 46.

The buffer memory 44 deletes the first supplementary data PD1 included in the third reproduced data D12,
This is input to the memory circuit 47 as fourth reproduction data D13 and synchronized with an external clock, and is sent to the host interface control section 14 as read data D14 outputted from the reproduction format control section 40.

Note that when the directory information table DIT input to the directory information table memory 46 is updated, the system control circuit 24 updates the directory information table DI with the data recorder control signal CDIR.
The update information UDD of T is sent to the data recorder 13, and the contents of the directory information table DIT on the magnetic tape 1 are updated.

The system control circuit 24 also outputs the output data D.
14, a control signal CHI is used to send a response to a data reproduction request inputted from the host interface control section 14.
It is sent to the host interface control unit 14 as C.

In this way, the playback format control section 20 of the format control section 15 performs the inverse formatting process of the formatting process described above in FIGS. 3 to 5 on the playback data PB played back by the data recorder 13. , generates read data D14 and sends it to the host interface control section 14.

(2) Interleave processing As shown in FIG. 8, in the data recorder control device 12, the buffer memory 22 has a recording capacity of 9 [MBITE].
Write data D0 that is input sequentially is buffered via a memory circuit 21 (not shown). Further, the buffer memory 22 stores the buffered write data D0 in units of 32,768 [BITE] (that is, the amount of data for one recording track).
After adding [BYTE] subcode data SCD,
It is output as first buffer data D2.

When the first buffer data D2 is less than the amount of data for one recording track, the multiplexer 25 having an adder circuit adds the first supplementary data PD1 to the third data of 33,088 [BITE] as a whole. Buffer data D4 is generated. As shown in FIG. 9, the C3 code generation circuit 32 divides the third buffer data D4 into 352 data blocks TF0 to TF351, generates a C3 code C3 for each data block TF0 to TF351, and
It is added to each data block TF0 to TF351.

As a result, the C3 code generation circuit 32 has a code length N (N=102 [BITE]) and a parity number P (
After generating a Reed-Solomon code of P=8 [BITE], it is output as recording track data D5.

The interleave circuit 33 is composed of an interleave memory circuit 33A and an address generation circuit 33B that generates write and read addresses for the interleave memory circuit 33A. As shown in FIG. 10, the interleave memory circuit 33A is provided with storage areas T1 to T4 so as to be able to store recording track data D5 for four recording tracks, and the recording track data D5 is transferred to each storage area T1 to T4 by arrows. W(0), W(1),...
, W(M), W(M+1), ..., W(2M), W(2
M+1), ..., W (3M), W (3M+1) ..., W
(4M-1), data blocks TF0 to TF35
Store in 1 unit.

Furthermore, the interleave memory circuit 33A stores the recorded track data D5 in a different order from that at the time of writing, as shown by arrows R(0), R(1), . . . , R(N-1). As a result, the recording track data D5 for four recording tracks are interleaved.

The multiplexer 34 outputs the second recording track data D6 (interleaved recording track data D) output from the interleave memory circuit 33A.
5), the second
Supplementary data PD2 and synchronization code data are added. As a result, the multiplexer 34 converts the second recording track data D6 into recording data REC in units of 36,108 [BITE] corresponding to the user data amount of one recording track in the D-1 format, and then sequentially transmits the data to the data recorder 13. Output to.

As a result, in the data recorder 13, the write data D0 with the C3 code can be interleaved and recorded using four recording tracks as one unit, and at this time, the data recorder 13 performs interleaving processing within the recording track. At the same time, by recording with C1 and C2 codes, the bit error rate can be significantly improved.

Furthermore, in this embodiment, the system control circuit 24 controls the operation of the data recorder 13 and records data in units of four recording tracks. That is, even if a write request is sent from the host computer 11 and the write data WR sent at the same time is less than the data amount of one recording track unit, the first supplementary data PD
By adding 1, recording data REC for four recording tracks is generated, and the data recorder 13 is driven for four recording tracks.

Furthermore, if the write data WR has an amount of data equal to or more than 4 recording tracks, by adding the first supplementary data PD1, the recorded data REC is generated to be an integral multiple of the data amount for 4 recording tracks. Then, the data recorder 13 is driven accordingly. In other words, the system control circuit 24 handles one write request (hereinafter referred to as a control unit) no matter how small the amount of write data WR is.
In response to this, the data recorder 13 is driven for four recording tracks, and the write data WR is interleaved with four recording tracks as one unit corresponding to the control unit.

As a result, in this embodiment, waste of the magnetic tape 1 can be prevented, and the write data WR can be
It is designed to enable high-density recording. In other words, if you increase the number of units of recording tracks to be interleaved,
Even if a dropout or the like occurs, it is possible to effectively prevent errors from being concentrated in one place, and the bit error rate can be improved.

Therefore, as shown in FIG. 11, even if the data recorder is driven by four recording tracks in response to one control unit, for example, if interleaving is performed in units of eight recording tracks, the bit error rate can be reduced accordingly. can be improved. However, in this case, if an error is detected in the first recording track of the Nth group due to read-after-write, it is necessary to re-record the data for the eight recording tracks of the Nth group.

However, as shown in FIG. 12, when driving the data recorder for four recording tracks in response to one control unit as in this embodiment, if interleaving is performed in units of four recording tracks, for example, Nth group 1
Even if an error is detected on a recording track, it can be rewritten by simply rerecording data for four recording tracks, thereby effectively avoiding wasteful consumption of the magnetic tape 1 and recording data efficiently. can.

Furthermore, in practice, by assigning C1 to C3 codes and performing interleave processing within a recording track and in units of four recording tracks, a practically sufficient bit error rate of 10-15 can be guaranteed; It was confirmed that the desired data could be reliably recorded at high density.

(3) Parallel Processing As shown in FIG. 13, in this embodiment, the C3 code generation circuit 32 and interleave memory circuit 33A are different from the C3 code generation circuits 32A to 32D and interleave memory circuits 33AA to 33AD, which have the same configuration. Four channels are prepared, so that data of every 32 bits can be processed as four channels of 8-bit parallel data.

That is, as shown in FIG. 14, the recording format control section 20 converts the 32-bit continuous write data WR (FIG. 14(A)) into 8-bit units 00, 01,
02, . . . , thereby generating 4-channel 8-bit parallel buffer data D4 (D4A to D4D) (FIG. 14 (B1) to (B4)).

As shown in FIG. 15, the C3 code generation circuit 3
2A to 32D are 102 [BITE] ((
00-372, 376-748, 752-11
22,...), (01-373, 377-749
,...), (02-374, 378-750,...
), (03-375, 379-751,...)
8 [BITE] C3 code ((P0~P28,
P32 ~ P60 , ...), (P1 ~ P29 , P3
3 ~ P61 , ...), (P2 ~ P30 , P34
~P62,...), (P3, ~P31, P35 ~
P63 ,...)) (Fig. 15 (C1) to (C
4)).

[0083] As a result, the C3 code generation circuits 32A to 32
D is the buffer data of each channel D4A~
For D4D, a Reed-Solomon code with a code length of 102 [BITE] and a parity number of 8 [BITE] is generated, and then outputted to interleave memory circuits 33AA to 33AD as recording track data D5 (D5A to D5D). The interleave memory circuits 33AA to 33AD store each recording track data D as described above with reference to FIG.
5A to D5D are sequentially accumulated for each data block TF0 to TF351, and when recording track data D5A to D5D for four recording tracks are accumulated, the order is changed from that at the time of writing and output.

At this time, interleaved memory circuit 33A
In A, 00, 04, 08, ..., 372, P
0, 04,..., P28, 376, 380,...
, 748 , P32 , P36 , ..., P60, 75
2, . . . , 1122, P64, . . . in the order of data blocks TF0 to TF351.
0, 376, 752, ... NN, 04, 380,
756,..., NN+4, 08,..., NN+8,...
..., and thereby the recording track data D5A for one recording track is interleaved and output (FIG. 15(A), FIG. 16(A)).

Similarly, interleaved memory circuit 33AB
In, 01, 05, 09, ..., 373, P1
,05,...,P29,377,381,...,
749, P33, P37,..., P61, 75
Recording track data D5B input in units of data blocks TF0 to TF351 are accumulated in the order of 3,..., 1123, P65, .
5, 381, 757,..., NN+5,09,...
, NN+9, .

Interleaved memory circuit 33AC and 3
Similarly, in 3AD, data blocks TF0 to TF
The recording track data D5C and D5D input in units of 351 are accumulated and output in an order orthogonal to the writing, thereby interleaving the recording track data D5C and D5D for one recording track and outputting them (see FIG. 15). C) and (D), Figure 16 (C) and (D))
. As a result, in the interleave memory circuit 33A, recording track data D5 (D5A
~D5D) are interleaved.

The data conversion circuit 33C is composed of a selection circuit that sequentially switches contacts, and thereby converts the four channels of recording track data D6A to D6D output from the interleave memory circuits 33AA to 33AD into one continuous channel of 8 bits. It is converted into recording track data D6 (FIG. 16(E)). As a result, the interleave memory circuit 33 is configured to sequentially convert write data WR subjected to four-channel parallel processing into recording data REC and record the data.

[0088] Therefore, for the 4-channel parallel processing,
In the interleaved memory circuit 33, the operating speed can be reduced, data can be processed reliably, and power consumption can be reduced accordingly. Furthermore, by performing four-channel parallel processing, the overall configuration can be simplified accordingly.

That is, when directly interleaving 32-bit data in units of four recording tracks, a memory circuit for storing data for four recording tracks is required on the input side of the C3 code generation circuit 32. However, if 4-channel parallel processing is performed as in this embodiment, the sequentially input data can be processed by simply dividing it into 4 channels, which simplifies the configuration of the input side of the C3 code generation circuit 32 and reduces the overall configuration. can be simplified.

(4) Processing for starting reproduction The system control circuit 24 outputs predetermined identification data DFT to the multiplexer 34, thereby recording the identification data DFT on the magnetic tape 1 together with the second supplementary data PD2. As a result, the data recorder control device 12
At the time of playback, the deinterleaving process and error correction process are switched based on the identification data DFT, and if the magnetic tape is recorded in the D-1 format, the interleaving process and error correction process are performed in a format different from that of the data recorder control device 12. Even if a C3 code is generated, it can be reproduced.

That is, in the D-1 format,
Since it is a standardized format, compatibility can be guaranteed even when recording with different data recorders 13. However, when preprocessed data is recorded by the data recorder 13 as in this embodiment, compatibility cannot be guaranteed. Therefore, in the system control circuit 24, interleave information and error correction information are recorded as identification data DFT.

Here, the interleaving information includes the recording track unit of interleaving processing (in this case, it consists of 4 recording tracks), the processing data length (data length in the vertical and horizontal directions in FIG. 10), and other information in the interleaving memory circuit 33.
Information regarding write and read processing of A is assigned. Further, the error correction information is assigned the code length, parity number, etc. (FIG. 9) of the Reed-Solomon code. This allows the data recorder control device 12 to reproduce magnetic tapes recorded in different formats by switching between deinterleave processing and error correction processing based on the identification data DFT.

Furthermore, at this time, in this embodiment, C
By recording the identification data DFT in the recording area of the second supplementary data PD2 that is not subjected to the 3 code and interleaving processing, the identification data DFT can be detected simply by taking in the reproduction data PB at a predetermined timing, and the detection can be performed more quickly. By switching the processing format, the subsequently inputted reproduction data PB is reliably processed. That is, the interleave control circuit 42C detects the identification data DFT by capturing the reproduced data PB output from the data recorder 13 at a predetermined timing, and the address generation circuit 42C detects the identification data DFT based on the detection result.
Control data is output to the B and C3 error correction circuits 43.

The deinterleave memory circuit 42A has the same configuration as the interleave memory circuit 33A, and sequentially processes the reproduced data PB based on the write and read addresses generated by the address generation circuit 42B. At this time, the deinterleave memory circuit 42A selects the selection circuit 5.
When inputting the reproduced data PB via 0, the continuous 8-bit reproduced data PB is converted into 4 channels of 8-bit parallel data and taken in as in the case of recording.

Accordingly, in this embodiment, by processing the reproduced data PB in parallel with the C3 error correction circuit 43, the operating speeds of the deinterleave circuit 42 and the C3 error correction circuit 43 are reduced, and the data This allows the configuration of the recorder control device 12 to be simplified. When generating write and read addresses, the address generation circuit 42B switches its operation based on the control data output from the interleave control circuit 42C, thereby deinterleaving the deinterleaving memory circuit 42A in accordance with the format determined by the identification data DFT. Switch interleave processing.

As a result, the data recorder control device 12 is configured to deinterleave the reproduced data PB even for magnetic tapes recorded in different interleave processing formats. The C3 code correction circuit 43 is composed of a 4-channel code correction circuit,
The operation is switched based on the control data output from the interleave control circuit 42C, and error-corrected reproduced data D12 is output to the buffer memory circuit 22.

[0097] As a result, the data recorder control device 1
In 2, even if preprocessed in a different format, the reproduced data P output from the data recorder 13
B can be reliably reproduced, and the field of application of the data recorder control device 12 can be expanded accordingly, and the usability can be improved.

(5) Configuration of Buffer Memory Here, the buffer memory 22 has a recording capacity of 9 [MBITE], which is much larger than the data amount of each recording track, so that it can sequentially capture the playback data D12. It is possible to selectively output only desired data. At this time, the buffer memory 22 is configured to selectively store only desired data based on the subcode SCD, so that the buffer memory 22 can be used efficiently.

Therefore, in this embodiment, when recording,
The amount of data corresponding to each recording track is recorded as one unit, with each subcode SCD attached. That is, during recording, the system control circuit 24 detects the attributes of the sequentially input write data WR based on the output data of the host computer 11, and generates subcode data SCD for each attribute.

Furthermore, the system control circuit 24 outputs the generated subcode data SCD to the buffer memory 22, so that as described above with reference to FIG. 3, every 36,108 [BITE] corresponding to the data amount of one recording track 320 [BITE] subcode data SCD is added. Therefore, in the subcode data SCD, a C3 code is generated together with the input data D0, and then interleaved with four recording tracks as one unit, and then recorded on the magnetic tape 1.

On the other hand, during playback, the buffer memory 22
is the reproduced data D output from the C3 error correction circuit 43
12 are taken in sequentially. At this time, as shown in FIG. 17, the buffer memory 22 takes in the reproduced data D12 for each subcode data SCD, and then outputs the taken in subcode data SCD to the system control circuit 24.

The system control circuit 24 uses the subcode data SCD as a reference to determine whether or not it is the data requested to be read from the host computer 11. As a result, the system control circuit 24 once takes in the reproduced data D12 together with the subcode data SCD into the buffer memory 22, and then determines whether or not the data is necessary.

[0103] If necessary data and unnecessary data are to be reproduced in a mixed manner, there is also a method of selectively capturing only the necessary data in advance. However, if only the necessary data is selectively captured in advance, it is necessary to judge whether the data is necessary or not in an extremely short period of time until the playback data is output, which complicates the configuration of the control circuit. It is inevitable that it will become

However, as in this embodiment, if it is determined whether or not the data is necessary after it has been imported into the buffer memory 22, the determination can be made over time during the period in which the subsequent reproduction data D12 is being input. , the configuration of the system control circuit 24 can be simplified accordingly.

[0105] Here, for reproduction data that does not need to be output to the host computer 11 (in this case, subcodes B and X are subcodes of unnecessary data), the system control circuit 24 outputs the corresponding subcode data SCD.
The recording area is output to the buffer memory 22. In response to this, the buffer memory 22 overwrites and records the subsequently input reproduction data D12 in this area, thereby effectively utilizing the capacity of the buffer memory 22 and selectively storing only necessary data.

Furthermore, when the reproduction data D12 has been reproduced by a predetermined amount, for example, the buffer memory 22 transmits the stored reproduction data in response to a transmission request from the host computer 11. In this way, only desired reproduction data can be reliably output with a simple configuration.

(6) Test mode When a self-diagnosis command is input from the host computer 11, the system control circuit 24 switches to a self-diagnosis mode and self-diagnoses the operation of the data recorder control device 12. That is, the system control circuit 24 outputs a control signal to the multiplexer 25, and replaces the second buffer data D2 with the predetermined test data TEST.
It is output to the code generation circuit 32.

Here, the test data TEST is generated by a data generation circuit having a read-only memory circuit configuration, and is shown in FIG.
As shown in 8, each data block TF0 to TF351
The value increases sequentially within each data block TF0~
The TF 351 generates numerical data in such a way that the leading numerical data increases sequentially. As a result, a C3 code is added to the test data TEST via the C3 code generation circuit 32, and recording track data D5 is generated.

Here, the system control circuit 24 first outputs a control signal to the selection circuit 52, and selects the recording track data D.
5 is directly input to the C3 error correction circuit 43. As a result, the C3 error correction circuit 43 corrects errors in the recording track data D5 based on the C3 code, and outputs a detection signal OK to the system control circuit 24 when an error is detected. Here, in the data recorder control device 12, by directly inputting the recording track data D5 output from the C3 code generation circuit 32 to the C3 error correction circuit 43, the C3 code generation circuit 32 or the C3 error correction circuit 4
If C3 code generation circuit 32 or C3 error correction circuit 43 is operating normally, no bit error can occur, but if there is a failure in either C3 code generation circuit 32 or C3 error correction circuit 43, detection signal OK rises.

[0110] Thereby, the data recorder control device 12 can easily perform self-diagnosis based on the error detection result of the C3 error correction circuit 43. In fact, in conventional data recorders, etc., as shown in FIG.
A dedicated self-diagnosis circuit 56 is used for self-diagnosis, and a data generation circuit 58 of the self-diagnosis circuit 56 generates test data. Furthermore, in the self-diagnosis circuit 56, the C3 code generation circuit 32 and the C3 error correction circuit 43
The test data is input to the data comparator 59 via the delay circuit 60, and a comparison result is obtained with the test data input via the delay circuit 60, so that the self-diagnosis result SOK is obtained based on the comparison result. being done.

Therefore, according to this embodiment, a self-diagnosis result can be obtained without providing a dedicated self-diagnosis circuit 56, and the overall configuration can be simplified as compared to the conventional one. When the self-diagnosis results of the C3 code generation circuit 32 and the C3 error correction circuit 43 are thus obtained, the system control circuit 24 switches the contacts of the selection circuits 50 and 52,
Interleaving circuit 33 and deinterleaving circuit 42
Let's move on to self-diagnosis.

Here, the system control circuit 24 converts the recording track data D5 into recording track data D6 via the interleave memory circuit 33A, and then directly converts the recording track data D6 into the deinterleave memory circuit 4.
Input 2A. Thereby, the system control circuit 24 can confirm the operation of the interleaving circuit 33 and the deinterleaving circuit 42 based on the detection signal OK, and thus can obtain a self-diagnosis function with a simple configuration.

(7) Unloading process When all recording and playback processes are completed and a tape cassette ejection command is input from the host computer 11, the system control circuit 24 executes the processing procedure shown in FIG. and eject the tape cassette. That is, the system control circuit 24 operates from step SP1 to step SP2.
When the tape cassette ejection command COM1 is input from the host computer 11, the process moves to step SP3.

After sending the rewind command COM2 to the data recorder 13, the system control circuit 24 moves to step SP4, and based on the response data DOU sent back from the data recorder 13, the system control circuit 24 sends the rewind command COM2 to the data recorder 13, and based on the response data DOU sent back from the data recorder 13, the system control circuit 24 moves to step SP4.
It is determined whether the magnetic tape 1 has been rewound within the range from OT to the logical end LBOT (FIG. 2). If a negative result is obtained here, the system control circuit 24 moves to step SP5 and waits for a predetermined period of time.
The rewinding operation of the data recorder 13 is awaited, and when a predetermined period of time has elapsed, the process moves to step SP4.

[0115] As a result, the system control circuit 24 rewinds the magnetic tape 1, and when the magnetic tape 1 is rewound within the range from the physical end PBOT to the logical end LBOT, a negative result is obtained in step SP4. As a result, the process moves to step SP6. Here, the system control circuit 24 outputs the unloading control data COM2 to the data recorder 13, and when the unloading completion response data DOU is input from the data recorder 13, the system control circuit 24 goes to step S.
Move to P8.

Here, the system control circuit 24 outputs a tape cassette ejection command COM2 to the data recorder 13, and then proceeds to step SP8 to end the processing procedure. As a result, in the data recorder control device 12, loading and unloading of the magnetic tape 1 is performed in the leading area of the magnetic tape 1 that is not used for recording data.

That is, in this type of magnetic recording/reproducing apparatus, a large load is applied to the magnetic tape 1 when loading and unloading the magnetic tape 1, and the largest load is applied especially when the magnetic tape 1 is held down by a capstan. . While such a load does not cause any serious problems in a video tape recorder or the like, in this type of data recorder 13, the bit error rate decreases.

Therefore, in this embodiment, by rewinding the magnetic tape 1 to the leading end and ejecting the tape cassette, loading and unloading of the magnetic tape 1 is always carried out at the leading end, thereby reducing bit errors. This makes it possible to effectively avoid a drop in rate.

(8) Effects of the Embodiment According to the above configuration, input data that is input sequentially is converted into input data of 4 channels, and C3 is converted for each channel.
After adding the code, the data is interleaved and converted into one channel of recording data, thereby simplifying the overall configuration and improving the bit error rate.

(9) Other Embodiments In the above-described embodiments, a case has been described in which recording is performed by interleaving between four recording tracks TR formed corresponding to one control unit, but the present invention The present invention is not limited to this, but can be widely applied to cases where a plurality of recording tracks are formed corresponding to one control unit.

Furthermore, in the above embodiment, the case where input data is converted into input data of four channels and processed is described, but the present invention is not limited to this, but can be broadly applied to cases where input data is divided into multiple channels and processed. Can be applied.

Furthermore, in the above embodiment, the case where the present invention was applied to a D-1 format data recorder was described, but the present invention is not limited to this, but can be widely applied to magnetic recording devices that record various data. can do.

[0123]

As described above, according to the present invention, input data that is input sequentially is converted into input data of a plurality of channels having a predetermined bit length, and an error detection and correction code is added to each channel to perform interleaving processing. After that, by converting the data into one channel of recording data, it is possible to obtain a magnetic recording device that can simplify the overall configuration and improve the bit error rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a computer system according to one embodiment of the present invention.

FIG. 2 is a schematic diagram showing recording areas on the magnetic tape.

FIG. 3 is a schematic diagram showing the recording format on the magnetic tape.

FIG. 4 is a schematic diagram for explaining interleave processing between recording tracks.

FIG. 5 is a schematic diagram showing a track format on a magnetic tape.

FIG. 6 is a block diagram showing a recording format control section.

FIG. 7 is a block diagram showing a reproduction format control section.

FIG. 8 is a block diagram showing a data recorder control device.

FIG. 9 is a schematic diagram illustrating a C3 code generation process.

FIG. 10 is a schematic diagram for explaining interleaving processing.

FIG. 11 is a schematic diagram illustrating a case where interleaving processing is performed in units of 8 tracks.

FIG. 12 is a schematic diagram illustrating a case where interleaving processing is performed in units of four tracks.

FIG. 13 is a block diagram showing an interleaved memory circuit.

FIG. 14 is a schematic diagram for explaining parallel processing of interleave processing.

FIG. 15 is a schematic diagram for explaining the operation of each interleave memory.

FIG. 16 is a schematic diagram for explaining interleaved data.

FIG. 17 is a schematic diagram for explaining the operation of a buffer memory.

FIG. 18 is a schematic diagram showing the configuration of test data.

FIG. 19 is a block diagram showing a self-diagnosis circuit.

FIG. 20 is a flowchart illustrating immediate processing.

FIG. 21 is a schematic diagram for explaining the D-1 format.

FIG. 22 is a schematic diagram for explaining the interleaving process.

[Explanation of symbols]

11...Host computer, 12...Data recorder control device, 13...Data recorder, 15...Format control unit, 22...Buffer memory, 32...C3 code generation circuit, 33A...Interleave memory, 42A
...Deinterleave memory, 43...C3 error correction circuit.

Claims (1)

[Claims] Claims: 1. A magnetic recording device that sequentially forms diagonal recording tracks on a magnetic tape and records desired input data on the recording tracks, wherein the sequentially inputted input data is converted into input data of a plurality of channels having a predetermined bit length. a converter for converting; a plurality of encoders for adding error detection and correction codes to the input data for each of the plurality of channels; and an interleaving process for the input data and the error detection and correction codes for each of the plurality of channels. By sequentially outputting the output data of the plurality of interleaving processing means and the plurality of interleaving processing means in a predetermined order, the input data of the plurality of channels interleaved by the plurality of interleaving processing means and the error detection and correction code are obtained. , a magnetic recording device comprising: data converting means for converting the recorded data into one channel of recorded data; and magnetic recording means for recording the recorded data on the magnetic tape.