JPH04286368A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a transistor which is lessened in ON-state current and excellent in characteristics by a method wherein one of two kinds of impurity ions is implanted into nearly all the surface of a substrate, and the other kind of impurity ions is implanted into a required region, and the fluorine content contained in an amorphous semiconductor is set to a prescribed value or below after the transistor is formed. CONSTITUTION:After a gate electrode 105 is formed, ions of P-type impurity such as boron are implanted into all the surface of a source/drain region 106 using the gate electrode 105 as mask. Then, a P-channel TFT part is covered with a resist 111, N-type impurities such as phosphorus are injected to form a source/drain region 107 of an N-channel TFT. In succession, an interlaminar insulating film 108 is formed, and an annealing process is carried out to enable source/drain regions to recover their crystallinity and to activate impurities contained in them. Moreover, activation annealing conditions are optimized corresponding to the quantity of fluorine mixed into a-Si. The quantity of fluorine is set to 1X10<18>/cm<3> or below.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor element on an insulating amorphous material.

0002

[Prior art] Insulating amorphous substrates such as glass and quartz,
Attempts are being made to form high-performance semiconductor elements on insulating amorphous layers such as SiO2.

In recent years, as the needs for large, high-resolution liquid crystal display panels, high-speed, high-resolution contact-type image sensors, and SRAMs using TFTs as load sections have increased, high-performance devices have been developed on insulating amorphous materials. There is an urgent need to establish technology for forming semiconductor devices. For example, when forming a thin film transistor (TFT) on an insulating amorphous material,
(1) TFT whose element material is amorphous silicon formed by plasma CVD method etc., (2) TFT whose element material is polycrystalline silicon formed by CVD method etc., (3) TFT which uses polycrystalline silicon formed by CVD method etc. TFTs and the like using formed single crystal silicon as an element material are being considered.

However, among these TFTs, TFTs using amorphous silicon as an element material have significantly lower field effect mobility (non-conducting TFTs) than those using polycrystalline silicon or single crystal silicon as an element material. Crystalline silicon TFT <
1cm2/V·sec), it is difficult to realize a high-performance TFT.

On the other hand, the melting and recrystallization method using a laser beam or the like is still not a fully developed technology, and it is difficult to use the technology when it is necessary to form elements over a large area, such as in liquid crystal display panels. The difficulty is especially great.

Therefore, as a high-performance semiconductor element formed on an insulating amorphous material, polycrystalline silicon formed by CVD method or the like, or solid phase growth method (Thin Solid Film) is used.
s 100 (1983) p. 227, JJAP
Vol. 25 No. 2 (1986) p. L12
Poly-Si TFTs using the large-grain polycrystalline silicon formed in step 1) as an element material are attracting attention, and research toward practical use is intensifying.

[0007]

[Problems to be Solved by the Invention] However, in the conventional technology, the poly-Si layer forming the channel region is formed by a CVD method or plasma CVD method. Impurities and the like are easily mixed in, which causes deterioration of characteristics such as increased off-state current of the TFT.

Therefore, the present invention aims to reduce the off-state current of an insulated gate field effect transistor in which at least a portion of the channel region is formed of a non-single-crystal semiconductor, and at the same time provide excellent characteristics such as high field effect mobility. The present invention provides a structure for realizing a transistor having the present invention and a method for manufacturing the same.

[0009]

[Means for Solving the Problems] A semiconductor device of the present invention includes:
1) In a semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is formed of a non-single crystal semiconductor, the amount of fluorine in the non-single crystal semiconductor is 1.
*1018/cm3 or less.

2) The non-single crystal semiconductor is polycrystalline silicon.

[0011] Furthermore, the method for manufacturing a semiconductor device of the present invention includes:
3) A method for manufacturing a CMOS type semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is formed of a non-single crystal semiconductor, in which (a) silicon is mainly formed on an insulating amorphous material; Step of forming a non-single crystal semiconductor layer, (b) Step of ion-implanting a first conductivity type impurity to form a source/drain region, (c)
(d) an annealing step for activating the ion-implanted dopants; One of the second impurity ion implantations is performed over almost the entire surface of the substrate, and the other is ion implanted only in a predetermined region, and the amount of fluorine in the non-single crystal semiconductor after the transistor is completed. is 1×10 18 /cm 3 or less.

4) The annealing for activation is 900
It is characterized by being made at a temperature below ℃.

5) The amount of fluorine in the non-single crystal semiconductor is 5×
It is characterized by being 1017/cm3 or less.

6) The annealing for activation is 100
It is characterized by being made at a temperature of 0°C or lower.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention. Note that FIG. 1 takes as an example a case where a thin film transistor (TFT) is formed as a semiconductor element.

In FIG. 1, (a) shows a silicon layer 1 on an insulating amorphous material 101 such as an insulating amorphous substrate such as glass or quartz, or an insulating amorphous material layer such as SiO2.
This is the process of forming 02. An example of film forming conditions is:
Using the plasma CVD method, the substrate temperature is maintained at room temperature to about 600°C, monosilane or a gas made by diluting monosilane with hydrogen, argon, helium, etc. is introduced into the reaction chamber, and high frequency energy etc. are applied to decompose the gas and form the desired substrate. There is a method of forming a silicon layer thereon with a thickness of about 100 Å to 2000 Å. Note that when a-Si is formed by plasma CVD, the F (fluorine) remaining in the chamber becomes a-Si.
It can be mixed into the Si film and increase defects in the poly-Si film after solid-phase growth and in the source/drain region after ion implantation/activation annealing, and have a large impact on TFT characteristics (especially increase in off-current). was clarified as a result of our investigation. The detailed results will be described later. In this embodiment, a case is exemplified in which a-Si formed by plasma CVD is grown in a solid phase, but the present invention is not limited to this. For example, a method of forming a poly-Si film using the LPCVD method, a method of forming a-Si film using a method other than the plasma CVD method and growing it in a solid phase, or a method of forming a-Si or poly-Si formed using a plasma CVD method etc. using a laser beam. The present invention is also effective for methods of crystal growth using an annealing method. In particular, in the method of forming a-Si by plasma CVD method and growing crystals by laser annealing method, the method for reducing impurities in the film described in the following embodiment can be applied as is.

In (b), a polycrystalline silicon layer 103 is formed by growing crystals of the silicon layer 102 by heat treatment or the like,
This is a step of patterning the polycrystalline silicon layer into a predetermined shape, if necessary. If necessary, such as when the heat treatment step of step (b) and the gate oxidation step of step (c) are performed consecutively, the silicon layer 102 is patterned into a predetermined shape before crystal growth. The heat treatment conditions are determined by the process (
The optimum conditions differ depending on the method of forming the silicon layer in a). For example, there are differences as described below depending on the substrate temperature during film formation.

(1) A film formed at a relatively low substrate temperature of about room temperature to 150°C becomes amorphous silicon containing a large amount of hydrogen, but a film formed at a substrate temperature of about 200 to 300°C becomes amorphous silicon. Hydrogen in the film can be removed by heat treatment at a lower temperature than with the film. An example of heat treatment conditions will be described below. Plasma C
First annealing is performed on the formed amorphous silicon film in a VD reaction chamber. Amorphous silicon films, which are formed at low deposition temperatures, are porous films, so if they are taken out into the atmosphere after being deposited, oxygen, etc. are likely to be incorporated into the film, causing deterioration of the film quality. When an appropriate heat treatment is performed on the film, the film is densified and the incorporation of oxygen and the like is prevented. The heat treatment temperature is desirably 300°C or higher, and the effect is particularly great when the temperature is raised to about 400 to 500°C. Note that even if the heat treatment temperature is less than 300° C., the effect of densification of the film by heat treatment is still present. However, if annealing is performed continuously without breaking the vacuum, the first annealing can be omitted.

[0019] Next, a second annealing is performed. The amorphous silicon film formed at a low deposition temperature is 550°C to 65°C.
When heat treatment is performed at a relatively low temperature of about 0°C for several hours to about 20 hours, hydrogen desorption and crystal growth occur, resulting in a crystal grain size of 1
Polycrystalline silicon having a large grain size of ~2 μm or more is formed. Note that in both the first annealing and the second annealing, when raising the temperature to a predetermined annealing temperature, it is not preferable to raise the temperature rapidly in a short period of time. The reason for this is that as the temperature rises (particularly when it exceeds 300° C.), hydrogen in the film is desorbed, and if the temperature rise rate is rapid, defects are likely to be formed in the film. In some cases, pinholes may form or the film may peel off. At temperatures above 300°C, the heating rate is slower than 20°C/min to 50°C/min (10°C
Gradually increasing the temperature at a heating rate slower than 1/min is particularly desirable) will reduce defects in the film.

(2) A film formed at a substrate temperature of about 150°C to 300°C has a reduced amount of hydrogen in the film compared to the amorphous silicon film formed at the above-mentioned low temperature, but hydrogen is desorbed. The temperature will shift to higher temperatures. However, since the film after formation is denser than a film formed at a low temperature, the first annealing described above can be omitted. The second annealing condition is
When heat treatment is performed at 550°C to 650°C for several hours to 20 hours, hydrogen desorption and crystal growth occur, resulting in a crystal grain size of 1
Polycrystalline silicon having a large grain size of about 2 μm is formed. In addition, the method of raising the temperature from 550℃ to 650℃ is 20℃ /
It is desirable to gradually increase the temperature at a rate slower than 50° C./min (preferably 10° C./min) because defects in the film will be reduced.

(3) When the substrate temperature exceeds 300°C, the amount of hydrogen in the film further decreases, but when annealing at about 550°C to 650°C, desorption of hydrogen becomes difficult, so the temperature is higher than the above. Heat treatment at high temperature is important.

FIG. 1(c) shows the polycrystalline silicon layer 103.
In this step, the gate insulating film 104 is formed by oxidizing the gate insulating film 104 by a thermal oxidation method. Gate oxidation temperature is 1000℃~120℃
The temperature is about 0°C. The polycrystalline silicon layer 103 is formed in step (b).
), but the crystallization rate is not necessarily high. In particular, when a silicon film (amorphous silicon or microcrystalline silicon in which a minute crystalline region exists in an amorphous phase) formed by plasma CVD is grown in solid phase by heat treatment, Its crystallization rate is not necessarily high, about 40% to 85%. Therefore, when oxidizing the polycrystalline silicon layer by thermal oxidation method,
Our studies have revealed that if the temperature is rapidly raised to a high temperature of about 1000° C. to 1200° C. in a short period of time, the crystallinity of the remaining uncrystallized region of about 60% to 15% is impaired. Although a clear causal relationship is not clear at present, when the temperature rises rapidly, (1) many crystal nuclei are generated in the uncrystallized region, and many fine crystal grains grow.

(2) Crystallization of the non-crystalline region that progresses during the temperature raising to thermal oxidation process does not progress very much.

(3) During the temperature rise, hydrogen remaining in the film is rapidly desorbed, causing defects.

Possible causes are as follows. Therefore, we
As a means to solve such problems,
We have found a method to significantly improve the crystallinity of a polycrystalline silicon layer by controlling the heating rate and heating method when raising the temperature to a thermal oxidation temperature of approximately 00°C.

[0026] Heat treatment conditions after solid phase growth in the present invention,
In particular, a method of raising the temperature to a predetermined temperature (for example, gate oxidation temperature) higher than the solid phase growth temperature will be described. (1)
At a predetermined temperature (T1), the silicon layer 102 is grown in a solid phase by annealing in an inert gas atmosphere such as argon or nitrogen to form a polycrystalline silicon layer 103, and then at a predetermined gate oxidation temperature (T2). ), the rate of temperature rise from T1 to T2 is approximately 20°C/min to 50°C/min (preferably 10°C/min).
It is desirable that the temperature increase rate be slower than 50° C./min because the crystallization rate after gate oxidation is high, and when the temperature increase rate exceeds 50° C./min, a clear deterioration of transistor characteristics was observed. There is also a method in which the atmosphere is switched from an inert gas atmosphere such as argon or nitrogen to an atmosphere containing at least one of oxygen, water vapor, hydrogen chloride, etc. during the temperature increase, and the temperature is increased while oxidation progresses. (
This method can also be applied to the temperature raising method described below. )
Note that the temperature increase rate does not always need to be constant, and may of course vary within the above-mentioned value range. Another method is to perform heat treatment at temperature T1, take out the sample, reinsert the sample into an oxidation furnace, etc. heated to a predetermined temperature (T3), and raise the temperature to T2 using a predetermined heating method (hereinafter referred to as (referred to as low-temperature insertion method)
There is also. Note that T3 is preferably between about 550°C and 1000°C. In particular, a temperature between about 700° C. and 950° C. is particularly desirable in terms of both shortening process time and improving crystallinity. This low-temperature insertion method is effective not only in the embodiment shown in FIG. 4(a) but also in other temperature raising methods. Also, by slowing down the conveyance speed when inserting the substrate into the furnace,
It is also effective to avoid rapid temperature rise of the substrate by substantially reducing the temperature rise rate of the substrate to about 20° C./min to 50° C./min or less. In this case, the temperature of the soaking section of the furnace should be 1000℃ to 12℃.
Even when the substrate was directly inserted into a furnace heated to about 00° C., almost no deterioration in transistor characteristics was observed.

(2) The polycrystalline silicon layer 1 is grown by annealing at a predetermined temperature (T1) to grow the silicon layer 102 in a solid phase.
03, followed by a predetermined gate oxidation temperature (T2)
It is also effective to increase the temperature by decreasing the rate of temperature increase on the high temperature side. In particular, in a region where the temperature exceeds approximately 900°C to 1000°C, it is desirable that the temperature increase rate be lower than 10°C/min to 20°C/min. Also, on the contrary, 800℃~900℃
If the temperature is lower than that, the temperature increase rate can be set higher than 20° C./min to 50° C./min to shorten the process time.

[0028] Such a temperature raising method is not limited to films formed by the plasma CVD method, but also applies to evaporation methods, CVD methods, EB evaporation methods,
When amorphous silicon or microcrystalline silicon is deposited by MBE method, sputtering method, etc., or when microcrystalline silicon or polycrystalline silicon is deposited by plasma CVD method, CVD method, vapor deposition method, EB vapor deposition method, MBE method, sputtering method, etc. After forming with etc., S
Formed by ion implantation of elements such as i, Ar, B, P, He, Ne, Kr, H, etc. to completely or partially amorphize the microcrystalline silicon or polycrystalline silicon, etc. It is also effective in cases where Especially, as-de
The higher the proportion of the amorphous phase in the po film and the lower the polycrystalline nucleation density (that is, the easier it is to form large-grain polycrystalline silicon by solid phase growth), the greater the effect of the present invention. .

FIG. 1(d) shows that after the gate electrode 105 is formed, the source/drain region 106 is implanted using the ion implantation method (dose 0.5 to 5×10
(about 15 cm-2, acceleration voltage about 20 to 100 keV)
This is the process of forming the film. An example of a manufacturing process is to form a gate electrode using a P-type or N-type material such as poly-Si using an LPCVD method, and then use an ion implantation method (dose of about 0.5 to 5 x 1015 cm-2, accelerating voltage 20
~100 keV), etc., and the source/drain regions are formed using the gate electrode as a mask. In this example, a CMOS type semiconductor element in which a P channel (Pch) TFT and an N channel (Nch) TFT are formed on the same substrate is formed as an example, and first, B (boron) etc. are applied over the entire surface. After ion implantation of P-type impurity (
In addition to the Pch region, the Nch region is also ion-implanted), P
The ch region is covered with a resist, and an N-type impurity such as P (phosphorus) is implanted to form an Nch TFT. Once a first conductivity type impurity is implanted over the entire surface, a predetermined region is covered with a resist, and a second impurity is implanted. Therefore, since only one photo process is required, the process is simplified and manufacturing costs can be reduced.

FIG. 1E shows a step of covering the PchTFT with a resist 111 and implanting an N-type impurity such as P (phosphorous) to form the source/drain regions 107 of the NchTFT. In the Nch source/drain region, P type impurities such as B and N type impurities such as P are mixed. Therefore, the dose of N-type impurities such as P needs to be at least two to three times the dose of P-type impurities such as B ion-implanted in step (d). In FIG. 1(f), an interlayer insulating film 108 is formed by CVD, sputtering, plasma CVD, etc., and heated to about 600°C to 1100°C for the purpose of restoring the crystallinity of the source/drain regions and activating impurities. This is a step of performing annealing, followed by opening a contact hole 109 in the interlayer insulating film and forming a wiring 110 using Al or the like. In this example, only annealing in a hydrogen gas atmosphere was performed, and no particular hydrogenation treatment such as hydrogen plasma treatment was performed. The optimum value of the activation annealing time varies depending on the annealing temperature, for example, 60
At 0°C, annealing time of about 16 to 70 hours is required, and at 900°C, annealing time of about 1 to 16 hours is required. Further, at 1000°C, an annealing time of about 15 to 30 minutes is required. Furthermore, we found that optimizing the activation annealing conditions according to the amount of F mixed in the a-Si mentioned above is important for improving TFT characteristics (particularly reducing off-state current). . The details will be discussed later.

The field effect mobility of the polycrystalline silicon TFT (N channel) manufactured by the method of manufacturing a semiconductor device based on the present invention is 150 to 200 cm2/V·sec, and the poly-Si TFT with sufficient on-current can be used. It could be formed using a simple process.

Next, the fluorine mixed into the a-Si is
The effect on characteristics (especially off-current characteristics) will be described. Hereinafter, a case will be described in which an a-Si film is formed by plasma CVD, but the film forming method is not limited thereto. When forming an a-Si film using the plasma CVD method, a trace amount of F (fluorine) may be mixed into the film. The amount is P
It varies greatly depending on conditions such as the method of cleaning the reaction chamber of the CVD apparatus and the method of cleaning and drying jigs such as substrate holders. For example, if the reaction chamber is cleaned using CF4+O2 gas and no measures are taken to remove residual fluorine, a large amount of fluorine will be mixed into the a-Si film after it has been formed.
2×1018/cm in poly-Si after TFT completion
Contains a large amount of fluorine, about 3 or more. Such a film is TF
When used in the channel region and source/drain region of T, the amount of fluorine in poly-Si is 5×1017/c.
It has been found that there is a large difference in the off-state current when the current is suppressed to about m3 or less. It has also been found that the off-state current varies greatly depending on the activation annealing conditions of the dopants in the source/drain regions. The details will be explained below based on examples.

[0033]

[Table 1]

[0034]

[Table 2]

Tables 1 and 2 show the amount of fluorine and T in the poly-Si film forming the channel region and source/drain regions.
It is a table showing the relationship with the off-state current of FT. Among them, Table 1 shows the results of Nch and Pch source/drain regions when resists are formed and ions are selectively implanted.
Table 2 shows the off-current characteristics of the Nch TFT manufactured by the manufacturing process shown in FIG. 1. The measurement conditions were an N-channel TFT (gate length 6 μm,
The gate voltage was 0V, and the drain voltage was 5V. The amount of F in the poly-Si film is a
By optimizing the removal of residual fluorine in the reaction chamber of the PCVD apparatus before -Si film formation, and the cleaning and drying of the substrate holder, etc., five levels of samples as shown in the table were prepared. Also, sauce
Also shown is the change in the off-state current value when the activation annealing conditions for the dopant in the drain region are changed to six levels (1000° C. for 20 minutes, 900° C. for 1, 5, and 16 hours, and 600° C. for 16 and 70 hours).

As is clear from comparing Tables 1 and 2, N
When a chTFT is manufactured by implanting only an N-type impurity, the off-state current tends to be lower than when a P-type impurity is implanted and then an N-type impurity is implanted. but,
The difference between the two tends to decrease as the amount of fluorine in the poly-Si film decreases. Off current is 1×10-11
Poly-Si
If the amount of fluorine present in the film is suppressed to 5 x 1017/cm3 or less, CMOS type poly
-The source and drain regions of the SiTFT are
It can be seen that it can be manufactured using only one process. In particular, the amount of fluorine is 1
When suppressed to about ×1017/cm3 or less, (1) the off-current can be reduced to 4 ×
(2) Nc can be suppressed to about 1017A or less
This is particularly desirable since it has the advantage that there is almost no difference in characteristics from the case where h and Pch ions are implanted separately. In this case, as activation annealing conditions, a relatively short annealing time such as 900° C. for 1 hour and 1000° C. for 20 minutes has the advantage that a low off-state current can be obtained. Further, even if the impurity concentration is about 1×10 18 /cm 3 , practically sufficient off-current characteristics can be obtained by performing low-temperature annealing such as 900° C. for 16 hours or 600° C. for 70 hours.

Next, a method for reducing the amount of fluorine in the film will be described using plasma CVD as an example. As mentioned above, if the reaction chamber is cleaned using CF4+O2 gas and no measures are taken to remove residual fluorine, a large amount of fluorine will be mixed into the a-Si film after it has been formed, and the Poly-Si contains a large amount of fluorine of approximately 2×10 18 /cm 3 or more. On the other hand, by implementing measures to remove residual fluorine described below, the amount of fluorine mixed into the film can be significantly reduced. (1) Cleaning the reaction chamber without using CF4+O2 gas, disassemble and remove the electrode plate, anti-adhesion plate, etc., and remove the silicon film attached to the surface by mechanical treatment such as glass bead treatment. (2)
The silicon film on jigs such as substrate holders is also removed by the above-mentioned mechanical treatment. Alternatively, in the case of washing with HF (hydrofluoric acid) or the like, residual HF is removed by baking at a temperature of about 250° C. to 300° C. or higher for about 30 minutes to about 2 hours. (3) After cleaning the reaction chamber, the reaction chamber is maintained at the substrate temperature during film formation or a slightly higher temperature for several hours, and at the same time is evacuated to a high vacuum to more completely remove residual fluorine. (4)
After cleaning, an a-Si film is formed without a substrate attached. Even if fluorine remains, if such a treatment is performed, the residual fluorine will be taken into the a-Si and adhered as a film to the substrate holder, etc., thereby having the effect of reducing the amount of residual fluorine. The film forming time is preferably about 10 minutes to 1 hour. A period of 30 minutes or more is particularly effective. (5) In order to remove fluorine (HF, etc.) adhering to the substrate, as a pretreatment for film formation, the temperature is about 250°C to 350°C or higher for 30 minutes to 20 minutes.
Anneal for about an hour. (6) Reduce impurities in raw material gas. By implementing one or more of the measures described above, the amount of fluorine in the film can be reduced to 1 x 1018/cm3, 5 x 101
7/cm3 and 1×1017/cm3 or less.

As described above, by reducing the amount of fluorine in poly-Si, the off-state current of a poly-Si TFT can be significantly reduced. It has also been found that a method of lowering the activation annealing temperature is also effective in reducing off-state current. Although the causal relationship between the amount of fluorine and the off-state current, the activation annealing method, and the off-state current has not been clearly elucidated at present, the following mechanism is presumed. First, the off-state current of a poly-Si TFT is caused by the current generated via the defect level at the drain end and the field-
Enhanced-Emission current is considered to be dominant. Therefore, it is easily inferred that reducing the density of defect levels at the drain end is effective in reducing the off-state current. In order to reduce the defect levels at the drain end, it is essential to improve the crystallinity of the poly-Si film near the drain end. Therefore, we have determined that the amount of fluorine in the film and the activation annealing after ion implantation are
It is speculated that there is a strong correlation with the crystallinity of the ly-Si film. After ion implantation in the steps shown in FIGS. 1(d) and 1(e), activation annealing is performed in the step shown in FIG. 1(f) to improve the crystallinity of the region into which impurity ions have been implanted. Recovery (at least a portion of the poly-Si film in the source/drain region is made amorphous by ion implantation, and by activation annealing, crystals grow and become poly-Si again) and activation of impurities are performed. At that time, poly-S
If fluorine exists in the i-film, the crystallinity cannot be recovered sufficiently by activation annealing, and the poly
-The crystallinity of the Si film decreases, resulting in a film with many defect levels. As a result, it is presumed that the off-state current increases due to the above-described mechanism. Therefore, the amount of fluorine in poly-Si is 2×1018/cm3, 1×1018/cm3, 5×
1017/cm3, 1×1017/cm3 using ESR for the defect density of the impurity implanted region after activation annealing.
(electron spin resonance). As a result, the amount of fluorine was 2×1018/cm3, 1×1018/cm3, 5
For the films of ×1017/cm3 and 1×1017/cm3, the spin density is 1.5×1019/cm3, respectively.
, 4.5×1018/cm3, 3.9×1017/cm
A value of 3.8.7×10 16 /cm 3 was obtained. The activation annealing conditions for this sample are 1000℃20
It's a minute. This result shows that a film with a large amount of fluorine has a high defect density. This result supports the above-mentioned speculation about the correlation between the amount of fluorine and the off-state current, and when combined with the off-current measurement results shown in Table 2, the spin density in the source/drain region is 1×101
8/cm3 or less, and 1×1017/cm3 or less.
It is particularly desirable that it be below cm3.

Note that the present invention is based on the TF shown in the embodiment of FIG.
In addition to T, it can be applied to insulated gate type semiconductor devices in general.

[0040]

As described above, according to the present invention, insulated gate field effect transistors such as poly-Si TFTs having low off-state current and high mobility can be manufactured using a simple manufacturing method. As a result, it has become possible to form high-performance semiconductor elements on insulating amorphous materials, and it has become possible to use large, high-resolution liquid crystal display panels, high-speed, high-resolution contact image sensors, and TFTs as load parts. Three-dimensional ICs such as SRAM can now be easily manufactured.

[Brief explanation of the drawing]

FIG. 1 is a manufacturing process diagram of a semiconductor device in an embodiment of the present invention.

[Explanation of symbols]

101... Insulating amorphous material 102... Silicon layer 103... Polycrystalline silicon layer 104... Gate insulating film 105... Gate electrodes 106, 107... Source/drain region 10
8... Interlayer insulating film 109... Contact hole 110... Wiring

Claims (6)

[Claims] 1. In a semiconductor device in which at least a part of a channel region of an insulated gate field effect transistor is formed of a non-single crystal semiconductor, the amount of fluorine in the non-single crystal semiconductor is 1×10 18 /cm 3 or less. Characteristic semiconductor devices. 2. The semiconductor device according to claim 1, wherein the non-single crystal semiconductor is polycrystalline silicon. 3. A method for manufacturing a CMOS type semiconductor device in which at least a part of the channel region of an insulated gate field effect transistor is formed of a non-single crystal semiconductor, comprising: (a) silicon on an insulating amorphous material; (b) Step of ion-implanting impurities of a first conductivity type to form a source/drain region; (c) Step of ion-implanting impurities of a second conductivity type to form a source/drain region. (d) an annealing step for activating the ion-implanted dopant, and one of the first impurity ion implantation or the second impurity ion implantation is performed. Ion implantation is performed over almost the entire surface of the substrate, and ions are implanted only into a predetermined region on the other side, and the amount of fluorine in the non-single crystal semiconductor after the transistor is completed is 1×10 18 /cm 3 or less. A method for manufacturing a semiconductor device. 4. The annealing for activation is performed at 900°C.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the manufacturing method is performed at a temperature of .degree. C. or lower. 5. The amount of fluorine in the non-single crystal semiconductor is 5×
Claim 3 characterized in that it is 1017/cm3 or less.
A method of manufacturing the semiconductor device described above. 6. The annealing for activation is 100%
6. The method of manufacturing a semiconductor device according to claim 5, wherein the manufacturing method is performed at a temperature of 0° C. or lower.